[AArch64, 5/6] Enable BTI : Add new pass for BTI.
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch adds a new pass called "bti" which is triggered by the command
line argument -mbranch-protection whenever "bti" is turned on.
The pass iterates through the instructions and adds appropriated BTI
instructions based on the following:
* Add a new "BTI C" at the beginning of a function, unless its already
protected by a "PACIASP". We exempt the functions that are only called
directly.
* Add a new "BTI J" for every target of an indirect jump, jump table
targets, non-local goto targets or labels that might be referenced by
variables, constant pools, etc (NOTE_INSN_DELETED_LABEL).
Since we have already changed the use of indirect tail calls to only x16 and
x17, we do not have to use "BTI JC".
(check patch 3/6).
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config.gcc (aarch64*-*-*): Add aarch64-bti-insert.o.
* gcc/config/aarch64/aarch64.h: Update comment for TRAMPOLINE_SIZE.
* config/aarch64/aarch64.c (aarch64_asm_trampoline_template): Update
if bti is enabled.
* config/aarch64/aarch64-bti-insert.c: New file.
* config/aarch64/aarch64-passes.def (INSERT_PASS_BEFORE): Insert bti
pass.
* config/aarch64/aarch64-protos.h (make_pass_insert_bti): Declare the
new bti pass.
* config/aarch64/aarch64.md (unspecv): Add UNSPECV_BTI_NOARG,
UNSPECV_BTI_C, UNSPECV_BTI_J and UNSPECV_BTI_JC.
(bti_noarg, bti_j, bti_c, bti_jc): New define_insns.
* config/aarch64/t-aarch64: Add rule for aarch64-bti-insert.o.
*** gcc/testsuite/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/bti-1.c: New test.
* gcc.target/aarch64/bti-2.c: New test.
* gcc.target/aarch64/bti-3.c: New test.
* lib/target-supports.exp
(check_effective_target_aarch64_bti_hw): Add new check for BTI hw.
Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
From-SVN: r267769
This commit is contained in:
Sudakshina Das
Sudakshina Das
parent
30afdf34a6
commit
b5f794b47b
14 changed files with 490 additions and 7 deletions
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@ -1,3 +1,20 @@
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2018-01-09 Sudakshina Das <sudi.das@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* config.gcc (aarch64*-*-*): Add aarch64-bti-insert.o.
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* gcc/config/aarch64/aarch64.h: Update comment for TRAMPOLINE_SIZE.
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* config/aarch64/aarch64.c (aarch64_asm_trampoline_template): Update
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if bti is enabled.
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* config/aarch64/aarch64-bti-insert.c: New file.
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* config/aarch64/aarch64-passes.def (INSERT_PASS_BEFORE): Insert bti
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pass.
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* config/aarch64/aarch64-protos.h (make_pass_insert_bti): Declare the
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new bti pass.
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* config/aarch64/aarch64.md (unspecv): Add UNSPECV_BTI_NOARG,
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UNSPECV_BTI_C, UNSPECV_BTI_J and UNSPECV_BTI_JC.
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(bti_noarg, bti_j, bti_c, bti_jc): New define_insns.
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* config/aarch64/t-aarch64: Add rule for aarch64-bti-insert.o.
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2018-01-09 Sudakshina Das <sudi.das@arm.com>
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* config/aarch64/aarch64-protos.h (aarch64_bti_enabled): Declare.
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@ -318,7 +318,7 @@ aarch64*-*-*)
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c_target_objs="aarch64-c.o"
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cxx_target_objs="aarch64-c.o"
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d_target_objs="aarch64-d.o"
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extra_objs="aarch64-builtins.o aarch-common.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o"
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extra_objs="aarch64-builtins.o aarch-common.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch64-bti-insert.o"
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target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.c"
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target_has_targetm_common=yes
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;;
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235
gcc/config/aarch64/aarch64-bti-insert.c
Normal file
235
gcc/config/aarch64/aarch64-bti-insert.c
Normal file
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@ -0,0 +1,235 @@
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/* Branch Target Identification for AArch64 architecture.
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Copyright (C) 2019 Free Software Foundation, Inc.
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Contributed by Arm Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#define IN_TARGET_CODE 1
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#include "config.h"
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#define INCLUDE_STRING
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#include "system.h"
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#include "coretypes.h"
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#include "backend.h"
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#include "target.h"
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#include "rtl.h"
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#include "tree.h"
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#include "memmodel.h"
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#include "gimple.h"
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#include "tm_p.h"
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#include "stringpool.h"
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#include "attribs.h"
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#include "emit-rtl.h"
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#include "gimplify.h"
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#include "gimple-iterator.h"
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#include "dumpfile.h"
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#include "rtl-iter.h"
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#include "cfgrtl.h"
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#include "tree-pass.h"
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#include "cgraph.h"
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/* This pass enables the support for Branch Target Identification Mechanism
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for AArch64. This is a new security feature introduced in ARMv8.5-A
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archtitecture. A BTI instruction is used to guard against the execution
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of instructions which are not the intended target of an indirect branch.
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Outside of a guarded memory region, a BTI instruction executes as a NOP.
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Within a guarded memory region any target of an indirect branch must be
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a compatible BTI or BRK, HLT, PACIASP, PACIBASP instruction (even if the
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branch is triggered in a non-guarded memory region). An incompatibility
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generates a Branch Target Exception.
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The compatibility of the BTI instruction is as follows:
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BTI j : Can be a target of any indirect jump (BR Xn).
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BTI c : Can be a target of any indirect call (BLR Xn and BR X16/X17).
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BTI jc: Can be a target of any indirect call or indirect jump.
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BTI : Can not be a target of any indirect call or indirect jump.
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In order to enable this mechanism, this pass iterates through the
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control flow of the code and adds appropriate BTI instructions :
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* Add a new "BTI C" at the beginning of a function, unless its already
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protected by a "PACIASP/PACIBSP". We exempt the functions that are only
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called directly.
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* Add a new "BTI J" for every target of an indirect jump, jump table targets,
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non-local goto targets or labels that might be referenced by variables,
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constant pools, etc (NOTE_INSN_DELETED_LABEL)
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Since we have already changed the use of indirect tail calls to only x16
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and x17, we do not have to use "BTI JC".
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This pass is triggered by the command line option -mbranch-protection=bti or
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-mbranch-protection=standard. Since all the BTI instructions are in the HINT
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space, this pass does not require any minimum architecture version. */
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namespace {
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const pass_data pass_data_insert_bti =
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{
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RTL_PASS, /* type. */
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"bti", /* name. */
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OPTGROUP_NONE, /* optinfo_flags. */
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TV_MACH_DEP, /* tv_id. */
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0, /* properties_required. */
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0, /* properties_provided. */
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0, /* properties_destroyed. */
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0, /* todo_flags_start. */
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0, /* todo_flags_finish. */
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};
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/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */
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static bool
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aarch64_pac_insn_p (rtx x)
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{
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if (!INSN_P (x))
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return x;
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subrtx_var_iterator::array_type array;
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FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL)
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{
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rtx sub = *iter;
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if (sub && GET_CODE (sub) == UNSPEC)
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{
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int unspec_val = XINT (sub, 1);
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switch (unspec_val)
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{
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case UNSPEC_PACISP:
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return true;
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default:
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return false;
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}
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iter.skip_subrtxes ();
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}
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}
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return false;
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}
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/* Insert the BTI instruction. */
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/* This is implemented as a late RTL pass that runs before branch
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shortening and does the following. */
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static unsigned int
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rest_of_insert_bti (void)
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{
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timevar_push (TV_MACH_DEP);
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rtx bti_insn;
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rtx_insn *insn;
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basic_block bb;
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/* Since a Branch Target Exception can only be triggered by an indirect call,
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we exempt function that are only called directly. We also exempt
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functions that are already protected by Return Address Signing (PACIASP/
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PACIBSP). For all other cases insert a BTI C at the beginning of the
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function. */
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if (!cgraph_node::get (cfun->decl)->only_called_directly_p ())
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{
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bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
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insn = BB_HEAD (bb);
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if (!aarch64_pac_insn_p (get_first_nonnote_insn ()))
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{
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bti_insn = gen_bti_c ();
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emit_insn_before (bti_insn, insn);
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}
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}
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bb = 0;
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FOR_EACH_BB_FN (bb, cfun)
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{
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for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
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insn = NEXT_INSN (insn))
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{
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/* If a label is marked to be preserved or can be a non-local goto
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target, it must be protected with a BTI J. The same applies to
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NOTE_INSN_DELETED_LABEL since they are basically labels that might
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be referenced via variables or constant pool. */
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if ((LABEL_P (insn)
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&& (LABEL_PRESERVE_P (insn)
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|| bb->flags & BB_NON_LOCAL_GOTO_TARGET))
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|| (NOTE_P (insn)
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&& NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
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{
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bti_insn = gen_bti_j ();
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emit_insn_after (bti_insn, insn);
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continue;
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}
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/* There could still be more labels that are valid targets of a
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BTI J instuction. To find them we start looking through the
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JUMP_INSN. If it jumps to a jump table, then we find all labels
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of the jump table to protect with a BTI J. */
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if (JUMP_P (insn))
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{
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rtx_jump_table_data *table;
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if (tablejump_p (insn, NULL, &table))
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{
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rtvec vec = table->get_labels ();
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int j;
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rtx_insn *label;
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for (j = GET_NUM_ELEM (vec) - 1; j >= 0; --j)
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{
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label = as_a <rtx_insn *> (XEXP (RTVEC_ELT (vec, j), 0));
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bti_insn = gen_bti_j ();
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emit_insn_after (bti_insn, label);
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}
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}
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}
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/* Also look for calls to setjmp () which would be marked with
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REG_SETJMP note and put a BTI J after. This is where longjump ()
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will return. */
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if (CALL_P (insn) && (find_reg_note (insn, REG_SETJMP, NULL)))
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{
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bti_insn = gen_bti_j ();
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emit_insn_after (bti_insn, insn);
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continue;
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}
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}
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}
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timevar_pop (TV_MACH_DEP);
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return 0;
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}
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class pass_insert_bti : public rtl_opt_pass
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{
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public:
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pass_insert_bti (gcc::context *ctxt)
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: rtl_opt_pass (pass_data_insert_bti, ctxt)
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{}
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/* opt_pass methods: */
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virtual bool gate (function *)
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{
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return aarch64_bti_enabled ();
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}
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virtual unsigned int execute (function *)
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{
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return rest_of_insert_bti ();
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}
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}; // class pass_insert_bti
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} // anon namespace
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rtl_opt_pass *
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make_pass_insert_bti (gcc::context *ctxt)
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{
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return new pass_insert_bti (ctxt);
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}
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@ -21,3 +21,4 @@
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INSERT_PASS_AFTER (pass_regrename, 1, pass_fma_steering);
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INSERT_PASS_BEFORE (pass_reorder_blocks, 1, pass_track_speculation);
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INSERT_PASS_AFTER (pass_machine_reorg, 1, pass_tag_collision_avoidance);
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INSERT_PASS_BEFORE (pass_shorten_branches, 1, pass_insert_bti);
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@ -633,6 +633,7 @@ extern void aarch64_d_target_versions (void);
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rtl_opt_pass *make_pass_fma_steering (gcc::context *);
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rtl_opt_pass *make_pass_track_speculation (gcc::context *);
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rtl_opt_pass *make_pass_tag_collision_avoidance (gcc::context *);
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rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt);
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poly_uint64 aarch64_regmode_natural_size (machine_mode);
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@ -8250,18 +8250,36 @@ aarch64_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
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static void
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aarch64_asm_trampoline_template (FILE *f)
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{
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int offset1 = 16;
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int offset2 = 20;
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if (aarch64_bti_enabled ())
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{
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asm_fprintf (f, "\thint\t34 // bti c\n");
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offset1 -= 4;
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offset2 -= 4;
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}
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if (TARGET_ILP32)
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{
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asm_fprintf (f, "\tldr\tw%d, .+16\n", IP1_REGNUM - R0_REGNUM);
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asm_fprintf (f, "\tldr\tw%d, .+16\n", STATIC_CHAIN_REGNUM - R0_REGNUM);
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asm_fprintf (f, "\tldr\tw%d, .+%d\n", IP1_REGNUM - R0_REGNUM, offset1);
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asm_fprintf (f, "\tldr\tw%d, .+%d\n", STATIC_CHAIN_REGNUM - R0_REGNUM,
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offset1);
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}
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else
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{
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asm_fprintf (f, "\tldr\t%s, .+16\n", reg_names [IP1_REGNUM]);
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asm_fprintf (f, "\tldr\t%s, .+20\n", reg_names [STATIC_CHAIN_REGNUM]);
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asm_fprintf (f, "\tldr\t%s, .+%d\n", reg_names [IP1_REGNUM], offset1);
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asm_fprintf (f, "\tldr\t%s, .+%d\n", reg_names [STATIC_CHAIN_REGNUM],
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offset2);
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}
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asm_fprintf (f, "\tbr\t%s\n", reg_names [IP1_REGNUM]);
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assemble_aligned_integer (4, const0_rtx);
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/* The trampoline needs an extra padding instruction. In case if BTI is
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enabled the padding instruction is replaced by the BTI instruction at
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the beginning. */
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if (!aarch64_bti_enabled ())
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assemble_aligned_integer (4, const0_rtx);
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assemble_aligned_integer (POINTER_BYTES, const0_rtx);
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assemble_aligned_integer (POINTER_BYTES, const0_rtx);
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}
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@ -918,7 +918,7 @@ typedef struct
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#define RETURN_ADDR_RTX aarch64_return_addr
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/* 3 insns + padding + 2 pointer-sized entries. */
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/* BTI c + 3 insns + 2 pointer-sized entries. */
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#define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32)
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/* Trampolines contain dwords, so must be dword aligned. */
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@ -237,6 +237,10 @@
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UNSPECV_BLOCKAGE ; Represent a blockage
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UNSPECV_PROBE_STACK_RANGE ; Represent stack range probing.
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UNSPECV_SPECULATION_BARRIER ; Represent speculation barrier.
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UNSPECV_BTI_NOARG ; Represent BTI.
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UNSPECV_BTI_C ; Represent BTI c.
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UNSPECV_BTI_J ; Represent BTI j.
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UNSPECV_BTI_JC ; Represent BTI jc.
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]
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)
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@ -6939,6 +6943,35 @@
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[(set_attr "type" "csel")]
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)
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;; BTI <target> instructions
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(define_insn "bti_noarg"
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[(unspec_volatile [(const_int 0)] UNSPECV_BTI_NOARG)]
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""
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"hint\t32 // bti"
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[(set_attr "type" "no_insn")]
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)
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(define_insn "bti_c"
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[(unspec_volatile [(const_int 0)] UNSPECV_BTI_C)]
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""
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"hint\t34 // bti c"
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[(set_attr "type" "no_insn")]
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)
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(define_insn "bti_j"
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[(unspec_volatile [(const_int 0)] UNSPECV_BTI_J)]
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""
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"hint\t36 // bti j"
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[(set_attr "type" "no_insn")]
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)
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(define_insn "bti_jc"
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[(unspec_volatile [(const_int 0)] UNSPECV_BTI_JC)]
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""
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"hint\t38 // bti jc"
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[(set_attr "type" "no_insn")]
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)
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;; Helper for aarch64.c code.
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(define_expand "set_clobber_cc"
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[(parallel [(set (match_operand 0)
|
||||
|
|
|
|||
|
|
@ -91,6 +91,15 @@ falkor-tag-collision-avoidance.o: \
|
|||
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
|
||||
$(srcdir)/config/aarch64/falkor-tag-collision-avoidance.c
|
||||
|
||||
aarch64-bti-insert.o: $(srcdir)/config/aarch64/aarch64-bti-insert.c \
|
||||
$(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \
|
||||
dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \
|
||||
output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \
|
||||
$(CONTEXT_H) $(TREE_PASS_H) regrename.h \
|
||||
$(srcdir)/config/aarch64/aarch64-protos.h
|
||||
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
|
||||
$(srcdir)/config/aarch64/aarch64-bti-insert.c
|
||||
|
||||
comma=,
|
||||
MULTILIB_OPTIONS = $(subst $(comma),/, $(patsubst %, mabi=%, $(subst $(comma),$(comma)mabi=,$(TM_MULTILIB_CONFIG))))
|
||||
MULTILIB_DIRNAMES = $(subst $(comma), ,$(TM_MULTILIB_CONFIG))
|
||||
|
|
|
|||
|
|
@ -1,3 +1,11 @@
|
|||
2018-01-09 Sudakshina Das <sudi.das@arm.com>
|
||||
|
||||
* gcc.target/aarch64/bti-1.c: New test.
|
||||
* gcc.target/aarch64/bti-2.c: New test.
|
||||
* gcc.target/aarch64/bti-3.c: New test.
|
||||
* lib/target-supports.exp
|
||||
(check_effective_target_aarch64_bti_hw): Add new check for BTI hw.
|
||||
|
||||
2018-01-09 Sudakshina Das <sudi.das@arm.com>
|
||||
|
||||
* gcc.target/aarch64/test_frame_17.c: Update to check for EP0_REGNUM
|
||||
|
|
|
|||
59
gcc/testsuite/gcc.target/aarch64/bti-1.c
Normal file
59
gcc/testsuite/gcc.target/aarch64/bti-1.c
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/* { dg-do compile } */
|
||||
/* -Os to create jump table. */
|
||||
/* { dg-options "-Os -mbranch-protection=standard" } */
|
||||
|
||||
extern int f1 (void);
|
||||
extern int f2 (void);
|
||||
extern int f3 (void);
|
||||
extern int f4 (void);
|
||||
extern int f5 (void);
|
||||
extern int f6 (void);
|
||||
extern int f7 (void);
|
||||
extern int f8 (void);
|
||||
extern int f9 (void);
|
||||
extern int f10 (void);
|
||||
|
||||
int (*ptr) (void);
|
||||
|
||||
int
|
||||
f_jump_table (int y, int n)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < n ;i ++)
|
||||
{
|
||||
switch (y)
|
||||
{
|
||||
case 0 : ptr = f1; break;
|
||||
case 1 : ptr = f2; break;
|
||||
case 2 : ptr = f3; break;
|
||||
case 3 : ptr = f4; break;
|
||||
case 4 : ptr = f5; break;
|
||||
case 5 : ptr = f6; break;
|
||||
case 6 : ptr = f7; break;
|
||||
case 7 : ptr = f8; break;
|
||||
case 8 : ptr = f9; break;
|
||||
case 9 : ptr = f10; break;
|
||||
default: break;
|
||||
}
|
||||
y += ptr ();
|
||||
}
|
||||
return (y == 0)? y+1:4;
|
||||
}
|
||||
/* f_jump_table should have PACIASP and AUTIASP. */
|
||||
/* { dg-final { scan-assembler-times "hint\t25" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "hint\t29" 1 } } */
|
||||
|
||||
int
|
||||
f_label_address ()
|
||||
{
|
||||
static void * addr = &&lab1;
|
||||
goto *addr;
|
||||
lab1:
|
||||
addr = &&lab2;
|
||||
return 1;
|
||||
lab2:
|
||||
addr = &&lab1;
|
||||
return 2;
|
||||
}
|
||||
/* { dg-final { scan-assembler-times "hint\t34" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "hint\t36" 12 } } */
|
||||
34
gcc/testsuite/gcc.target/aarch64/bti-2.c
Normal file
34
gcc/testsuite/gcc.target/aarch64/bti-2.c
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target aarch64_bti_hw } */
|
||||
/* { dg-options "-mbranch-protection=standard" } */
|
||||
|
||||
#include<stdio.h>
|
||||
|
||||
typedef int FP (int);
|
||||
|
||||
int
|
||||
f1 (FP fp, int n)
|
||||
{
|
||||
return (fp) (n);
|
||||
}
|
||||
|
||||
int
|
||||
f2 (int n, FP fp)
|
||||
{
|
||||
return (fp) (n);
|
||||
}
|
||||
|
||||
int __attribute__ ((noinline))
|
||||
func (int x)
|
||||
{
|
||||
return x+1;
|
||||
}
|
||||
|
||||
int main ()
|
||||
{
|
||||
int s = 0;
|
||||
s += f1 (func, 10);
|
||||
s += f2 (s, func);
|
||||
printf ("S: %d\n", s);
|
||||
return !(s == 23);
|
||||
}
|
||||
52
gcc/testsuite/gcc.target/aarch64/bti-3.c
Normal file
52
gcc/testsuite/gcc.target/aarch64/bti-3.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/* This is a copy of gcc/testsuite/gcc.c-torture/execute/pr56982.c to test the
|
||||
setjmp case of the bti pass. */
|
||||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target aarch64_bti_hw } */
|
||||
/* { dg-options "--save-temps -mbranch-protection=standard" } */
|
||||
|
||||
#include <setjmp.h>
|
||||
|
||||
extern void abort (void);
|
||||
extern void exit (int);
|
||||
|
||||
static jmp_buf env;
|
||||
|
||||
void baz (void)
|
||||
{
|
||||
__asm__ volatile ("" : : : "memory");
|
||||
}
|
||||
|
||||
static inline int g(int x)
|
||||
{
|
||||
if (x)
|
||||
{
|
||||
baz();
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
baz();
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
int f(int *e)
|
||||
{
|
||||
if (*e)
|
||||
return 1;
|
||||
|
||||
int x = setjmp(env);
|
||||
int n = g(x);
|
||||
if (n == 0)
|
||||
exit(0);
|
||||
if (x)
|
||||
abort();
|
||||
longjmp(env, 42);
|
||||
}
|
||||
/* { dg-final { scan-assembler "hint\t36" } } */
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
int v = 0;
|
||||
return f(&v);
|
||||
}
|
||||
|
|
@ -4313,6 +4313,22 @@ proc check_effective_target_arm_neonv2_hw { } {
|
|||
} [add_options_for_arm_neonv2 ""]]
|
||||
}
|
||||
|
||||
# ID_AA64PFR1_EL1.BT using bits[3:0] == 1 implies BTI implimented.
|
||||
proc check_effective_target_aarch64_bti_hw { } {
|
||||
if { ![istarget aarch64*-*-*] } {
|
||||
return 0
|
||||
}
|
||||
return [check_runtime aarch64_bti_hw_available {
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
int a;
|
||||
asm volatile ("mrs %0, id_aa64pfr1_el1" : "=r" (a));
|
||||
return !((a & 0xf) == 1);
|
||||
}
|
||||
} "-O2" ]
|
||||
}
|
||||
|
||||
# Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
|
||||
# otherwise. The test is valid for AArch64 and ARM. Record the command
|
||||
# line options needed.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue