Support signbit/xorsign/copysign/abs/neg/and/xor/ior/andn for V2HF/V4HF.
gcc/ChangeLog: * config/i386/i386.cc (ix86_build_const_vector): Handle V2HF and V4HFmode. (ix86_build_signbit_mask): Ditto. * config/i386/mmx.md (mmxintvecmode): Ditto. (<code><mode>2): New define_expand. (*mmx_<code><mode>): New define_insn_and_split. (*mmx_nabs<mode>2): Ditto. (*mmx_andnot<mode>3): New define_insn. (<code><mode>3): Ditto. (copysign<mode>3): New define_expand. (xorsign<mode>3): Ditto. (signbit<mode>2): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/part-vect-absneghf.c: New test. * gcc.target/i386/part-vect-copysignhf.c: New test. * gcc.target/i386/part-vect-xorsignhf.c: New test.
This commit is contained in:
liuhongt
parent
91fdbd650d
commit
b4fc1abbd9
5 changed files with 328 additions and 1 deletions
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@ -15894,6 +15894,8 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value)
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case E_V2DImode:
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gcc_assert (vect);
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/* FALLTHRU */
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case E_V2HFmode:
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case E_V4HFmode:
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case E_V8HFmode:
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case E_V16HFmode:
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case E_V32HFmode:
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@ -15935,6 +15937,8 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert)
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switch (mode)
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{
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case E_V2HFmode:
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case E_V4HFmode:
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case E_V8HFmode:
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case E_V16HFmode:
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case E_V32HFmode:
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@ -99,7 +99,8 @@
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;; Mapping of vector float modes to an integer mode of the same size
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(define_mode_attr mmxintvecmode
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[(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")])
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[(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")
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(V4HF "V4HF") (V2HF "V2HI")])
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(define_mode_attr mmxintvecmodelower
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[(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")])
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@ -2052,6 +2053,117 @@
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DONE;
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})
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(define_expand "<code><mode>2"
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[(set (match_operand:VHF_32_64 0 "register_operand")
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(absneg:VHF_32_64
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(match_operand:VHF_32_64 1 "register_operand")))]
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"TARGET_SSE"
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"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
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(define_insn_and_split "*mmx_<code><mode>"
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[(set (match_operand:VHF_32_64 0 "register_operand" "=x,x,x")
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(absneg:VHF_32_64
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(match_operand:VHF_32_64 1 "register_operand" "0,x,x")))
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(use (match_operand:VHF_32_64 2 "register_operand" "x,0,x"))]
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"TARGET_SSE"
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"#"
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"&& reload_completed"
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[(set (match_dup 0)
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(<absneg_op>:<MODE> (match_dup 1) (match_dup 2)))]
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{
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if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
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std::swap (operands[1], operands[2]);
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}
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[(set_attr "isa" "noavx,noavx,avx")])
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(define_insn_and_split "*mmx_nabs<mode>2"
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[(set (match_operand:VHF_32_64 0 "register_operand" "=x,x,x")
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(neg:VHF_32_64
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(abs:VHF_32_64
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(match_operand:VHF_32_64 1 "register_operand" "0,x,x"))))
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(use (match_operand:VHF_32_64 2 "register_operand" "x,0,x"))]
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"TARGET_SSE"
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"#"
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"&& reload_completed"
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[(set (match_dup 0)
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(ior:<MODE> (match_dup 1) (match_dup 2)))])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Parallel half-precision floating point logical operations
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn "*mmx_andnot<mode>3"
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[(set (match_operand:VHF_32_64 0 "register_operand" "=x,x")
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(and:VHF_32_64
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(not:VHF_32_64
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(match_operand:VHF_32_64 1 "register_operand" "0,x"))
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(match_operand:VHF_32_64 2 "register_operand" "x,x")))]
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"TARGET_SSE"
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"@
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andnps\t{%2, %0|%0, %2}
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vandnps\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "V4SF")])
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(define_insn "<code><mode>3"
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[(set (match_operand:VHF_32_64 0 "register_operand" "=x,x")
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(any_logic:VHF_32_64
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(match_operand:VHF_32_64 1 "register_operand" "%0,x")
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(match_operand:VHF_32_64 2 "register_operand" " x,x")))]
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"TARGET_SSE"
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"@
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<logic>ps\t{%2, %0|%0, %2}
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v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog,sselog")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "V4SF")])
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(define_expand "copysign<mode>3"
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[(set (match_dup 4)
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(and:VHF_32_64
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(not:VHF_32_64 (match_dup 3))
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(match_operand:VHF_32_64 1 "register_operand")))
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(set (match_dup 5)
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(and:VHF_32_64 (match_dup 3)
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(match_operand:VHF_32_64 2 "register_operand")))
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(set (match_operand:VHF_32_64 0 "register_operand")
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(ior:VHF_32_64 (match_dup 4) (match_dup 5)))]
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"TARGET_SSE"
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{
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operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
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operands[4] = gen_reg_rtx (<MODE>mode);
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operands[5] = gen_reg_rtx (<MODE>mode);
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})
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(define_expand "xorsign<mode>3"
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[(set (match_dup 4)
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(and:VHF_32_64 (match_dup 3)
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(match_operand:VHF_32_64 2 "register_operand")))
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(set (match_operand:VHF_32_64 0 "register_operand")
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(xor:VHF_32_64 (match_dup 4)
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(match_operand:VHF_32_64 1 "register_operand")))]
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"TARGET_SSE"
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{
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operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
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operands[4] = gen_reg_rtx (<MODE>mode);
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})
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(define_expand "signbit<mode>2"
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[(set (match_operand:<mmxintvecmode> 0 "register_operand")
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(lshiftrt:<mmxintvecmode>
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(subreg:<mmxintvecmode>
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(match_operand:VHF_32_64 1 "register_operand") 0)
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(match_dup 2)))]
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"TARGET_SSE2"
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"operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Parallel integral arithmetic
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91
gcc/testsuite/gcc.target/i386/part-vect-absneghf.c
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91
gcc/testsuite/gcc.target/i386/part-vect-absneghf.c
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@ -0,0 +1,91 @@
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/* { dg-do run { target avx512fp16 } } */
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/* { dg-options "-O1 -mavx512fp16 -mavx512vl -ftree-vectorize -fdump-tree-slp-details -fdump-tree-optimized" } */
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extern void abort ();
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static void do_test (void);
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#define DO_TEST do_test
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#define AVX512FP16
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#include "avx512-check.h"
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#define N 16
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_Float16 a[N] = {-0.1f, -3.2f, -6.3f, -9.4f,
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-12.5f, -15.6f, -18.7f, -21.8f,
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24.9f, 27.1f, 30.2f, 33.3f,
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36.4f, 39.5f, 42.6f, 45.7f};
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_Float16 b[N] = {-1.2f, 3.4f, -5.6f, 7.8f,
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-9.0f, 1.0f, -2.0f, 3.0f,
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-4.0f, -5.0f, 6.0f, 7.0f,
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-8.0f, -9.0f, 10.0f, 11.0f};
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_Float16 r[N];
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void
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__attribute__((noipa,noinline,optimize("O2")))
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abs_32 (void)
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{
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r[0] = __builtin_fabsf16 (b[0]);
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r[1] = __builtin_fabsf16 (b[1]);
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}
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void
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__attribute__((noipa,noinline,optimize("O2")))
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abs_64 (void)
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{
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r[0] = __builtin_fabsf16 (b[0]);
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r[1] = __builtin_fabsf16 (b[1]);
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r[2] = __builtin_fabsf16 (b[2]);
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r[3] = __builtin_fabsf16 (b[3]);
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}
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void
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__attribute__((noipa,noinline,optimize("O2")))
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neg_32 (void)
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{
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r[0] = -b[0];
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r[1] = -b[1];
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}
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void
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__attribute__((noipa,noinline,optimize("O2")))
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neg_64 (void)
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{
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r[0] = -b[0];
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r[1] = -b[1];
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r[2] = -b[2];
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r[3] = -b[3];
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}
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static void
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__attribute__ ((noinline, noclone))
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do_test (void)
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{
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abs_32 ();
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/* check results: */
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for (int i = 0; i != 2; i++)
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if (r[i] != __builtin_fabsf16 (b[i]))
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abort ();
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abs_64 ();
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/* check results: */
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for (int i = 0; i != 4; i++)
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if (r[i] != __builtin_fabsf16 (b[i]))
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abort ();
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neg_32 ();
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/* check results: */
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for (int i = 0; i != 2; i++)
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if (r[i] != -b[i])
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abort ();
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neg_64 ();
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/* check results: */
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for (int i = 0; i != 4; i++)
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if (r[i] != -b[i])
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abort ();
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}
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/* { dg-final { scan-tree-dump-times "vectorized using 8 byte vectors" 2 "slp2" } } */
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/* { dg-final { scan-tree-dump-times "vectorized using 4 byte vectors" 2 "slp2" } } */
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/* { dg-final { scan-tree-dump-times {(?n)ABS_EXPR <vect} 2 "optimized" { target { ! ia32 } } } } */
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/* { dg-final { scan-tree-dump-times {(?n)= -vect} 2 "optimized" { target { ! ia32 } } } } */
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60
gcc/testsuite/gcc.target/i386/part-vect-copysignhf.c
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60
gcc/testsuite/gcc.target/i386/part-vect-copysignhf.c
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@ -0,0 +1,60 @@
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/* { dg-do run { target avx512fp16 } } */
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/* { dg-options "-O1 -mavx512fp16 -mavx512vl -ftree-vectorize -fdump-tree-slp-details -fdump-tree-optimized" } */
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extern void abort ();
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static void do_test (void);
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#define DO_TEST do_test
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#define AVX512FP16
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#include "avx512-check.h"
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#define N 16
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_Float16 a[N] = {-0.1f, -3.2f, -6.3f, -9.4f,
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-12.5f, -15.6f, -18.7f, -21.8f,
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24.9f, 27.1f, 30.2f, 33.3f,
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36.4f, 39.5f, 42.6f, 45.7f};
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_Float16 b[N] = {-1.2f, 3.4f, -5.6f, 7.8f,
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-9.0f, 1.0f, -2.0f, 3.0f,
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-4.0f, -5.0f, 6.0f, 7.0f,
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-8.0f, -9.0f, 10.0f, 11.0f};
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_Float16 r[N];
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void
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__attribute__((noipa,noinline,optimize("O2")))
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copysign_32 (void)
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{
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r[0] = __builtin_copysignf16 (1.0f, b[0]);
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r[1] = __builtin_copysignf16 (1.0f, b[1]);
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}
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void
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__attribute__((noipa,noinline,optimize("O2")))
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copysign_64 (void)
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{
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r[0] = __builtin_copysignf16 (1.0f, b[0]);
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r[1] = __builtin_copysignf16 (1.0f, b[1]);
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r[2] = __builtin_copysignf16 (1.0f, b[2]);
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r[3] = __builtin_copysignf16 (1.0f, b[3]);
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}
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static void
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__attribute__ ((noinline, noclone))
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do_test (void)
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{
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copysign_32 ();
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/* check results: */
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for (int i = 0; i != 2; i++)
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if (r[i] != __builtin_copysignf16 (1.0f, b[i]))
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abort ();
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copysign_64 ();
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/* check results: */
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for (int i = 0; i != 4; i++)
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if (r[i] != __builtin_copysignf16 (1.0f, b[i]))
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abort ();
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}
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/* { dg-final { scan-tree-dump-times "vectorized using 8 byte vectors" 1 "slp2" } } */
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/* { dg-final { scan-tree-dump-times "vectorized using 4 byte vectors" 1 "slp2" } } */
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/* { dg-final { scan-tree-dump-times ".COPYSIGN" 2 "optimized" { target { ! ia32 } } } } */
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60
gcc/testsuite/gcc.target/i386/part-vect-xorsignhf.c
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60
gcc/testsuite/gcc.target/i386/part-vect-xorsignhf.c
Normal file
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@ -0,0 +1,60 @@
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/* { dg-do run { target avx512fp16 } } */
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/* { dg-options "-O1 -mavx512fp16 -mavx512vl -ftree-vectorize -fdump-tree-slp-details -fdump-tree-optimized" } */
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extern void abort ();
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static void do_test (void);
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#define DO_TEST do_test
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#define AVX512FP16
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#include "avx512-check.h"
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#define N 16
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_Float16 a[N] = {-0.1f, -3.2f, -6.3f, -9.4f,
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-12.5f, -15.6f, -18.7f, -21.8f,
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24.9f, 27.1f, 30.2f, 33.3f,
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36.4f, 39.5f, 42.6f, 45.7f};
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_Float16 b[N] = {-1.2f, 3.4f, -5.6f, 7.8f,
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-9.0f, 1.0f, -2.0f, 3.0f,
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-4.0f, -5.0f, 6.0f, 7.0f,
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-8.0f, -9.0f, 10.0f, 11.0f};
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_Float16 r[N];
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void
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__attribute__((noipa,noinline,optimize("O2")))
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xorsign_32 (void)
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{
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r[0] = a[0] * __builtin_copysignf16 (1.0f, b[0]);
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r[1] = a[1] * __builtin_copysignf16 (1.0f, b[1]);
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}
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void
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__attribute__((noipa,noinline,optimize("O2")))
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xorsign_64 (void)
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{
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r[0] = a[0] * __builtin_copysignf16 (1.0f, b[0]);
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r[1] = a[1] * __builtin_copysignf16 (1.0f, b[1]);
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r[2] = a[2] * __builtin_copysignf16 (1.0f, b[2]);
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r[3] = a[3] * __builtin_copysignf16 (1.0f, b[3]);
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}
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static void
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__attribute__ ((noinline, noclone))
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do_test (void)
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{
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xorsign_32 ();
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/* check results: */
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for (int i = 0; i != 2; i++)
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if (r[i] != a[i] * __builtin_copysignf16 (1.0f, b[i]))
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abort ();
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xorsign_64 ();
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/* check results: */
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for (int i = 0; i != 4; i++)
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if (r[i] != a[i] * __builtin_copysignf16 (1.0f, b[i]))
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abort ();
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}
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/* { dg-final { scan-tree-dump-times "vectorized using 8 byte vectors" 1 "slp2" } } */
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/* { dg-final { scan-tree-dump-times "vectorized using 4 byte vectors" 1 "slp2" } } */
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/* { dg-final { scan-tree-dump-times ".XORSIGN" 2 "optimized" { target { ! ia32 } } } } */
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