re PR target/20342 (ICE in spill_failure, at reload1.c:1872)
PR target/20342
PR target/20447
* config/i386/i386.c (print_operand): Handle vector zeros.
(ix86_split_to_parts): Handle CONST_VECTOR.
(ix86_hard_regno_mode_ok): Allow MMX modes in general regs.
(ix86_modes_tieable_p): Use ix86_hard_regno_mode_ok to decide
what modes to tie for MMX and SSE registers.
* config/i386/i386.h (MMX_REG_MODE_P): Remove.
* config/i386/i386.md: Extend move 0 -> xor peephole to apply
to vector modes as well.
* config/i386/predicates.md (const0_operand): Handle VOIDmode
properly as an input mode.
From-SVN: r97663
This commit is contained in:
Richard Henderson
Richard Henderson
parent
aca32e16b0
commit
b4e82619bc
5 changed files with 75 additions and 25 deletions
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@ -1,3 +1,18 @@
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2005-04-05 Richard Henderson <rth@redhat.com>
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PR target/20342
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PR target/20447
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* config/i386/i386.c (print_operand): Handle vector zeros.
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(ix86_split_to_parts): Handle CONST_VECTOR.
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(ix86_hard_regno_mode_ok): Allow MMX modes in general regs.
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(ix86_modes_tieable_p): Use ix86_hard_regno_mode_ok to decide
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what modes to tie for MMX and SSE registers.
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* config/i386/i386.h (MMX_REG_MODE_P): Remove.
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* config/i386/i386.md: Extend move 0 -> xor peephole to apply
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to vector modes as well.
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* config/i386/predicates.md (const0_operand): Handle VOIDmode
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properly as an input mode.
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2005-04-05 Andrew MacLeod <amacleod@redhat.com>
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* tree-ssa-operands.c (verify_abort): Use %p for pointers.
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@ -6773,6 +6773,17 @@ print_operand (FILE *file, rtx x, int code)
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else
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{
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/* We have patterns that allow zero sets of memory, for instance.
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In 64-bit mode, we should probably support all 8-byte vectors,
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since we can in fact encode that into an immediate. */
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if (GET_CODE (x) == CONST_VECTOR)
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{
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if (x == CONST0_RTX (GET_MODE (x)))
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x = const0_rtx;
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else
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abort ();
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}
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if (code != 'P')
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{
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if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
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@ -10350,8 +10361,18 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
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operand = copy_rtx (operand);
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PUT_MODE (operand, Pmode);
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parts[0] = parts[1] = parts[2] = operand;
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return size;
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}
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else if (!TARGET_64BIT)
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if (GET_CODE (operand) == CONST_VECTOR)
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{
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enum machine_mode imode = int_mode_for_mode (mode);
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operand = simplify_subreg (imode, operand, mode, 0);
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gcc_assert (operand != NULL);
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mode = imode;
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}
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if (!TARGET_64BIT)
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{
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if (mode == DImode)
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split_di (&operand, 1, &parts[0], &parts[1]);
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@ -15111,15 +15132,30 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
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return (VALID_MMX_REG_MODE (mode)
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|| VALID_MMX_REG_MODE_3DNOW (mode));
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}
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/* We handle both integer and floats in the general purpose registers.
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In future we should be able to handle vector modes as well. */
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if (!VALID_INT_MODE_P (mode) && !VALID_FP_MODE_P (mode))
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return 0;
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/* Take care for QImode values - they can be in non-QI regs, but then
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they do cause partial register stalls. */
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if (regno < 4 || mode != QImode || TARGET_64BIT)
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if (mode == QImode)
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{
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/* Take care for QImode values - they can be in non-QI regs,
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but then they do cause partial register stalls. */
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if (regno < 4 || TARGET_64BIT)
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return 1;
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if (!TARGET_PARTIAL_REG_STALL)
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return 1;
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return reload_in_progress || reload_completed;
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}
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/* We handle both integer and floats in the general purpose registers. */
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else if (VALID_INT_MODE_P (mode))
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return 1;
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return reload_in_progress || reload_completed || !TARGET_PARTIAL_REG_STALL;
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else if (VALID_FP_MODE_P (mode))
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return 1;
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/* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
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on to use that value in smaller contexts, this can easily force a
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pseudo to be allocated to GENERAL_REGS. Since this is no worse than
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supporting DImode, allow it. */
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else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
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return 1;
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return 0;
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}
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/* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
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@ -15172,12 +15208,14 @@ ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
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/* If MODE2 is only appropriate for an SSE register, then tie with
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any other mode acceptable to SSE registers. */
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if (SSE_REG_MODE_P (mode2))
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if (GET_MODE_SIZE (mode2) >= 8
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&& ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
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return ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1);
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/* If MODE2 is appropriate for an MMX (or SSE) register, then tie
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with any other mode acceptable to MMX registers. */
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if (MMX_REG_MODE_P (mode2))
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if (GET_MODE_SIZE (mode2) == 8
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&& ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
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return ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1);
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return false;
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@ -1109,11 +1109,6 @@ do { \
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|| (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
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|| (MODE) == V4SFmode || (MODE) == V4SImode)
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/* Return true for modes passed in MMX registers. */
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#define MMX_REG_MODE_P(MODE) \
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((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \
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|| (MODE) == V2SFmode)
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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@ -18659,18 +18659,16 @@
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;; Attempt to always use XOR for zeroing registers.
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(define_peephole2
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[(set (match_operand 0 "register_operand" "")
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(const_int 0))]
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"(GET_MODE (operands[0]) == QImode
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|| GET_MODE (operands[0]) == HImode
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|| GET_MODE (operands[0]) == SImode
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|| (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
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(match_operand 1 "const0_operand" ""))]
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"GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
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&& (! TARGET_USE_MOV0 || optimize_size)
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&& GENERAL_REG_P (operands[0])
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (const_int 0))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
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operands[0]);")
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{
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operands[0] = gen_lowpart (word_mode, operands[0]);
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})
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(define_peephole2
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[(set (strict_low_part (match_operand 0 "register_operand" ""))
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@ -499,8 +499,12 @@
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;; Match exactly zero.
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(define_predicate "const0_operand"
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(and (match_code "const_int,const_double,const_vector")
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(match_test "op == CONST0_RTX (mode)")))
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(match_code "const_int,const_double,const_vector")
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{
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if (mode == VOIDmode)
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mode = GET_MODE (op);
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return op == CONST0_RTX (mode);
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})
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;; Match exactly one.
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(define_predicate "const1_operand"
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