RISC-V: Fix failed tests for regression due to fix ICE patch

Ref:
https://github.com/ewlu/gcc-precommit-ci/issues/3096#issue-2854419069

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/bug-9.c: Added new failure check.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c: Likewise.

gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c

@@ -11,3 +11,4 @@ vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c

@@ -11,3 +11,4 @@ test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c

@@ -11,3 +11,4 @@ test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c

@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c

@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c

@@ -11,3 +11,4 @@ test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c

@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c

@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c

@@ -11,3 +11,4 @@ test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c

@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c

@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c

@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c

@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c

@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c

@@ -11,3 +11,4 @@ test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vint32m1_t' requires the V ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint32m1_t' requires the V ISA extension" "" { target { "riscv*-*-*" } } 0 } */