* config/aarch64/aarch64-protos.h
(aarch64_gen_atomic_cas): Declare. * config/aarch64/aarch64.c (aarch64_expand_compare_and_swap): Choose appropriate instruction pattern for the target. (aarch64_gen_atomic_cas): New. * config/aarch64/atomics.md (UNSPECV_ATOMIC_CAS): New. (atomic_compare_and_swap<mode>_1): Rename to aarch64_compare_and_swap<mode>. Fix some indentation. (aarch64_compare_and_swap<mode>_lse): New. (aarch64_atomic_cas<mode>): New. From-SVN: r226858
This commit is contained in:
Matthew Wahab
Matthew Wahab
parent
045c2d32d9
commit
b0770c0f18
4 changed files with 191 additions and 18 deletions
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@ -1,3 +1,16 @@
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2015-08-13 Matthew Wahab <matthew.wahab@arm.com>
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* config/aarch64/aarch64-protos.h
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(aarch64_gen_atomic_cas): Declare.
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* config/aarch64/aarch64.c (aarch64_expand_compare_and_swap):
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Choose appropriate instruction pattern for the target.
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(aarch64_gen_atomic_cas): New.
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* config/aarch64/atomics.md (UNSPECV_ATOMIC_CAS): New.
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(atomic_compare_and_swap<mode>_1): Rename to
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aarch64_compare_and_swap<mode>. Fix some indentation.
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(aarch64_compare_and_swap<mode>_lse): New.
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(aarch64_atomic_cas<mode>): New.
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2015-08-13 Matthew Wahab <matthew.wahab@arm.com>
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* config/aarch64/aarch64.h (AARCH64_ISA_LSE): New.
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@ -362,6 +362,7 @@ rtx aarch64_load_tp (rtx);
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void aarch64_expand_compare_and_swap (rtx op[]);
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void aarch64_split_compare_and_swap (rtx op[]);
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void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx);
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void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
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bool aarch64_gen_adjusted_ldpstp (rtx *, bool, enum machine_mode, RTX_CODE);
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@ -10754,7 +10754,23 @@ aarch64_expand_compare_and_swap (rtx operands[])
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{
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rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
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machine_mode mode, cmp_mode;
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rtx (*gen) (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
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typedef rtx (*gen_cas_fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
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int idx;
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gen_cas_fn gen;
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const gen_cas_fn split_cas[] =
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{
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gen_aarch64_compare_and_swapqi,
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gen_aarch64_compare_and_swaphi,
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gen_aarch64_compare_and_swapsi,
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gen_aarch64_compare_and_swapdi
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};
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const gen_cas_fn atomic_cas[] =
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{
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gen_aarch64_compare_and_swapqi_lse,
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gen_aarch64_compare_and_swaphi_lse,
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gen_aarch64_compare_and_swapsi_lse,
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gen_aarch64_compare_and_swapdi_lse
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};
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bval = operands[0];
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rval = operands[1];
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@ -10799,13 +10815,17 @@ aarch64_expand_compare_and_swap (rtx operands[])
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switch (mode)
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{
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case QImode: gen = gen_atomic_compare_and_swapqi_1; break;
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case HImode: gen = gen_atomic_compare_and_swaphi_1; break;
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case SImode: gen = gen_atomic_compare_and_swapsi_1; break;
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case DImode: gen = gen_atomic_compare_and_swapdi_1; break;
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case QImode: idx = 0; break;
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case HImode: idx = 1; break;
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case SImode: idx = 2; break;
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case DImode: idx = 3; break;
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default:
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gcc_unreachable ();
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}
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if (TARGET_LSE)
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gen = atomic_cas[idx];
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else
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gen = split_cas[idx];
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emit_insn (gen (rval, mem, oldval, newval, is_weak, mod_s, mod_f));
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@ -10834,6 +10854,42 @@ aarch64_emit_post_barrier (enum memmodel model)
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}
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}
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/* Emit an atomic compare-and-swap operation. RVAL is the destination register
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for the data in memory. EXPECTED is the value expected to be in memory.
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DESIRED is the value to store to memory. MEM is the memory location. MODEL
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is the memory ordering to use. */
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void
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aarch64_gen_atomic_cas (rtx rval, rtx mem,
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rtx expected, rtx desired,
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rtx model)
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{
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rtx (*gen) (rtx, rtx, rtx, rtx);
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machine_mode mode;
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mode = GET_MODE (mem);
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switch (mode)
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{
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case QImode: gen = gen_aarch64_atomic_casqi; break;
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case HImode: gen = gen_aarch64_atomic_cashi; break;
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case SImode: gen = gen_aarch64_atomic_cassi; break;
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case DImode: gen = gen_aarch64_atomic_casdi; break;
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default:
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gcc_unreachable ();
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}
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/* Move the expected value into the CAS destination register. */
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emit_insn (gen_rtx_SET (rval, expected));
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/* Emit the CAS. */
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emit_insn (gen (rval, mem, desired, model));
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/* Compare the expected value with the value loaded by the CAS, to establish
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whether the swap was made. */
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aarch64_gen_compare_reg (EQ, rval, expected);
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}
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/* Split a compare and swap pattern. */
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void
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@ -26,6 +26,7 @@
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UNSPECV_STL ; Represent an atomic store or store-release.
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UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
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UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
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UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
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UNSPECV_ATOMIC_OP ; Represent an atomic operation.
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])
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@ -45,10 +46,10 @@
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}
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)
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(define_insn_and_split "atomic_compare_and_swap<mode>_1"
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(define_insn_and_split "aarch64_compare_and_swap<mode>"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:SI 0 "register_operand" "=&r") ;; val out
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(set (match_operand:SI 0 "register_operand" "=&r") ;; val out
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(zero_extend:SI
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(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
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(set (match_dup 1)
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@ -57,6 +58,30 @@
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(match_operand:SHORT 3 "register_operand" "r") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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UNSPECV_ATOMIC_CMPSW))
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(clobber (match_scratch:SI 7 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_compare_and_swap (operands);
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DONE;
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}
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)
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(define_insn_and_split "aarch64_compare_and_swap<mode>"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:GPI 0 "register_operand" "=&r") ;; val out
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(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
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(set (match_dup 1)
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(unspec_volatile:GPI
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[(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect
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(match_operand:GPI 3 "register_operand" "r") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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UNSPECV_ATOMIC_CMPSW))
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(clobber (match_scratch:SI 7 "=&r"))]
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@ -70,26 +95,53 @@
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}
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)
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(define_insn_and_split "atomic_compare_and_swap<mode>_1"
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(define_insn_and_split "aarch64_compare_and_swap<mode>_lse"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:GPI 0 "register_operand" "=&r") ;; val out
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(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
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(set (match_operand:SI 0 "register_operand" "=&r") ;; val out
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(zero_extend:SI
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(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
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(set (match_dup 1)
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(unspec_volatile:GPI
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[(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect
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(match_operand:GPI 3 "register_operand" "r") ;; desired
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(unspec_volatile:SHORT
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[(match_operand:SI 2 "aarch64_plus_operand" "rI") ;; expected
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(match_operand:SHORT 3 "register_operand" "r") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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UNSPECV_ATOMIC_CMPSW))
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(clobber (match_scratch:SI 7 "=&r"))]
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""
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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UNSPECV_ATOMIC_CMPSW))]
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"TARGET_LSE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_compare_and_swap (operands);
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aarch64_gen_atomic_cas (operands[0], operands[1],
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operands[2], operands[3],
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operands[5]);
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DONE;
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}
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)
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(define_insn_and_split "aarch64_compare_and_swap<mode>_lse"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:GPI 0 "register_operand" "=&r") ;; val out
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(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
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(set (match_dup 1)
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(unspec_volatile:GPI
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[(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect
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(match_operand:GPI 3 "register_operand" "r") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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UNSPECV_ATOMIC_CMPSW))]
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"TARGET_LSE "
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_gen_atomic_cas (operands[0], operands[1],
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operands[2], operands[3],
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operands[5]);
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DONE;
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}
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)
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@ -370,3 +422,54 @@
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return "dmb\\tish";
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}
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)
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;; ARMv8.1 LSE instructions.
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;; Atomic compare-and-swap: HI and smaller modes.
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(define_insn "aarch64_atomic_cas<mode>"
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[(set (match_operand:SI 0 "register_operand" "+&r") ;; out
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(zero_extend:SI
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(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory.
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(set (match_dup 1)
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(unspec_volatile:SHORT
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[(match_dup 0)
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(match_operand:SHORT 2 "register_operand" "r") ;; value.
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(match_operand:SI 3 "const_int_operand" "")] ;; model.
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UNSPECV_ATOMIC_CAS))]
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"TARGET_LSE && reload_completed"
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
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if (is_mm_relaxed (model))
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return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_acquire (model) || is_mm_consume (model))
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return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_release (model))
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return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
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else
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return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
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})
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;; Atomic compare-and-swap: SI and larger modes.
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(define_insn "aarch64_atomic_cas<mode>"
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[(set (match_operand:GPI 0 "register_operand" "+&r") ;; out
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(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory.
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(set (match_dup 1)
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(unspec_volatile:GPI
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[(match_dup 0)
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(match_operand:GPI 2 "register_operand" "r") ;; value.
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(match_operand:SI 3 "const_int_operand" "")] ;; model.
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UNSPECV_ATOMIC_CAS))]
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"TARGET_LSE && reload_completed"
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
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if (is_mm_relaxed (model))
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return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_acquire (model) || is_mm_consume (model))
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return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_release (model))
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return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
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else
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return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
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})
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