diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0406ed24da0..27e196ec147 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2012-02-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/52352
+	* config/i386/i386.md (*movabs<mode>_1): Enable only for
+	TARGET_LP64.
+	(*movabs<mode>_2): Likewise.
+
 2012-02-27  Jakub Jelinek  <jakub@redhat.com>
 
 	PR target/52375
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 630b1143bbc..7f5a9e0c1c3 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2362,7 +2362,7 @@
 (define_insn "*movabs<mode>_1"
   [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
 	(match_operand:SWI1248x 1 "nonmemory_operand" "a,r<i>"))]
-  "TARGET_64BIT && ix86_check_movabs (insn, 0)"
+  "TARGET_LP64 && ix86_check_movabs (insn, 0)"
   "@
    movabs{<imodesuffix>}\t{%1, %P0|%P0, %1}
    mov{<imodesuffix>}\t{%1, %a0|%a0, %1}"
@@ -2376,7 +2376,7 @@
 (define_insn "*movabs<mode>_2"
   [(set (match_operand:SWI1248x 0 "register_operand" "=a,r")
         (mem:SWI1248x (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
-  "TARGET_64BIT && ix86_check_movabs (insn, 1)"
+  "TARGET_LP64 && ix86_check_movabs (insn, 1)"
   "@
    movabs{<imodesuffix>}\t{%P1, %0|%0, %P1}
    mov{<imodesuffix>}\t{%a1, %0|%0, %a1}"