re PR target/68779 (HPPA/PARISC 32-bit Linux kernel build triggers multiple ICEs)
PR target/68779 * config/pa/pa.md (atomic_loaddi): Honor -mdisable-fpregs. (atomic_loaddi_1): Likewise. (atomic_storedi): Likewise. (atomic_storedi_1): Likewise. (atomic_loaddf): Likewise. (atomic_loaddf_1): Likewise. (atomic_storedf): Likewise. (atomic_storedf_1): Likewise. Move all atomic patterns to end of file. From-SVN: r231727
This commit is contained in:
John David Anglin
parent
f3b5cf3ddc
commit
ad7e0b44ae
2 changed files with 248 additions and 231 deletions
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@ -1,3 +1,16 @@
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2015-12-16 John David Anglin <danglin@gcc.gnu.org>
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PR target/68779
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* config/pa/pa.md (atomic_loaddi): Honor -mdisable-fpregs.
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(atomic_loaddi_1): Likewise.
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(atomic_storedi): Likewise.
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(atomic_storedi_1): Likewise.
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(atomic_loaddf): Likewise.
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(atomic_loaddf_1): Likewise.
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(atomic_storedf): Likewise.
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(atomic_storedf_1): Likewise.
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Move all atomic patterns to end of file.
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2015-12-16 Abderrazek Zaafrani <a.zaafrani@samsung.com>
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* graphite-isl-ast-to-gimple.c: Include isl/schedule_node.h.
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@ -692,237 +692,6 @@
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(include "predicates.md")
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(include "constraints.md")
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;; Atomic instructions
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;; All memory loads and stores access storage atomically except
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;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and
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;; doubleword loads and stores are not guaranteed to be atomic
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;; when referencing the I/O address space.
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;; The kernel cmpxchg operation on linux is not atomic with respect to
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;; memory stores on SMP machines, so we must do stores using a cmpxchg
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;; operation.
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;; Implement atomic QImode store using exchange.
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(define_expand "atomic_storeqi"
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[(match_operand:QI 0 "memory_operand") ;; memory
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(match_operand:QI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic HImode stores using exchange.
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(define_expand "atomic_storehi"
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[(match_operand:HI 0 "memory_operand") ;; memory
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(match_operand:HI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic SImode store using exchange.
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(define_expand "atomic_storesi"
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[(match_operand:SI 0 "memory_operand") ;; memory
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(match_operand:SI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic SFmode store using exchange.
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(define_expand "atomic_storesf"
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[(match_operand:SF 0 "memory_operand") ;; memory
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(match_operand:SF 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic DImode load using 64-bit floating point load.
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(define_expand "atomic_loaddi"
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[(match_operand:DI 0 "register_operand") ;; val out
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(match_operand:DI 1 "memory_operand") ;; memory
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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enum memmodel model;
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if (TARGET_64BIT || TARGET_SOFT_FLOAT)
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FAIL;
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[1] = force_reg (SImode, XEXP (operands[1], 0));
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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expand_mem_thread_fence (model);
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DONE;
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})
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(define_insn "atomic_loaddi_1"
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[(set (match_operand:DI 0 "register_operand" "=f,r")
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(mem:DI (match_operand:SI 1 "register_operand" "r,r")))
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(clobber (match_scratch:DI 2 "=X,f"))]
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"!TARGET_64BIT && !TARGET_SOFT_FLOAT"
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"@
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{fldds|fldd} 0(%1),%0
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{fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
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[(set_attr "type" "move,move")
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(set_attr "length" "4,16")])
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;; Implement atomic DImode store.
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(define_expand "atomic_storedi"
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[(match_operand:DI 0 "memory_operand") ;; memory
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(match_operand:DI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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enum memmodel model;
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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if (TARGET_64BIT || TARGET_SOFT_FLOAT)
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FAIL;
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[0] = force_reg (SImode, XEXP (operands[0], 0));
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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expand_mem_thread_fence (model);
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DONE;
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})
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(define_insn "atomic_storedi_1"
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[(set (mem:DI (match_operand:SI 0 "register_operand" "r,r"))
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(match_operand:DI 1 "register_operand" "f,r"))
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(clobber (match_scratch:DI 2 "=X,f"))]
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"!TARGET_64BIT && !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL"
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"@
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{fstds|fstd} %1,0(%0)
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{stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
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[(set_attr "type" "move,move")
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(set_attr "length" "4,16")])
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;; Implement atomic DFmode load using 64-bit floating point load.
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(define_expand "atomic_loaddf"
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[(match_operand:DF 0 "register_operand") ;; val out
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(match_operand:DF 1 "memory_operand") ;; memory
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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enum memmodel model;
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if (TARGET_64BIT || TARGET_SOFT_FLOAT)
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FAIL;
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[1] = force_reg (SImode, XEXP (operands[1], 0));
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_loaddf_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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expand_mem_thread_fence (model);
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DONE;
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})
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(define_insn "atomic_loaddf_1"
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[(set (match_operand:DF 0 "register_operand" "=f,r")
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(mem:DF (match_operand:SI 1 "register_operand" "r,r")))
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(clobber (match_scratch:DF 2 "=X,f"))]
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"!TARGET_64BIT && !TARGET_SOFT_FLOAT"
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"@
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{fldds|fldd} 0(%1),%0
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{fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
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[(set_attr "type" "move,move")
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(set_attr "length" "4,16")])
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;; Implement atomic DFmode store using 64-bit floating point store.
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(define_expand "atomic_storedf"
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[(match_operand:DF 0 "memory_operand") ;; memory
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(match_operand:DF 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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enum memmodel model;
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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if (TARGET_64BIT || TARGET_SOFT_FLOAT)
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FAIL;
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[0] = force_reg (SImode, XEXP (operands[0], 0));
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_storedf_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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expand_mem_thread_fence (model);
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DONE;
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})
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(define_insn "atomic_storedf_1"
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[(set (mem:DF (match_operand:SI 0 "register_operand" "r,r"))
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(match_operand:DF 1 "register_operand" "f,r"))
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(clobber (match_scratch:DF 2 "=X,f"))]
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"!TARGET_64BIT && !TARGET_SOFT_FLOAT"
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"@
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{fstds|fstd} %1,0(%0)
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{stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
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[(set_attr "type" "move,move")
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(set_attr "length" "4,16")])
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;; Compare instructions.
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;; This controls RTL generation and register allocation.
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@ -9930,3 +9699,238 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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"addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
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[(set_attr "type" "multi")
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(set_attr "length" "8")])
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;; Atomic instructions
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;; All memory loads and stores access storage atomically except
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;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and
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;; doubleword loads and stores are not guaranteed to be atomic
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;; when referencing the I/O address space.
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;; The kernel cmpxchg operation on linux is not atomic with respect to
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;; memory stores on SMP machines, so we must do stores using a cmpxchg
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;; operation.
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;; These patterns are at the bottom so the non atomic versions are preferred.
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;; Implement atomic QImode store using exchange.
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(define_expand "atomic_storeqi"
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[(match_operand:QI 0 "memory_operand") ;; memory
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(match_operand:QI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic HImode stores using exchange.
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(define_expand "atomic_storehi"
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[(match_operand:HI 0 "memory_operand") ;; memory
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(match_operand:HI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic SImode store using exchange.
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(define_expand "atomic_storesi"
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[(match_operand:SI 0 "memory_operand") ;; memory
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(match_operand:SI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic SFmode store using exchange.
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(define_expand "atomic_storesf"
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[(match_operand:SF 0 "memory_operand") ;; memory
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(match_operand:SF 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic DImode load using 64-bit floating point load.
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(define_expand "atomic_loaddi"
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[(match_operand:DI 0 "register_operand") ;; val out
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(match_operand:DI 1 "memory_operand") ;; memory
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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enum memmodel model;
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if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
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FAIL;
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[1] = force_reg (SImode, XEXP (operands[1], 0));
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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expand_mem_thread_fence (model);
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DONE;
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})
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(define_insn "atomic_loaddi_1"
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[(set (match_operand:DI 0 "register_operand" "=f,r")
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(mem:DI (match_operand:SI 1 "register_operand" "r,r")))
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(clobber (match_scratch:DI 2 "=X,f"))]
|
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"!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
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"@
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{fldds|fldd} 0(%1),%0
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{fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
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[(set_attr "type" "move,move")
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(set_attr "length" "4,16")])
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;; Implement atomic DImode store.
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||||
|
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(define_expand "atomic_storedi"
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[(match_operand:DI 0 "memory_operand") ;; memory
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||||
(match_operand:DI 1 "register_operand") ;; val out
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||||
(match_operand:SI 2 "const_int_operand")] ;; model
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||||
""
|
||||
{
|
||||
enum memmodel model;
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||||
|
||||
if (TARGET_SYNC_LIBCALL)
|
||||
{
|
||||
rtx mem = operands[0];
|
||||
rtx val = operands[1];
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||||
if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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||||
DONE;
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||||
}
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||||
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if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
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FAIL;
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[0] = force_reg (SImode, XEXP (operands[0], 0));
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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expand_mem_thread_fence (model);
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||||
DONE;
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||||
})
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(define_insn "atomic_storedi_1"
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[(set (mem:DI (match_operand:SI 0 "register_operand" "r,r"))
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(match_operand:DI 1 "register_operand" "f,r"))
|
||||
(clobber (match_scratch:DI 2 "=X,f"))]
|
||||
"!TARGET_64BIT && !TARGET_DISABLE_FPREGS
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&& !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL"
|
||||
"@
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||||
{fstds|fstd} %1,0(%0)
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||||
{stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
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[(set_attr "type" "move,move")
|
||||
(set_attr "length" "4,16")])
|
||||
|
||||
;; Implement atomic DFmode load using 64-bit floating point load.
|
||||
|
||||
(define_expand "atomic_loaddf"
|
||||
[(match_operand:DF 0 "register_operand") ;; val out
|
||||
(match_operand:DF 1 "memory_operand") ;; memory
|
||||
(match_operand:SI 2 "const_int_operand")] ;; model
|
||||
""
|
||||
{
|
||||
enum memmodel model;
|
||||
|
||||
if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
|
||||
FAIL;
|
||||
|
||||
model = memmodel_from_int (INTVAL (operands[2]));
|
||||
operands[1] = force_reg (SImode, XEXP (operands[1], 0));
|
||||
expand_mem_thread_fence (model);
|
||||
emit_insn (gen_atomic_loaddf_1 (operands[0], operands[1]));
|
||||
if (is_mm_seq_cst (model))
|
||||
expand_mem_thread_fence (model);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "atomic_loaddf_1"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f,r")
|
||||
(mem:DF (match_operand:SI 1 "register_operand" "r,r")))
|
||||
(clobber (match_scratch:DF 2 "=X,f"))]
|
||||
"!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
|
||||
"@
|
||||
{fldds|fldd} 0(%1),%0
|
||||
{fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
|
||||
[(set_attr "type" "move,move")
|
||||
(set_attr "length" "4,16")])
|
||||
|
||||
;; Implement atomic DFmode store using 64-bit floating point store.
|
||||
|
||||
(define_expand "atomic_storedf"
|
||||
[(match_operand:DF 0 "memory_operand") ;; memory
|
||||
(match_operand:DF 1 "register_operand") ;; val out
|
||||
(match_operand:SI 2 "const_int_operand")] ;; model
|
||||
""
|
||||
{
|
||||
enum memmodel model;
|
||||
|
||||
if (TARGET_SYNC_LIBCALL)
|
||||
{
|
||||
rtx mem = operands[0];
|
||||
rtx val = operands[1];
|
||||
if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
|
||||
DONE;
|
||||
}
|
||||
|
||||
if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
|
||||
FAIL;
|
||||
|
||||
model = memmodel_from_int (INTVAL (operands[2]));
|
||||
operands[0] = force_reg (SImode, XEXP (operands[0], 0));
|
||||
expand_mem_thread_fence (model);
|
||||
emit_insn (gen_atomic_storedf_1 (operands[0], operands[1]));
|
||||
if (is_mm_seq_cst (model))
|
||||
expand_mem_thread_fence (model);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "atomic_storedf_1"
|
||||
[(set (mem:DF (match_operand:SI 0 "register_operand" "r,r"))
|
||||
(match_operand:DF 1 "register_operand" "f,r"))
|
||||
(clobber (match_scratch:DF 2 "=X,f"))]
|
||||
"!TARGET_64BIT && !TARGET_DISABLE_FPREGS
|
||||
&& !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL"
|
||||
"@
|
||||
{fstds|fstd} %1,0(%0)
|
||||
{stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
|
||||
[(set_attr "type" "move,move")
|
||||
(set_attr "length" "4,16")])
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue