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rs6000.md (altivec_stvx): Add parallels to stvx.

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* config/rs6000/rs6000.md (altivec_stvx): Add parallels to stvx.
        (altivec_lvsl): Change constraint to b.
        (altivec_lvsr): Same.
        (altivec_lvebx): Same.
        (altivec_lvehx): Same.
        (altivec_lvewx): Same.
        (altivec_lvxl): Same.
        (altivec_lvx): Same.
        (altivec_stvx): Add parallel.
        (altivec_stvxl): Same.
        (altivec_stvehx): Same.
        (altivec_stvebx): Same.
        (altivec_stvebx): Same.

From-SVN: r48890
This commit is contained in:
Aldy Hernandez 2002-01-16 00:25:54 +00:00 • committed by Aldy Hernandez
parent 33b16473de
commit acfab996f3
2 changed files with 51 additions and 26 deletions
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16
gcc/ChangeLog
View file

@ -1,3 +1,19 @@
2002-01-15 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md (altivec_stvx): Add parallels to stvx.
(altivec_lvsl): Change constraint to b.
(altivec_lvsr): Same.
(altivec_lvebx): Same.
(altivec_lvehx): Same.
(altivec_lvewx): Same.
(altivec_lvxl): Same.
(altivec_lvx): Same.
(altivec_stvx): Add parallel.
(altivec_stvxl): Same.
(altivec_stvehx): Same.
(altivec_stvebx): Same.
(altivec_stvebx): Same.
2002-01-15 Aldy Hernandez <aldyh@redhat.com>
* config.gcc: Change altivec.h to altivec-defs.h.

61
gcc/config/rs6000/rs6000.md
View file

@ -15496,7 +15496,7 @@
(define_insn "altivec_lvsl"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "r")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 194))]
"TARGET_ALTIVEC"
"lvsl %0,%1,%2"
@ -15504,7 +15504,7 @@
(define_insn "altivec_lvsr"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "r")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 195))]
"TARGET_ALTIVEC"
"lvsr %0,%1,%2"
@ -15512,7 +15512,7 @@
(define_insn "altivec_lvebx"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "r")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 196))]
"TARGET_ALTIVEC"
"lvebx %0,%1,%2"
@ -15520,7 +15520,7 @@
(define_insn "altivec_lvehx"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:SI 1 "register_operand" "r")
(unspec:V8HI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 197))]
"TARGET_ALTIVEC"
"lvehx %0,%1,%2"
@ -15528,7 +15528,7 @@
(define_insn "altivec_lvewx"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:SI 1 "register_operand" "r")
(unspec:V4SI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 198))]
"TARGET_ALTIVEC"
"lvewx %0,%1,%2"
@ -15536,7 +15536,7 @@
(define_insn "altivec_lvxl"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:SI 1 "register_operand" "r")
(unspec:V4SI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 199))]
"TARGET_ALTIVEC"
"lvxl %0,%1,%2"
@ -15544,18 +15544,23 @@
(define_insn "altivec_lvx"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:SI 1 "register_operand" "r")
(unspec:V4SI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 200))]
"TARGET_ALTIVEC"
"lvx %0,%1,%2"
[(set_attr "type" "vecload")])
;; Parallel the STV*'s with unspecs because some of them have
;; identical rtl but are different instructions-- and gcc gets confused.
(define_insn "altivec_stvx"
[(set (mem:V4SI
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "register_operand" "r"))
(const_int -16)))
(match_operand:V4SI 2 "register_operand" "v"))]
[(parallel
[(set (mem:V4SI
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r"))
(const_int -16)))
(match_operand:V4SI 2 "register_operand" "v"))
(unspec [(const_int 0)] 201)])]
"TARGET_ALTIVEC"
"stvx %2,%0,%1"
[(set_attr "type" "vecstore")])
@ -15563,11 +15568,11 @@
(define_insn "altivec_stvxl"
[(parallel
[(set (mem:V4SI
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r"))
(const_int -16)))
(match_operand:V4SI 2 "register_operand" "v"))
(unspec [(const_int 0)] 201)])]
(unspec [(const_int 0)] 202)])]
"TARGET_ALTIVEC"
"stvxl %2,%0,%1"
[(set_attr "type" "vecstore")])
@ -15575,30 +15580,34 @@
(define_insn "altivec_stvebx"
[(parallel
[(set (mem:V16QI
(plus:SI (match_operand:SI 0 "register_operand" "r")
(plus:SI (match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r")))
(match_operand:V16QI 2 "register_operand" "v"))
(unspec [(const_int 0)] 202)])]
(unspec [(const_int 0)] 203)])]
"TARGET_ALTIVEC"
"stvebx %2,%0,%1"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvehx"
[(set (mem:V8HI
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "register_operand" "r"))
(const_int -2)))
(match_operand:V8HI 2 "register_operand" "v"))]
[(parallel
[(set (mem:V8HI
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r"))
(const_int -2)))
(match_operand:V8HI 2 "register_operand" "v"))
(unspec [(const_int 0)] 204)])]
"TARGET_ALTIVEC"
"stvehx %2,%0,%1"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvewx"
[(set (mem:V4SI
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "register_operand" "r"))
(const_int -4)))
(match_operand:V4SI 2 "register_operand" "v"))]
[(parallel
[(set (mem:V4SI
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r"))
(const_int -4)))
(match_operand:V4SI 2 "register_operand" "v"))
(unspec [(const_int 0)] 205)])]
"TARGET_ALTIVEC"
"stvewx %2,%0,%1"
[(set_attr "type" "vecstore")])