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RISC-V: remove param riscv-vector-abi. [PR113538]

Browse source 
Also adjust some of the tests for scan-assembly. The behavior is the
same as --param=riscv-vector-abi before.

gcc/ChangeLog:

	PR target/113538
	* config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
	(riscv_fntype_abi): Ditto.
	* config/riscv/riscv.opt: Ditto.

gcc/testsuite/ChangeLog:

	PR target/113538
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Fix the asm
	check.
	* gcc.target/riscv/rvv/base/abi-call-args-1-run.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-args-1.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-args-2-run.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-args-2.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-args-3-run.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-args-3.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-args-4-run.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-args-4.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-error-1.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-return-run.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-return.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-call-variant_cc.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-callee-saved-1.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: Ditto.
	* gcc.target/riscv/rvv/base/abi-callee-saved-2.c: Ditto.
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c: Ditto.
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c: Ditto.
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c: Ditto.
	* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c: Ditto.
	* gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c: Ditto.
	* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
	* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
	* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
	* gcc.target/riscv/rvv/base/tuple_vundefined.c: Ditto.
	* gcc.target/riscv/rvv/base/vcreate.c: Ditto.
	* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
	* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
	* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Ditto.
	* lib/target-supports.exp: Remove the flag.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
This commit is contained in:
Yanzhang Wang 2024-01-25 21:06:09 +08:00 • committed by Pan Li
parent fb1b7e2fec
commit acc22d56e1
46 changed files with 69 additions and 117 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
gcc/config/riscv/riscv.cc
View file

@ -4999,7 +4999,7 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
/* When disable vector_abi or scalable vector argument is anonymous, this
argument is passed by reference. */
if (riscv_v_ext_mode_p (mode) && (!riscv_vector_abi || !named))
if (riscv_v_ext_mode_p (mode) && !named)
return NULL_RTX;
if (named)
@ -5320,9 +5320,8 @@ riscv_fntype_abi (const_tree fntype)
You can enable this feature via the `--param=riscv-vector-abi` compiler
option. */
if (riscv_vector_abi
&& (riscv_return_value_is_vector_type_p (fntype)
|| riscv_arguments_is_vector_type_p (fntype)))
if (riscv_return_value_is_vector_type_p (fntype)
|| riscv_arguments_is_vector_type_p (fntype))
return riscv_v_abi ();
return default_function_abi;

5
gcc/config/riscv/riscv.opt
View file

@ -543,11 +543,6 @@ Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) In
madjust-lmul-cost
Target Var(TARGET_ADJUST_LMUL_COST) Init(0)
-param=riscv-vector-abi
Target Undocumented Var(riscv_vector_abi) Init(0)
Enable the use of vector registers for function arguments and return value.
This is an experimental switch and may be subject to change in the future.
Enum
Name(vsetvl_strategy) Type(enum vsetvl_strategy_enum)
Valid arguments to -param=vsetvl-strategy=:

2
gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
View file

@ -41,7 +41,7 @@ foo (int32_t *__restrict a, int32_t *__restrict b, int32_t *__restrict c,
}
/* { dg-final { scan-assembler {e32,m1} } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-assembler-not {csrr} { xfail "*-*-*" } } } */
/* { dg-final { scan-tree-dump-times "Preferring smaller LMUL loop because it has unexpected spills" 3 "vect" } } */
/* { dg-final { scan-tree-dump-times "Maximum lmul = 8" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "Maximum lmul = 4" 1 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
View file

@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-options "-O1" } */
/* { dg-additional-sources abi-call-args-1.c } */
#include <stdbool.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c
View file

@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-options "-O1" } */
/* { dg-additional-sources abi-call-args-2.c } */
#include <stdlib.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1" } */
#include <stdarg.h>
#include "riscv_vector.h"

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c
View file

@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-options "-O1" } */
/* { dg-additional-sources abi-call-args-3.c } */
#include <stdbool.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c
View file

@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-options "-O1" } */
/* { dg-additional-sources abi-call-args-4.c } */
#include <stdbool.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-vector-abi -Wno-implicit-function-declaration" } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -Wno-implicit-function-declaration" } */
#include "riscv_vector.h"

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c
View file

@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-options "-O1" } */
/* { dg-additional-sources abi-call-return.c } */
#include <stdbool.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O1 --param=riscv-vector-abi" } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O1 --param=riscv-vector-abi" } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */
#include "riscv_vector.h"

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-vector-abi --param=riscv-autovec-preference=fixed-vlmax" } */
/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-vector-abi --param=riscv-autovec-preference=fixed-vlmax" } */
/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -msave-restore" } */
/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d --param=riscv-vector-abi -fno-shrink-wrap-separate" } */
/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi" } */
/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -msave-restore" } */
/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d --param=riscv-vector-abi -fno-shrink-wrap-separate" } */
/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>

2
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi" } */
/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>

6
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
View file

@ -24,8 +24,8 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
return result;
}
/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 1 } } */
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */
/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */
/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
/* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */

6
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
View file

@ -21,8 +21,8 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
return result;
}
/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */
/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */
/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
/* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */

6
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
View file

@ -21,8 +21,8 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
return result;
}
/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */
/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 3 } } */
/* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */

4
gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
View file

@ -114,6 +114,4 @@ vuint64m1_t test_vreinterpret_v_b1_vuint64m1 (vbool1_t src) {
return __riscv_vreinterpret_v_b1_u64m1 (src);
}
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */
/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */
/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 28 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c
View file

@ -4,9 +4,7 @@
#include "overloaded_vadd.h"
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 8 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*tu,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*ta,\s*mu} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*tu,\s*mu} 2 } } */
/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[ax][0-9]+} 6 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c
View file

@ -3,9 +3,7 @@
#include "overloaded_vfadd.h"
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma} 16 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*ta,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 8 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*tu,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*ta,\s*mu} 2 } } */

3
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c
View file

@ -3,5 +3,4 @@
#include "overloaded_vget_vset.h"
/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([ax][0-9]+\)} 14 } } */
/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([ax][0-9]+\)} 13 } } */
/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */

1
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c
View file

@ -4,7 +4,6 @@
#include "overloaded_vloxseg2ei16.h"
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*ta,\s*ma} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*tu,\s*ma} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*tu,\s*mu} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c
View file

@ -3,8 +3,4 @@
#include "overloaded_vreinterpret.h"
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c
View file

@ -3,9 +3,7 @@
#include "overloaded_vadd.h"
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 8 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*tu,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*ta,\s*mu} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*tu,\s*mu} 2 } } */
/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[ax][0-9]+} 6 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c
View file

@ -2,9 +2,7 @@
#include "overloaded_vfadd.h"
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma} 16 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*ta,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 8 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*tu,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*ta,\s*mu} 2 } } */

3
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c
View file

@ -2,5 +2,4 @@
#include "overloaded_vget_vset.h"
/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([ax][0-9]+\)} 14 } } */
/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([ax][0-9]+\)} 13 } } */
/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c
View file

@ -3,8 +3,6 @@
#include "overloaded_vloxseg2ei16.h"
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*ta,\s*ma} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 4 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*tu,\s*ma} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*tu,\s*mu} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
/* { dg-final { scan-assembler-times {vloxseg2ei16\.v\s+v[0-9]+,\s*\([ax][0-9]+\),\s*v[0-9]+} 6 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c
View file

@ -2,8 +2,4 @@
#include "overloaded_vreinterpret.h"
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */

11
gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
View file

@ -11,13 +11,16 @@ void f (char*);
** addi\tsp,sp,-32
** sw\tra,4\(sp\)
** sw\ts0,0\(sp\)
** addi\ts0,sp,8
** addi\ts0,sp,8
** csrr\tt0,vlenb
** sub\tsp,sp,t0
** vs1r.v\tv1,0\(sp\)
** sub\tsp,sp,t0
** vs1r.v\tv2,0\(sp\)
** ...
** addi\ta2,a2,15
** andi\ta2,a2,-8
** sub\tsp,sp,a2
** addi\ta1,a1,15
** andi\ta1,a1,-8
** sub\tsp,sp,a1
** ...
** lw\tra,4\(sp\)
** lw\ts0,0\(sp\)

17
gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
View file

@ -9,21 +9,22 @@ void fn3 (char*);
/*
** stack_save_restore_2:
** call\tt0,__riscv_save_1
** call\tt0,__riscv_save_0
** csrr\tt0,vlenb
** slli\tt1,t0,1
** sub\tsp,sp,t1
** li\tt0,-8192
** addi\tt0,t0,192
** add\tsp,sp,t0
** sub\tsp,sp,t0
** vs1r.v\tv1,0\(sp\)
** ...
** csrr\tt0,vlenb
** slli\tt1,t0,1
** slli\tt1,t0,2
** sub\tt1,t1,t0
** add\tsp,sp,t1
** li\tt0,8192
** addi\tt0,t0,-192
** add\tsp,sp,t0
** tail\t__riscv_restore_1
** ...
** vl1re64.v\tv1,0\(sp\)
** add\tsp,sp,t0
** tail\t__riscv_restore_0
*/
int stack_save_restore_2 (float a1, float a2, float a3, float a4,
float a5, float a6, float a7, float a8,

12
gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
View file

@ -11,14 +11,14 @@ void f (char*);
** addi\tsp,sp,-48
** sw\tra,12\(sp\)
** sw\ts0,8\(sp\)
** addi\ts0,sp,16
** addi\ts0,sp,16
** csrr\tt0,vlenb
** slli\tt1,t0,1
** sub\tsp,sp,t1
** sub\tsp,sp,t0
** vs1r.v\tv1,0\(sp\)
** ...
** addi\ta2,a2,23
** andi\ta2,a2,-16
** sub\tsp,sp,a2
** addi\ta0,sp,15
** andi\ta0,a0,-16
** call\tf
** ...
** lw\tra,12\(sp\)
** lw\ts0,8\(sp\)

4
gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
View file

@ -69,5 +69,5 @@ test_vundefined_u64m4x2 ()
return __riscv_vundefined_u64m4x2 ();
}
/* { dg-final { scan-assembler-times {vse[0-9]+\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 18 } } */
/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */
/* { dg-final { scan-assembler-times {vse[0-9]+\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 0 } } */
/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 0 } } */

7
gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
View file

@ -254,7 +254,6 @@ test_vcreate_v_i64m2x4 (vint64m2_t v0, vint64m2_t v1, vint64m2_t v2,
return __riscv_vcreate_v_i64m2x4 (v0, v1, v2, v3);
}
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 7 } } */
/* { dg-final { scan-assembler-times {v[ls]e16\.v\s+v[0-9]+,\s*0\([0-9a-x]+\)} 70 } } */
/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([0-9a-x]+\)} 110 } } */
/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x0-9]+\)} 81 } } */
/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 24 } } */
/* { dg-final { scan-assembler-times {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vmv4r.v\s+v[0-9]+,\s*v[0-9]+} 16 } } */

3
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
View file

@ -11,4 +11,5 @@ vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
}
/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */
/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */

12
gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
View file

@ -72,17 +72,7 @@ vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) {
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 8 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 7 } } */
/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */
/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 2 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
View file

@ -187,20 +187,9 @@ vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) {
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 18 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 6 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 5 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 7 } } */
/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */
/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */
/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */

2
gcc/testsuite/lib/target-supports.exp
View file

@ -11769,13 +11769,11 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} elseif [istarget riscv*-*-*] {
if [check_effective_target_riscv_v] {
lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
set dg-do-what-default run
} else {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
set dg-do-what-default compile
}
} elseif [istarget loongarch*-*-*] {