diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b459fc717bc..63f746b2c25 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,52 @@
+2023-12-29  Jan Hubicka  <jh@suse.cz>
+
+	* config/i386/x86-tune.def (X86_TUNE_AVOID_128FMA_CHAINS,
+	X86_TUNE_AVOID_256FMA_CHAINS): Enable for znver4 and Core.
+
+2023-12-29  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/110625
+	* config/aarch64/aarch64.cc (aarch64_vector_costs::add_stmt_cost):
+	Adjust throughput and latency calculations for vector conversions.
+	(class aarch64_vector_costs): Add m_num_last_promote_demote.
+
+2023-12-29  Xi Ruoyao  <xry111@xry111.site>
+
+	* config/loongarch/loongarch.md (bstrins_<mode>_for_ior_mask):
+	For the condition, remove unneeded trailing "\" and move "&&" to
+	follow GNU coding style.  NFC.
+
+2023-12-29  Xi Ruoyao  <xry111@xry111.site>
+
+	* config/loongarch/predicates.md
+	(symbolic_pcrel_offset_operand): New define_predicate.
+	(mem_simple_ldst_operand): Likewise.
+	* config/loongarch/loongarch-protos.h
+	(loongarch_rewrite_mem_for_simple_ldst): Declare.
+	* config/loongarch/loongarch.cc
+	(loongarch_rewrite_mem_for_simple_ldst): Implement.
+	* config/loongarch/loongarch.md (simple_load<mode>): New
+	define_insn_and_rewrite.
+	(simple_load_<su>ext<SUBDI:mode><GPR:mode>): Likewise.
+	(simple_store<mode>): Likewise.
+	(define_peephole2): Remove la.local/[f]ld peepholes.
+
+2023-12-29  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/113133
+	* config/i386/i386.md
+	(TARGET_USE_VECTOR_FP_CONVERTS SF->DF float_extend splitter):
+	Do not handle xmm16+ with TARGET_EVEX512.
+
+2023-12-29  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/riscv-v.cc (is_vlmax_len_p): New function.
+	(expand_load_store): Disallow transformation into VLMAX when len is in range of [0,31]
+	(expand_cond_len_op): Ditto.
+	(expand_gather_scatter): Ditto.
+	(expand_lanes_load_store): Ditto.
+	(expand_fold_extract_last): Ditto.
+
 2023-12-28  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/i386.cc (ix86_unary_operator_ok): Move from here...
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index df708b5dec6..be4676c0042 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20231229
+20231230
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 51eea2b960b..6cfc025725d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,39 @@
+2023-12-29  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/110625
+	* gcc.target/aarch64/pr110625_4.c: New test.
+	* gcc.target/aarch64/sve/unpack_fcvt_signed_1.c: Add
+	--param aarch64-sve-compare-costs=0.
+	* gcc.target/aarch64/sve/unpack_fcvt_unsigned_1.c: Likewise
+
+2023-12-29  Xi Ruoyao  <xry111@xry111.site>
+
+	* gcc.target/loongarch/explicit-relocs-auto-single-load-store-2.c:
+	New test.
+	* gcc.target/loongarch/explicit-relocs-auto-single-load-store-3.c:
+	New test.
+
+2023-12-29  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/113133
+	* gcc.target/i386/pr113133-1.c: New test.
+	* gcc.target/i386/pr113133-2.c: New test.
+
+2023-12-29  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	PR testsuite/113167
+	* gcc.dg/tree-ssa/gen-vect-26.c: Mark the test/check loop
+	as novector.
+
+2023-12-29  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Remove redundant checks.
+
+2023-12-29  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/post-ra-avl.c: Adapt test.
+	* gcc.target/riscv/rvv/base/vf_avl-2.c: New test.
+
 2023-12-28  David Edelsohn  <dje.gcc@gmail.com>
 
 	* g++.dg/template/linkage2.C: XFAIL on AIX.