i386-opts.h (enum prefer_vector_width): Added new enum for the new option -mprefer-vector-width=[none|128|256|512].
* config/i386/i386-opts.h (enum prefer_vector_width): Added new enum for the new option -mprefer-vector-width=[none|128|256|512]. * config/i386/i386.c (ix86_target_string): remove old style options -mprefer-avx256 and make -mprefer-avx128 as alias. (ix86_option_override_internal): Apply defaults for the -mprefer-vector-width=[128|256] option. * config/i386/i386.h (TARGET_PREFER_AVX128, TARGET_PREFER_AVX256): Implement macros to work with -mprefer-vector-width=. * config/i386/i386.opt: Implemented option -mprefer-vector-width=[none|128|256|512]. * doc/invoke.texi: Documentation for -mprefer-vector-width=[none|128|256|512]. gcc/testsuite/ * g++.dg/ext/pr57362.C (__attribute__): Test prefer-vector-width=[128|256] target attribute. * gcc.target/i386/avx512f-constant-float-return.c (dg-optioins): Use -mprefer-vector-width=256 instead of -mprefer-avx256. * gcc.target/i386/avx512f-prefer.c: Ditto. * gcc.target/i386/pr82460-2.c: Ditto. From-SVN: r255030
This commit is contained in:
Sergey Shalnov
Uros Bizjak
parent
84fa214dea
commit
ab2c4ec8dc
11 changed files with 93 additions and 21 deletions
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@ -1,3 +1,18 @@
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2017-11-21 Sergey Shalnov <Sergey.Shalnov@intel.com>
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* config/i386/i386-opts.h (enum prefer_vector_width): Added new enum
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for the new option -mprefer-vector-width=[none|128|256|512].
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* config/i386/i386.c (ix86_target_string): remove old style options
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-mprefer-avx256 and make -mprefer-avx128 as alias.
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(ix86_option_override_internal): Apply defaults for the
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-mprefer-vector-width=[128|256] option.
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* config/i386/i386.h (TARGET_PREFER_AVX128, TARGET_PREFER_AVX256):
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Implement macros to work with -mprefer-vector-width=.
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* config/i386/i386.opt: Implemented option
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-mprefer-vector-width=[none|128|256|512].
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* doc/invoke.texi: Documentation for
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-mprefer-vector-width=[none|128|256|512].
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2017-11-21 Pat Haugen <pthaugen@us.ibm.com>
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* config/rs6000/ppc-asm.h (f50, vs50): Fix values.
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@ -99,4 +99,11 @@ enum stack_protector_guard {
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SSP_GLOBAL /* global canary */
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};
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enum prefer_vector_width {
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PVW_NONE,
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PVW_AVX128,
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PVW_AVX256,
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PVW_AVX512
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};
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#endif
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@ -2847,15 +2847,13 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
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{ "-mstv", MASK_STV },
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{ "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD },
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{ "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE },
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{ "-mprefer-avx128", MASK_PREFER_AVX128 },
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{ "-mcall-ms2sysv-xlogues", MASK_CALL_MS2SYSV_XLOGUES }
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};
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/* Additional flag options. */
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static struct ix86_target_opts flag2_opts[] =
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{
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{ "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY },
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{ "-mprefer-avx256", OPTION_MASK_PREFER_AVX256 },
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{ "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY }
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};
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const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (isa2_opts)
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@ -4686,16 +4684,18 @@ ix86_option_override_internal (bool main_args_p,
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if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL]
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&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE))
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opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
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/* Enable 128-bit AVX instruction generation
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for the auto-vectorizer. */
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if (TARGET_AVX128_OPTIMAL
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&& !(opts_set->x_target_flags & MASK_PREFER_AVX128))
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opts->x_target_flags |= MASK_PREFER_AVX128;
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/* Use 256-bit AVX instructions instead of 512-bit AVX instructions
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&& (opts_set->x_prefer_vector_width_type == PVW_NONE))
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opts->x_prefer_vector_width_type = PVW_AVX128;
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/* Use 256-bit AVX instruction generation
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in the auto-vectorizer. */
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if (ix86_tune_features[X86_TUNE_AVX256_OPTIMAL]
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&& !(opts_set->x_ix86_target_flags & OPTION_MASK_PREFER_AVX256))
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opts->x_ix86_target_flags |= OPTION_MASK_PREFER_AVX256;
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&& (opts_set->x_prefer_vector_width_type == PVW_NONE))
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opts->x_prefer_vector_width_type = PVW_AVX256;
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if (opts->x_ix86_recip_name)
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{
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@ -2678,6 +2678,11 @@ extern void debug_dispatch_window (int);
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#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
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#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
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/* Use 128-bit AVX instructions in the auto-vectorizer. */
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#define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
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/* Use 256-bit AVX instructions in the auto-vectorizer. */
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#define TARGET_PREFER_AVX256 (prefer_vector_width_type == PVW_AVX256)
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#define IX86_HLE_ACQUIRE (1 << 16)
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#define IX86_HLE_RELEASE (1 << 17)
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@ -182,6 +182,10 @@ int x_ix86_tune_no_default
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TargetSave
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enum ix86_veclibabi x_ix86_veclibabi_type
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;; -mprefer-vector-width=
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TargetSave
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enum prefer_vector_width x_prefer_vector_width_type
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;; x86 options
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m128bit-long-double
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Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
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@ -588,12 +592,28 @@ Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
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or znver1 and Haifa scheduling is selected.
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mprefer-avx128
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Target Report Mask(PREFER_AVX128) Save
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Target Alias(mprefer-vector-width=, 128, 256)
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Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
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mprefer-avx256
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Target Report Mask(PREFER_AVX256) Var(ix86_target_flags) Save
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Use 256-bit AVX instructions instead of 512-bit AVX instructions in the auto-vectorizer.
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mprefer-vector-width=
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Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE)
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Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
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Enum
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Name(prefer_vector_width) Type(enum prefer_vector_width)
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Known preferred register vector length (to use with the -mprefer-vector-width= option)
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EnumValue
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Enum(prefer_vector_width) String(none) Value(PVW_NONE)
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EnumValue
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Enum(prefer_vector_width) String(128) Value(PVW_AVX128)
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EnumValue
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Enum(prefer_vector_width) String(256) Value(PVW_AVX256)
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EnumValue
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Enum(prefer_vector_width) String(512) Value(PVW_AVX512)
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;; ISA support
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@ -1196,7 +1196,7 @@ See RS/6000 and PowerPC Options.
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-mincoming-stack-boundary=@var{num} @gol
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-mcld -mcx16 -msahf -mmovbe -mcrc32 @gol
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-mrecip -mrecip=@var{opt} @gol
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-mvzeroupper -mprefer-avx128 -mprefer-avx256 @gol
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-mvzeroupper -mprefer-avx128 -mprefer-vector-width=@var{opt} @gol
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-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
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-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -mavx512vl @gol
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-mavx512bw -mavx512dq -mavx512ifma -mavx512vbmi -msha -maes @gol
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@ -26095,10 +26095,24 @@ intrinsics.
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This option instructs GCC to use 128-bit AVX instructions instead of
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256-bit AVX instructions in the auto-vectorizer.
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@item -mprefer-avx256
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@opindex mprefer-avx256
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This option instructs GCC to use 256-bit AVX instructions instead of
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512-bit AVX instructions in the auto-vectorizer.
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@item -mprefer-vector-width=@var{opt}
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@opindex mprefer-vector-width
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This option instructs GCC to use @var{opt}-bit vector width in instructions
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instead of default on the selected platform.
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@table @samp
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@item none
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No extra limitations applied to GCC other than defined by the selected platform.
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@item 128
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Prefer 128-bit vector width for instructions.
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@item 256
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Prefer 256-bit vector width for instructions.
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@item 512
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Prefer 512-bit vector width for instructions.
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@end table
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@item -mcx16
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@opindex mcx16
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@ -1,3 +1,12 @@
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2017-11-21 Sergey Shalnov <Sergey.Shalnov@intel.com>
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* g++.dg/ext/pr57362.C (__attribute__): Test
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prefer-vector-width=[128|256] target attribute.
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* gcc.target/i386/avx512f-constant-float-return.c (dg-optioins):
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Use -mprefer-vector-width=256 instead of -mprefer-avx256.
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* gcc.target/i386/avx512f-prefer.c: Ditto.
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* gcc.target/i386/pr82460-2.c: Ditto.
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2017-11-21 Martin Liska <mliska@suse.cz>
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* g++.dg/cpp0x/constexpr-48089.C: Add quotes for constexpr
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@ -81,7 +81,9 @@ __attribute__((target("dispatch-scheduler")))
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int foo(void) { return 1; }
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__attribute__((target("prefer-avx128")))
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int foo(void) { return 1; }
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__attribute__((target("prefer-avx256")))
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__attribute__((target("prefer-vector-width=128")))
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int foo(void) { return 1; }
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__attribute__((target("prefer-vector-width=256")))
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int foo(void) { return 1; }
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__attribute__((target("32")))
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int foo(void) { return 1; }
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
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/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
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/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
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float
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
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/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
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/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
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/* { dg-final { scan-assembler "vmulpd" } } */
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@ -1,6 +1,6 @@
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/* PR target/82460 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mno-prefer-avx256" } */
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/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mprefer-vector-width=none" } */
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/* We want to reuse the permutation mask in the loop, so use vpermt2b rather
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than vpermi2b. */
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/* { dg-final { scan-assembler-not {\mvpermi2b\M} } } */
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