RISC-V: Using merge approach to optimize repeating sequence in vec_init
This patch would like to optimize the VLS vector initialization like
repeating sequence. From the vslide1down to the vmerge with a simple
cost model, aka every instruction only has 1 cost.
Given code with -march=rv64gcv_zvl256b --param riscv-autovec-preference=fixed-vlmax
typedef int64_t vnx32di __attribute__ ((vector_size (256)));
__attribute__ ((noipa)) void
f_vnx32di (int64_t a, int64_t b, int64_t *out)
{
vnx32di v = {
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
};
*(vnx32di *) out = v;
}
Before this patch:
vslide1down.vx (x31 times)
After this patch:
li a5,-1431654400
addi a5,a5,-1365
li a3,-1431654400
addi a3,a3,-1366
slli a5,a5,32
add a5,a5,a3
vsetvli a4,zero,e64,m8,ta,ma
vmv.v.x v8,a0
vmv.s.x v0,a5
vmerge.vxm v8,v8,a1,v0
vs8r.v v8,0(a2)
Since we dont't have SEW = 128 in vec_duplicate, we can't combine ab into
SEW = 128 element and then broadcast this big element.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (enum insn_type): New type.
* config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
(rvv_builder::can_duplicate_repeating_sequence_p): Align the referenced
class member.
(rvv_builder::get_merged_repeating_sequence): Ditto.
(rvv_builder::repeating_sequence_use_merge_profitable_p): New function
to evaluate the optimization cost.
(rvv_builder::get_merge_scalar_mask): New function to get the merge
mask.
(emit_scalar_move_insn): New function to emit vmv.s.x.
(emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
(emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
vmv.v.x.
(get_repeating_sequence_dup_machine_mode): New function to get the dup
machine mode.
(expand_vector_init_merge_repeating_sequence): New function to perform
the optimization.
(expand_vec_init): Add this vector init optimization.
* config/riscv/riscv.h (BITS_PER_WORD): New macro.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li
parent
8d1d9b1648
commit
a99dc11fe2
11 changed files with 457 additions and 6 deletions
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@ -142,6 +142,7 @@ enum insn_type
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RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand. */
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RVV_UNOP_MU = RVV_UNOP + 2, /* Likewise. */
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RVV_TERNOP = 5,
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RVV_SCALAR_MOV_OP = 4, /* +1 for VUNDEF according to vector.md. */
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};
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enum vlmul_type
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{
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@ -21,6 +21,10 @@
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#define IN_TARGET_CODE 1
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/* We have a maximum of 11 operands for RVV instruction patterns according to
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the vector.md. */
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#define RVV_INSN_OPERANDS_MAX 11
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#include "config.h"
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#include "system.h"
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#include "coretypes.h"
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@ -1286,19 +1290,32 @@ public:
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: rtx_vector_builder (mode, npatterns, nelts_per_pattern)
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{
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m_inner_mode = GET_MODE_INNER (mode);
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m_inner_size = GET_MODE_BITSIZE (m_inner_mode).to_constant ();
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m_inner_bits_size = GET_MODE_BITSIZE (m_inner_mode);
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m_inner_bytes_size = GET_MODE_SIZE (m_inner_mode);
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gcc_assert (
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int_mode_for_size (inner_bits_size (), 0).exists (&m_inner_int_mode));
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}
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bool can_duplicate_repeating_sequence_p ();
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rtx get_merged_repeating_sequence ();
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bool repeating_sequence_use_merge_profitable_p ();
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rtx get_merge_scalar_mask (unsigned int) const;
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machine_mode new_mode () const { return m_new_mode; }
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scalar_mode inner_mode () const { return m_inner_mode; }
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scalar_int_mode inner_int_mode () const { return m_inner_int_mode; }
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unsigned int inner_bits_size () const { return m_inner_bits_size; }
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unsigned int inner_bytes_size () const { return m_inner_bytes_size; }
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private:
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machine_mode m_inner_mode;
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scalar_mode m_inner_mode;
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scalar_int_mode m_inner_int_mode;
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machine_mode m_new_mode;
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scalar_int_mode m_new_inner_mode;
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unsigned int m_inner_size;
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unsigned int m_inner_bits_size;
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unsigned int m_inner_bytes_size;
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};
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/* Return true if the vector duplicated by a super element which is the fusion
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@ -1309,7 +1326,7 @@ bool
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rvv_builder::can_duplicate_repeating_sequence_p ()
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{
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poly_uint64 new_size = exact_div (full_nelts (), npatterns ());
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unsigned int new_inner_size = m_inner_size * npatterns ();
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unsigned int new_inner_size = m_inner_bits_size * npatterns ();
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if (!int_mode_for_size (new_inner_size, 0).exists (&m_new_inner_mode)
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|| GET_MODE_SIZE (m_new_inner_mode) > UNITS_PER_WORD
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|| !get_vector_mode (m_new_inner_mode, new_size).exists (&m_new_mode))
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@ -1317,6 +1334,61 @@ rvv_builder::can_duplicate_repeating_sequence_p ()
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return repeating_sequence_p (0, full_nelts ().to_constant (), npatterns ());
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}
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/* Return true if it is a repeating sequence that using
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merge approach has better codegen than using default
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approach (slide1down).
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Sequence A:
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{a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b}
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nelts = 16
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npatterns = 2
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for merging a we need mask 101010....
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for merging b we need mask 010101....
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Foreach element in the npattern, we need to build a mask in scalar register.
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Mostely we need 3 instructions (aka COST = 3), which is consist of 2 scalar
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instruction and 1 scalar move to v0 register. Finally we need vector merge
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to merge them.
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lui a5, #imm
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add a5, #imm
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vmov.s.x v0, a5
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vmerge.vxm v9, v9, a1, v0
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So the overall (roughly) COST of Sequence A = (3 + 1) * npatterns = 8.
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If we use slide1down, the COST = nelts = 16 > 8 (COST of merge).
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So return true in this case as it is profitable.
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Sequence B:
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{a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h}
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nelts = 16
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npatterns = 8
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COST of merge approach = (3 + 1) * npatterns = 24
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COST of slide1down approach = nelts = 16
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Return false in this case as it is NOT profitable in merge approach.
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*/
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bool
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rvv_builder::repeating_sequence_use_merge_profitable_p ()
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{
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if (inner_bytes_size () > UNITS_PER_WORD)
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return false;
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unsigned int nelts = full_nelts ().to_constant ();
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if (!repeating_sequence_p (0, nelts, npatterns ()))
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return false;
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unsigned int merge_cost = 1;
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unsigned int build_merge_mask_cost = 3;
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unsigned int slide1down_cost = nelts;
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return (build_merge_mask_cost + merge_cost) * npatterns () < slide1down_cost;
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}
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/* Merge the repeating sequence into a single element and return the RTX. */
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rtx
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rvv_builder::get_merged_repeating_sequence ()
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@ -1324,11 +1396,11 @@ rvv_builder::get_merged_repeating_sequence ()
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scalar_int_mode mode = Pmode;
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rtx target = gen_reg_rtx (mode);
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emit_move_insn (target, const0_rtx);
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rtx imm = gen_int_mode ((1ULL << m_inner_size) - 1, mode);
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rtx imm = gen_int_mode ((1ULL << m_inner_bits_size) - 1, mode);
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/* { a, b, a, b }: Generate duplicate element = b << bits | a. */
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for (unsigned int i = 0; i < npatterns (); i++)
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{
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unsigned int loc = m_inner_size * i;
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unsigned int loc = m_inner_bits_size * i;
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rtx shift = gen_int_mode (loc, mode);
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rtx ele = gen_lowpart (mode, elt (i));
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rtx tmp = expand_simple_binop (mode, AND, ele, imm, NULL_RTX, false,
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@ -1344,6 +1416,29 @@ rvv_builder::get_merged_repeating_sequence ()
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return target;
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}
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/* Get the mask for merge approach.
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Consider such following case:
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{a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b}
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To merge "a", the mask should be 1010....
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To merge "b", the mask should be 0101....
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*/
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rtx
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rvv_builder::get_merge_scalar_mask (unsigned int index_in_pattern) const
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{
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unsigned HOST_WIDE_INT mask = 0;
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unsigned HOST_WIDE_INT base_mask = (1ULL << index_in_pattern);
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gcc_assert (BITS_PER_WORD % npatterns () == 0);
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int limit = BITS_PER_WORD / npatterns ();
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for (int i = 0; i < limit; i++)
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mask |= base_mask << (i * npatterns ());
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return gen_int_mode (mask, inner_int_mode ());
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}
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/* Subroutine of riscv_vector_expand_vector_init.
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Works as follows:
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(a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
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@ -1371,6 +1466,111 @@ expand_vector_init_insert_elems (rtx target, const rvv_builder &builder,
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}
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}
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/* Emit vmv.s.x instruction. */
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static void
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emit_scalar_move_insn (unsigned icode, rtx *ops)
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{
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machine_mode data_mode = GET_MODE (ops[0]);
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machine_mode mask_mode = get_mask_mode (data_mode).require ();
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insn_expander<RVV_INSN_OPERANDS_MAX> e (riscv_vector::RVV_SCALAR_MOV_OP,
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/* HAS_DEST_P */ true,
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/* FULLY_UNMASKED_P */ false,
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/* USE_REAL_MERGE_P */ true,
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/* HAS_AVL_P */ true,
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/* VLMAX_P */ false,
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data_mode, mask_mode);
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e.set_policy (TAIL_ANY);
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e.set_policy (MASK_ANY);
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e.set_vl (CONST1_RTX (Pmode));
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e.emit_insn ((enum insn_code) icode, ops);
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}
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/* Emit vmv.v.x instruction with vlmax. */
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static void
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emit_vlmax_integer_move_insn (unsigned icode, rtx *ops, rtx vl)
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{
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emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ops, vl);
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}
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/* Emit vmv.v.x instruction with nonvlmax. */
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static void
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emit_nonvlmax_integer_move_insn (unsigned icode, rtx *ops, rtx avl)
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{
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emit_nonvlmax_insn (icode, riscv_vector::RVV_UNOP, ops, avl);
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}
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/* Emit merge instruction. */
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static machine_mode
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get_repeating_sequence_dup_machine_mode (const rvv_builder &builder)
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{
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poly_uint64 dup_nunits = GET_MODE_NUNITS (builder.mode ());
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if (known_ge (GET_MODE_SIZE (builder.mode ()), BYTES_PER_RISCV_VECTOR))
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{
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dup_nunits = exact_div (BYTES_PER_RISCV_VECTOR,
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builder.inner_bytes_size ());
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}
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return get_vector_mode (builder.inner_int_mode (), dup_nunits).require ();
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}
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/* Use merge approach to initialize the vector with repeating sequence.
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v = {a, b, a, b, a, b, a, b}.
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v = broadcast (a).
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mask = 0b01010101....
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v = merge (v, b, mask)
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*/
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static void
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expand_vector_init_merge_repeating_sequence (rtx target,
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const rvv_builder &builder)
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{
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machine_mode dup_mode = get_repeating_sequence_dup_machine_mode (builder);
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machine_mode dup_mask_mode = get_mask_mode (dup_mode).require ();
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machine_mode mask_mode = get_mask_mode (builder.mode ()).require ();
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uint64_t full_nelts = builder.full_nelts ().to_constant ();
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/* Step 1: Broadcast the first pattern. */
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rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))};
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emit_vlmax_integer_move_insn (code_for_pred_broadcast (builder.mode ()),
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ops, NULL_RTX);
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/* Step 2: Merge the rest iteration of pattern. */
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for (unsigned int i = 1; i < builder.npatterns (); i++)
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{
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/* Step 2-1: Generate mask register v0 for each merge. */
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rtx merge_mask = builder.get_merge_scalar_mask (i);
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rtx mask = gen_reg_rtx (mask_mode);
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rtx dup = gen_reg_rtx (dup_mode);
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if (full_nelts <= BITS_PER_WORD) /* vmv.s.x. */
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{
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rtx ops[] = {dup, gen_scalar_move_mask (dup_mask_mode),
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RVV_VUNDEF (dup_mode), merge_mask};
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emit_scalar_move_insn (code_for_pred_broadcast (GET_MODE (dup)),
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ops);
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}
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else /* vmv.v.x. */
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{
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rtx ops[] = {dup, force_reg (GET_MODE_INNER (dup_mode), merge_mask)};
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rtx vl = gen_int_mode (CEIL (full_nelts, BITS_PER_WORD), Pmode);
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emit_nonvlmax_integer_move_insn (code_for_pred_broadcast (dup_mode),
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ops, vl);
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}
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emit_move_insn (mask, gen_lowpart (mask_mode, dup));
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/* Step 2-2: Merge pattern according to the mask. */
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rtx ops[] = {target, target, builder.elt (i), mask};
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emit_vlmax_merge_insn (code_for_pred_merge_scalar (GET_MODE (target)),
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riscv_vector::RVV_MERGE_OP, ops);
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}
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}
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/* Initialize register TARGET from the elements in PARALLEL rtx VALS. */
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void
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@ -1394,6 +1594,19 @@ expand_vec_init (rtx target, rtx vals)
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emit_move_insn (target, gen_lowpart (mode, dup));
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return;
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}
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/* Case 2: Optimize repeating sequence cases that Case 1 can
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not handle and it is profitable. For example:
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ELEMENT BITSIZE = 64.
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v = {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b}.
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We can't find a vector mode for "ab" which will be combined into
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128-bit element to duplicate. */
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if (v.repeating_sequence_use_merge_profitable_p ())
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{
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expand_vector_init_merge_repeating_sequence (target, v);
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return;
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}
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/* TODO: We will support more Initialization of vector in the future. */
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}
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@ -150,6 +150,7 @@ ASM_MISA_SPEC
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/* Width of a word, in units (bytes). */
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#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
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#define BITS_PER_WORD (BITS_PER_UNIT * UNITS_PER_WORD)
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#ifndef IN_LIBGCC2
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#define MIN_UNITS_PER_WORD 4
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#endif
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@ -0,0 +1,21 @@
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/* { dg-do compile } */
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/* { dg-additional-options "-march=rv64gcv_zvl1024b -mabi=lp64d" } */
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#include <stdint-gcc.h>
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typedef int64_t vnx16di __attribute__ ((vector_size (1024)));
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__attribute__ ((noipa)) void
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f_vnx16di (int64_t a, int64_t b, int64_t *out)
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{
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vnx16di v = {
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a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b,
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a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b,
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a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b,
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a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b,
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};
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*(vnx16di *) out = v;
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}
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/* { dg-final { scan-assembler-times {vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */
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/* { dg-final { scan-assembler-times {vmerge\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0} 1 } } */
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@ -0,0 +1,24 @@
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/* { dg-do compile } */
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/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
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#include <stdint-gcc.h>
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typedef double vnx8df __attribute__ ((vector_size (64)));
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typedef double vnx16df __attribute__ ((vector_size (128)));
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|
||||
__attribute__ ((noipa)) void
|
||||
f_vnx8df (double a, double b, double *out)
|
||||
{
|
||||
vnx8df v = {a, b, a, b, a, b, a, b};
|
||||
*(vnx8df *) out = v;
|
||||
}
|
||||
|
||||
__attribute__ ((noipa)) void
|
||||
f_vnx16df (double a, double b, double *out)
|
||||
{
|
||||
vnx16df v = {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b};
|
||||
*(vnx16df *) out = v;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {vmv\.s\.x\tv[0-9]+,\s*[a-x0-9]+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vfmerge\.vfm\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0} 1 } } */
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
|
||||
|
||||
#include <stdint-gcc.h>
|
||||
|
||||
typedef int64_t vnx8di __attribute__ ((vector_size (64)));
|
||||
typedef int64_t vnx16di __attribute__ ((vector_size (128)));
|
||||
|
||||
__attribute__ ((noipa)) void
|
||||
f_vnx8di (int64_t a, int64_t b, int64_t *out)
|
||||
{
|
||||
vnx8di v = {a, b, a, b, a, b, a, b};
|
||||
*(vnx8di *) out = v;
|
||||
}
|
||||
|
||||
__attribute__ ((noipa)) void
|
||||
f_vnx16di (int64_t a, int64_t b, int64_t *out)
|
||||
{
|
||||
vnx16di v = {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b};
|
||||
*(vnx16di *) out = v;
|
||||
}
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vmv\.s\.x\tv[0-9]+,\s*[a-x0-9]+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vmerge\.vxm\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0} 1 } } */
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
|
||||
|
||||
#include <stdint-gcc.h>
|
||||
|
||||
typedef int64_t vnx8di __attribute__ ((vector_size (64)));
|
||||
|
||||
__attribute__ ((noipa)) void
|
||||
f_vnx8di (int64_t a, int64_t b, int64_t c, int64_t d, int64_t *out)
|
||||
{
|
||||
vnx8di v = {a, b, c, d, a, b, c, d};
|
||||
*(vnx8di *) out = v;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 7 } } */
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
|
||||
|
||||
#include <stdint-gcc.h>
|
||||
|
||||
typedef int64_t vnx16di __attribute__ ((vector_size (128)));
|
||||
|
||||
__attribute__ ((noipa)) void
|
||||
f_vnx16di (int64_t a, int64_t b, int64_t c, int64_t d, int64_t *out)
|
||||
{
|
||||
vnx16di v = {a, b, c, d, a, b, c, d, a, b, c, d, a, b, c, d,};
|
||||
*(vnx16di *) out = v;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {vmv\.v\.x\tv[0-9]+,\s*[a-x0-9]+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vmv\.s\.x\tv[0-9]+,\s*[a-x0-9]+} 0 } } */
|
||||
/* { dg-final { scan-assembler-times {vmerge\.vxm\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0} 0 } } */
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/* { dg-do run { target { riscv_vector } } } */
|
||||
/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
|
||||
|
||||
#include "init-repeat-sequence-2.c"
|
||||
|
||||
int
|
||||
main ()
|
||||
{
|
||||
double a = -1789089.23423;
|
||||
double b = -8916156.45644;
|
||||
|
||||
double v_vnx8df[sizeof (vnx8df) / sizeof (double)];
|
||||
f_vnx8df (a, b, v_vnx8df);
|
||||
|
||||
return 0;
|
||||
for (int i = 0; i < sizeof (vnx8df) / sizeof (double); i++)
|
||||
{
|
||||
if (i % 2 == 0)
|
||||
{
|
||||
if (v_vnx8df[i] != a)
|
||||
__builtin_abort ();
|
||||
}
|
||||
else
|
||||
{
|
||||
if (v_vnx8df[i] != b)
|
||||
__builtin_abort ();
|
||||
}
|
||||
}
|
||||
|
||||
double v_vnx16df[sizeof (vnx16df) / sizeof (double)];
|
||||
f_vnx16df (a, b, v_vnx16df);
|
||||
for (int i = 0; i < sizeof (vnx16df) / sizeof (double); i++)
|
||||
{
|
||||
if (i % 2 == 0)
|
||||
{
|
||||
if (v_vnx16df[i] != a)
|
||||
__builtin_abort ();
|
||||
}
|
||||
else
|
||||
{
|
||||
if (v_vnx16df[i] != b)
|
||||
__builtin_abort ();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/* { dg-do run { target { riscv_vector } } } */
|
||||
/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
|
||||
|
||||
#include "init-repeat-sequence-3.c"
|
||||
|
||||
int
|
||||
main ()
|
||||
{
|
||||
int64_t a = -178908923423;
|
||||
int64_t b = -891615645644;
|
||||
|
||||
int64_t v_vnx8di[sizeof (vnx8di) / sizeof (int64_t)];
|
||||
f_vnx8di (a, b, v_vnx8di);
|
||||
for (int i = 0; i < sizeof (vnx8di) / sizeof (int64_t); i++)
|
||||
{
|
||||
if (i % 2 == 0)
|
||||
{
|
||||
if (v_vnx8di[i] != a)
|
||||
__builtin_abort ();
|
||||
}
|
||||
else
|
||||
{
|
||||
if (v_vnx8di[i] != b)
|
||||
__builtin_abort ();
|
||||
}
|
||||
}
|
||||
|
||||
int64_t v_vnx16di[sizeof (vnx16di) / sizeof (int64_t)];
|
||||
f_vnx16di (a, b, v_vnx16di);
|
||||
|
||||
for (int i = 0; i < sizeof (vnx16di) / sizeof (int64_t); i++)
|
||||
{
|
||||
if (i % 2 == 0)
|
||||
{
|
||||
if (v_vnx16di[i] != a)
|
||||
__builtin_abort ();
|
||||
}
|
||||
else
|
||||
{
|
||||
if (v_vnx16di[i] != b)
|
||||
__builtin_abort ();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* { dg-do run { target { riscv_vector } } } */
|
||||
/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
|
||||
|
||||
#include "init-repeat-sequence-5.c"
|
||||
|
||||
int
|
||||
main ()
|
||||
{
|
||||
int64_t a = -178908923423;
|
||||
int64_t b = -891615645644;
|
||||
int64_t c = 78908923423;
|
||||
int64_t d = 81615645644;
|
||||
|
||||
int64_t v_vnx16di[sizeof (vnx16di) / sizeof (int64_t)];
|
||||
f_vnx16di (a, b, c, d, v_vnx16di);
|
||||
for (int i = 0; i < sizeof (vnx16di) / sizeof (int64_t); i++)
|
||||
{
|
||||
if (i % 4 == 0)
|
||||
{
|
||||
if (v_vnx16di[i] != a)
|
||||
__builtin_abort ();
|
||||
}
|
||||
else if (i % 4 == 1)
|
||||
{
|
||||
if (v_vnx16di[i] != b)
|
||||
__builtin_abort ();
|
||||
}
|
||||
else if (i % 4 == 2)
|
||||
{
|
||||
if (v_vnx16di[i] != c)
|
||||
__builtin_abort ();
|
||||
}
|
||||
else
|
||||
{
|
||||
if (v_vnx16di[i] != d)
|
||||
__builtin_abort ();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue