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i386.md ("*movtf_internal): Penalize moves to and from integer registers.

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* config/i386/i386.md ("*movtf_internal): Penalize moves to and
        from integer registers.
        (FP mode splitters): Handle TFmode.

From-SVN: r125623
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Uros Bizjak 2007-06-11 18:06:19 +02:00 • committed by Uros Bizjak
parent 7a9007db0c
commit a91d32a4a6
2 changed files with 63 additions and 56 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2007-06-11 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md ("*movtf_internal): Penalize moves to and
from integer registers.
(FP mode splitters): Handle TFmode.
2007-06-11 Eric Botcazou <ebotcazou@adacore.com>
* tree-ssa-structalias.c (find_what_p_points_to): Return false

113
gcc/config/i386/i386.md
View file

@ -3015,6 +3015,59 @@
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")])
(define_expand "movtf"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "nonimmediate_operand" ""))]
"TARGET_64BIT"
{
ix86_expand_move (TFmode, operands);
DONE;
})
(define_insn "*movtf_internal"
[(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?r,?o")
(match_operand:TF 1 "general_operand" "xm,x,C,roF,Fr"))]
"TARGET_64BIT
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (which_alternative)
{
case 0:
case 1:
if (get_attr_mode (insn) == MODE_V4SF)
return "movaps\t{%1, %0|%0, %1}";
else
return "movdqa\t{%1, %0|%0, %1}";
case 2:
if (get_attr_mode (insn) == MODE_V4SF)
return "xorps\t%0, %0";
else
return "pxor\t%0, %0";
case 3:
case 4:
return "#";
default:
gcc_unreachable ();
}
}
[(set_attr "type" "ssemov,ssemov,sselog1,*,*")
(set (attr "mode")
(cond [(eq_attr "alternative" "0,2")
(if_then_else
(ne (symbol_ref "optimize_size")
(const_int 0))
(const_string "V4SF")
(const_string "TI"))
(eq_attr "alternative" "1")
(if_then_else
(ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
(const_int 0))
(ne (symbol_ref "optimize_size")
(const_int 0)))
(const_string "V4SF")
(const_string "TI"))]
(const_string "DI")))])
(define_split
[(set (match_operand 0 "nonimmediate_operand" "")
(match_operand 1 "general_operand" ""))]
@ -3067,7 +3120,8 @@
(float_extend (match_operand 1 "memory_operand" "")))]
"reload_completed
&& MEM_P (operands[1])
&& (GET_MODE (operands[0]) == XFmode
&& (GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == XFmode
|| GET_MODE (operands[0]) == SFmode
|| GET_MODE (operands[0]) == DFmode)
&& (operands[2] = find_constant_src (insn))"
@ -3128,64 +3182,11 @@
operands[1] = CONST1_RTX (<MODE>mode);
})
(define_expand "movtf"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "nonimmediate_operand" ""))]
"TARGET_64BIT"
{
ix86_expand_move (TFmode, operands);
DONE;
})
(define_insn "*movtf_internal"
[(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
(match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
"TARGET_64BIT
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (which_alternative)
{
case 0:
case 1:
return "#";
case 2:
if (get_attr_mode (insn) == MODE_V4SF)
return "xorps\t%0, %0";
else
return "pxor\t%0, %0";
case 3:
case 4:
if (get_attr_mode (insn) == MODE_V4SF)
return "movaps\t{%1, %0|%0, %1}";
else
return "movdqa\t{%1, %0|%0, %1}";
default:
gcc_unreachable ();
}
}
[(set_attr "type" "*,*,sselog1,ssemov,ssemov")
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(if_then_else
(ne (symbol_ref "optimize_size")
(const_int 0))
(const_string "V4SF")
(const_string "TI"))
(eq_attr "alternative" "4")
(if_then_else
(ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
(const_int 0))
(ne (symbol_ref "optimize_size")
(const_int 0)))
(const_string "V4SF")
(const_string "TI"))]
(const_string "DI")))])
(define_split
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "general_operand" ""))]
"reload_completed && !SSE_REG_P (operands[0])
&& !SSE_REG_P (operands[1])"
"reload_completed
&& !(SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]))"
[(const_int 0)]
"ix86_split_long_move (operands); DONE;")