i386: Remove unneeded binary operand fixup from expanders.
There is no need to call ix86_fixup_binary_operands when there are only one or no memory operands allowed. 2021-05-27 Uroš Bizjak <ubizjak@gmail.com> gcc/ * config/i386/mmx.md (addv2sf3): Do not call ix86_fixup_binary_operands_no_copy. (subv2sf3): Ditto. (mulv2sf3): Ditto. (<smaxmin:code>v2sf3): Ditto. (<plusminus:insn><MMXMODEI:mode>3): Ditto. (<plusminus:insn><VI_32:mode>3): Remove expander. (<plusminus:insn><VI_32:mode>3): Rename from "*<plusminus:insn><VI_32:mode>3". (mulv4hi): Do not call ix86_fixup_binary_operands_no_copy. (mulv2hi3): Remove expander. (mulv2hi3): Rename from *mulv2hi3. (<s>mulv2hi3_highpart): Remove expander. (<s>mulv2hi3_highpart): Rename from *<s>mulv2hi3_highpart. (<smaxmin:code><MMXMODE14:mode>3): Rename from "*mmx_<smaxmin:code><MMXMODE14:mode>3". (<smaxmin:code><SMAXMIN_MMXMODEI:mode>3): Remove expander. (SMAXMIN_MMXMODEI): Remove mode iterator. (<smaxmin:code>v4hi3): New expander. (<smaxmin:code>v4qi3): Rename from *<smaxmin:code>v4qi3. (<smaxmin:code>v2hi3): Rename from *<smaxmin:code>v2hi3. (<smaxmin:code><SMAXMIN_VI_32:mode>3): Remove expander. (SMAXMIN_VI_32): Remove mode iterator. (<umaxmin:code><MMXMODE24:mode>3): Rename from "*mmx_<umaxmin:code><MMXMODE24:mode>3". (<umaxmin:code><UMAXMIN_MMXMODEI:mode>3): Remove expander. (UMAXMIN_MMXMODEI): Remove mode iterator. (<umaxmin:code>v8qi3): New expander. (<umaxmin:code>v4qi3): Rename from *<umaxmin:code>v4qi3. (<umaxmin:code>v2hi3): Rename from *<umaxmin:code>v2hi3. (<umaxmin:code><SMAXMIN_VI_32:mode>3): Remove expander. (UMAXMIN_VI_32): Remove mode iterator. (<any_shift:insn>v2hi3): Remove expander. (<any_shift:insn>v2hi3): Rename from *<any_shift:insn>v2hi3. (<any_logic:code><MMXMODEI:mode>3): Do not call ix86_fixup_binary_operands_no_copy. (<any_logic:code><VI_32:mode>3): Remove expander. (<any_logic:code><VI_32:mode>3): Rename from "*<any_logic:code><VI_32:mode>3". (uavg<mode>3_ceil): Do not call ix86_fixup_binary_operands_no_copy. * config/i386/sse.md (div<VF2:mode>3): Do not call ix86_fixup_binary_operands_no_copy. (div<VF1:mode>3): Ditto. (<maxmin:code><VI8_AVX2_AVX512F:mode>3): Ditto. (smulhrsv4hi3): Ditto. (smulhrsv2hi3): Ditto.
This commit is contained in:
Uros Bizjak
parent
5d05e83e24
commit
a617e5d516
2 changed files with 56 additions and 160 deletions
|
|
@ -417,8 +417,7 @@
|
|||
(plus:V2SF
|
||||
(match_operand:V2SF 1 "register_operand")
|
||||
(match_operand:V2SF 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_insn "*mmx_addv2sf3"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=y,x,v")
|
||||
|
|
@ -455,8 +454,7 @@
|
|||
(minus:V2SF
|
||||
(match_operand:V2SF 1 "register_operand")
|
||||
(match_operand:V2SF 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (MINUS, V2SFmode, operands);")
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_insn "*mmx_subv2sf3"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=y,y,x,v")
|
||||
|
|
@ -489,8 +487,7 @@
|
|||
(mult:V2SF
|
||||
(match_operand:V2SF 1 "register_operand")
|
||||
(match_operand:V2SF 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_insn "*mmx_mulv2sf3"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=y,x,v")
|
||||
|
|
@ -542,8 +539,6 @@
|
|||
(operands[0], operands[1], operands[2]));
|
||||
DONE;
|
||||
}
|
||||
else
|
||||
ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
|
||||
})
|
||||
|
||||
;; These versions of the min/max patterns are intentionally ignorant of
|
||||
|
|
@ -709,7 +704,7 @@
|
|||
(vec_select:SF
|
||||
(match_dup 1)
|
||||
(parallel [(match_operand:SI 3 "const_0_to_1_operand")]))))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSE3
|
||||
"TARGET_SSE3 && TARGET_MMX_WITH_SSE
|
||||
&& INTVAL (operands[2]) != INTVAL (operands[3])"
|
||||
"@
|
||||
haddps\t{%0, %0|%0, %0}
|
||||
|
|
@ -747,7 +742,7 @@
|
|||
(vec_select:SF
|
||||
(match_dup 1)
|
||||
(parallel [(const_int 1)]))))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSE3"
|
||||
"TARGET_SSE3 && TARGET_MMX_WITH_SSE"
|
||||
"@
|
||||
hsubps\t{%0, %0|%0, %0}
|
||||
vhsubps\t{%1, %1, %0|%0, %1, %1}"
|
||||
|
|
@ -1091,7 +1086,7 @@
|
|||
(define_insn "fixuns_truncv2sfv2si2"
|
||||
[(set (match_operand:V2SI 0 "register_operand" "=v")
|
||||
(unsigned_fix:V2SI (match_operand:V2SF 1 "register_operand" "v")))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_AVX512VL"
|
||||
"TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
|
||||
"vcvttps2udq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "evex")
|
||||
|
|
@ -1119,7 +1114,7 @@
|
|||
(define_insn "floatunsv2siv2sf2"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=v")
|
||||
(unsigned_float:V2SF (match_operand:V2SI 1 "register_operand" "v")))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_AVX512VL"
|
||||
"TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
|
||||
"vcvtudq2ps\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "evex")
|
||||
|
|
@ -1361,8 +1356,7 @@
|
|||
(plusminus:MMXMODEI
|
||||
(match_operand:MMXMODEI 1 "register_operand")
|
||||
(match_operand:MMXMODEI 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_insn "*mmx_<insn><mode>3"
|
||||
[(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,<Yv_Yw>")
|
||||
|
|
@ -1390,21 +1384,12 @@
|
|||
"TARGET_SSE2"
|
||||
"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
|
||||
|
||||
(define_expand "<insn><mode>3"
|
||||
[(set (match_operand:VI_32 0 "register_operand")
|
||||
(plusminus:VI_32
|
||||
(match_operand:VI_32 1 "register_operand")
|
||||
(match_operand:VI_32 2 "register_operand")))]
|
||||
"TARGET_SSE2"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<insn><mode>3"
|
||||
(define_insn "<insn><mode>3"
|
||||
[(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
|
||||
(plusminus:VI_32
|
||||
(match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
|
||||
(match_operand:VI_32 2 "register_operand" "x,Yw")))]
|
||||
"TARGET_SSE2
|
||||
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
|
||||
vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
|
||||
|
|
@ -1441,8 +1426,7 @@
|
|||
(sat_plusminus:VI_32
|
||||
(match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
|
||||
(match_operand:VI_32 2 "register_operand" "x,Yw")))]
|
||||
"TARGET_SSE2
|
||||
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
|
||||
vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
|
||||
|
|
@ -1461,8 +1445,7 @@
|
|||
[(set (match_operand:V4HI 0 "register_operand")
|
||||
(mult:V4HI (match_operand:V4HI 1 "register_operand")
|
||||
(match_operand:V4HI 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_insn "*mmx_mulv4hi3"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
|
||||
|
|
@ -1479,19 +1462,11 @@
|
|||
(set_attr "type" "mmxmul,ssemul,ssemul")
|
||||
(set_attr "mode" "DI,TI,TI")])
|
||||
|
||||
(define_expand "mulv2hi3"
|
||||
[(set (match_operand:V2HI 0 "register_operand")
|
||||
(mult:V2HI (match_operand:V2HI 1 "register_operand")
|
||||
(match_operand:V2HI 2 "register_operand")))]
|
||||
"TARGET_SSE2"
|
||||
"ix86_fixup_binary_operands_no_copy (MULT, V2HImode, operands);")
|
||||
|
||||
(define_insn "*mulv2hi3"
|
||||
(define_insn "mulv2hi3"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
|
||||
(mult:V2HI (match_operand:V2HI 1 "register_operand" "%0,Yw")
|
||||
(match_operand:V2HI 2 "register_operand" "x,Yw")))]
|
||||
"TARGET_SSE2
|
||||
&& ix86_binary_operator_ok (MULT, V2HImode, operands)"
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
pmullw\t{%2, %0|%0, %2}
|
||||
vpmullw\t{%2, %1, %0|%0, %1, %2}"
|
||||
|
|
@ -1579,10 +1554,9 @@
|
|||
(any_extend:V4SI
|
||||
(match_operand:V4HI 2 "register_operand")))
|
||||
(const_int 16))))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_insn "*<s>mulv2hi3_highpart"
|
||||
(define_insn "<s>mulv2hi3_highpart"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
|
||||
(truncate:V2HI
|
||||
(lshiftrt:V2SI
|
||||
|
|
@ -1592,8 +1566,7 @@
|
|||
(any_extend:V2SI
|
||||
(match_operand:V2HI 2 "register_operand" "x,Yw")))
|
||||
(const_int 16))))]
|
||||
"TARGET_SSE2
|
||||
&& ix86_binary_operator_ok (MULT, V2HImode, operands)"
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
pmulh<u>w\t{%2, %0|%0, %2}
|
||||
vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
|
||||
|
|
@ -1601,19 +1574,6 @@
|
|||
(set_attr "type" "ssemul")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_expand "<s>mulv2hi3_highpart"
|
||||
[(set (match_operand:V2HI 0 "register_operand")
|
||||
(truncate:V2HI
|
||||
(lshiftrt:V2SI
|
||||
(mult:V2SI
|
||||
(any_extend:V2SI
|
||||
(match_operand:V2HI 1 "register_operand"))
|
||||
(any_extend:V2SI
|
||||
(match_operand:V2HI 2 "register_operand")))
|
||||
(const_int 16))))]
|
||||
"TARGET_SSE2"
|
||||
"ix86_fixup_binary_operands_no_copy (MULT, V2HImode, operands);")
|
||||
|
||||
(define_expand "mmx_pmaddwd"
|
||||
[(set (match_operand:V2SI 0 "register_operand")
|
||||
(plus:V2SI
|
||||
|
|
@ -1744,13 +1704,12 @@
|
|||
;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
(define_insn "*mmx_<code><mode>3"
|
||||
(define_insn "<code><mode>3"
|
||||
[(set (match_operand:MMXMODE14 0 "register_operand" "=Yr,*x,Yv")
|
||||
(smaxmin:MMXMODE14
|
||||
(match_operand:MMXMODE14 1 "register_operand" "%0,0,Yv")
|
||||
(match_operand:MMXMODE14 2 "register_operand" "Yr,*x,Yv")))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSE4_1
|
||||
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
|
||||
"@
|
||||
p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
|
||||
p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
|
||||
|
|
@ -1787,24 +1746,19 @@
|
|||
(set_attr "type" "mmxadd,sseiadd,sseiadd")
|
||||
(set_attr "mode" "DI,TI,TI")])
|
||||
|
||||
(define_mode_iterator SMAXMIN_MMXMODEI
|
||||
[(V8QI "TARGET_SSE4_1") V4HI (V2SI "TARGET_SSE4_1")])
|
||||
(define_expand "<code>v4hi3"
|
||||
[(set (match_operand:V4HI 0 "register_operand")
|
||||
(smaxmin:V4HI
|
||||
(match_operand:V4HI 1 "register_operand")
|
||||
(match_operand:V4HI 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_expand "<code><mode>3"
|
||||
[(set (match_operand:SMAXMIN_MMXMODEI 0 "register_operand")
|
||||
(smaxmin:SMAXMIN_MMXMODEI
|
||||
(match_operand:SMAXMIN_MMXMODEI 1 "register_operand")
|
||||
(match_operand:SMAXMIN_MMXMODEI 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<code>v4qi3"
|
||||
(define_insn "<code>v4qi3"
|
||||
[(set (match_operand:V4QI 0 "register_operand" "=Yr,*x,Yv")
|
||||
(smaxmin:V4QI
|
||||
(match_operand:V4QI 1 "register_operand" "%0,0,Yv")
|
||||
(match_operand:V4QI 2 "register_operand" "Yr,*x,Yv")))]
|
||||
"TARGET_SSE4_1
|
||||
&& ix86_binary_operator_ok (<CODE>, V4QImode, operands)"
|
||||
"TARGET_SSE4_1"
|
||||
"@
|
||||
p<maxmin_int>b\t{%2, %0|%0, %2}
|
||||
p<maxmin_int>b\t{%2, %0|%0, %2}
|
||||
|
|
@ -1815,13 +1769,12 @@
|
|||
(set_attr "prefix" "orig,orig,vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "*<code>v2hi3"
|
||||
(define_insn "<code>v2hi3"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
|
||||
(smaxmin:V2HI
|
||||
(match_operand:V2HI 1 "register_operand" "%0,Yw")
|
||||
(match_operand:V2HI 2 "register_operand" "x,Yw")))]
|
||||
"TARGET_SSE2
|
||||
&& ix86_binary_operator_ok (<CODE>, V2HImode, operands)"
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
p<maxmin_int>w\t{%2, %0|%0, %2}
|
||||
vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
|
||||
|
|
@ -1829,23 +1782,12 @@
|
|||
(set_attr "type" "sseiadd")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_mode_iterator SMAXMIN_VI_32 [(V4QI "TARGET_SSE4_1") V2HI])
|
||||
|
||||
(define_expand "<code><mode>3"
|
||||
[(set (match_operand:SMAXMIN_VI_32 0 "register_operand")
|
||||
(smaxmin:SMAXMIN_VI_32
|
||||
(match_operand:SMAXMIN_VI_32 1 "register_operand")
|
||||
(match_operand:SMAXMIN_VI_32 2 "register_operand")))]
|
||||
"TARGET_SSE2"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
|
||||
|
||||
(define_insn "*mmx_<code><mode>3"
|
||||
(define_insn "<code><mode>3"
|
||||
[(set (match_operand:MMXMODE24 0 "register_operand" "=Yr,*x,Yv")
|
||||
(umaxmin:MMXMODE24
|
||||
(match_operand:MMXMODE24 1 "register_operand" "%0,0,Yv")
|
||||
(match_operand:MMXMODE24 2 "register_operand" "Yr,*x,Yv")))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSE4_1
|
||||
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
|
||||
"@
|
||||
p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
|
||||
p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
|
||||
|
|
@ -1882,24 +1824,19 @@
|
|||
(set_attr "type" "mmxadd,sseiadd,sseiadd")
|
||||
(set_attr "mode" "DI,TI,TI")])
|
||||
|
||||
(define_mode_iterator UMAXMIN_MMXMODEI
|
||||
[V8QI (V4HI "TARGET_SSE4_1") (V2SI "TARGET_SSE4_1")])
|
||||
(define_expand "<code>v8qi3"
|
||||
[(set (match_operand:V8QI 0 "register_operand")
|
||||
(umaxmin:V8QI
|
||||
(match_operand:V8QI 1 "register_operand")
|
||||
(match_operand:V8QI 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_expand "<code><mode>3"
|
||||
[(set (match_operand:UMAXMIN_MMXMODEI 0 "register_operand")
|
||||
(umaxmin:UMAXMIN_MMXMODEI
|
||||
(match_operand:UMAXMIN_MMXMODEI 1 "register_operand")
|
||||
(match_operand:UMAXMIN_MMXMODEI 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<code>v4qi3"
|
||||
(define_insn "<code>v4qi3"
|
||||
[(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
|
||||
(umaxmin:V4QI
|
||||
(match_operand:V4QI 1 "register_operand" "%0,Yw")
|
||||
(match_operand:V4QI 2 "register_operand" "x,Yw")))]
|
||||
"TARGET_SSE2
|
||||
&& ix86_binary_operator_ok (<CODE>, V4QImode, operands)"
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
p<maxmin_int>b\t{%2, %0|%0, %2}
|
||||
vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
|
||||
|
|
@ -1907,13 +1844,12 @@
|
|||
(set_attr "type" "sseiadd")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "*<code>v2hi3"
|
||||
(define_insn "<code>v2hi3"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,Yv")
|
||||
(umaxmin:V2HI
|
||||
(match_operand:V2HI 1 "register_operand" "%0,0,Yv")
|
||||
(match_operand:V2HI 2 "register_operand" "Yr,*x,Yv")))]
|
||||
"TARGET_SSE4_1
|
||||
&& ix86_binary_operator_ok (<CODE>, V2HImode, operands)"
|
||||
"TARGET_SSE4_1"
|
||||
"@
|
||||
p<maxmin_int>w\t{%2, %0|%0, %2}
|
||||
p<maxmin_int>w\t{%2, %0|%0, %2}
|
||||
|
|
@ -1924,16 +1860,6 @@
|
|||
(set_attr "prefix" "orig,orig,vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_mode_iterator UMAXMIN_VI_32 [V4QI (V2HI "TARGET_SSE4_1")])
|
||||
|
||||
(define_expand "<code><mode>3"
|
||||
[(set (match_operand:UMAXMIN_VI_32 0 "register_operand")
|
||||
(umaxmin:UMAXMIN_VI_32
|
||||
(match_operand:UMAXMIN_VI_32 1 "register_operand")
|
||||
(match_operand:UMAXMIN_VI_32 2 "register_operand")))]
|
||||
"TARGET_SSE2"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
|
||||
|
||||
(define_insn "ssse3_abs<mode>2"
|
||||
[(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yv")
|
||||
(abs:MMXMODEI
|
||||
|
|
@ -1953,7 +1879,7 @@
|
|||
[(set (match_operand:MMXMODEI 0 "register_operand")
|
||||
(abs:MMXMODEI
|
||||
(match_operand:MMXMODEI 1 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSSE3")
|
||||
"TARGET_SSSE3 && TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_insn "abs<mode>2"
|
||||
[(set (match_operand:VI_32 0 "register_operand" "=Yv")
|
||||
|
|
@ -2025,7 +1951,7 @@
|
|||
(match_operand:DI 2 "nonmemory_operand")))]
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_insn "*<insn>v2hi3"
|
||||
(define_insn "<insn>v2hi3"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
|
||||
(any_shift:V2HI
|
||||
(match_operand:V2HI 1 "register_operand" "0,Yw")
|
||||
|
|
@ -2042,13 +1968,6 @@
|
|||
(const_string "0")))
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_expand "<insn>v2hi3"
|
||||
[(set (match_operand:V2HI 0 "register_operand")
|
||||
(any_shift:V2HI
|
||||
(match_operand:V2HI 1 "register_operand")
|
||||
(match_operand:DI 2 "nonmemory_operand")))]
|
||||
"TARGET_SSE2")
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Parallel integral comparisons
|
||||
|
|
@ -2084,8 +2003,7 @@
|
|||
(eq:VI_32
|
||||
(match_operand:VI_32 1 "register_operand" "%0,x")
|
||||
(match_operand:VI_32 2 "register_operand" "x,x")))]
|
||||
"TARGET_SSE2
|
||||
&& ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
|
||||
vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
|
||||
|
|
@ -2441,8 +2359,7 @@
|
|||
(any_logic:MMXMODEI
|
||||
(match_operand:MMXMODEI 1 "register_operand")
|
||||
(match_operand:MMXMODEI 2 "register_operand")))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
"TARGET_MMX_WITH_SSE")
|
||||
|
||||
(define_insn "*mmx_<code><mode>3"
|
||||
[(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
|
||||
|
|
@ -2461,21 +2378,12 @@
|
|||
(set_attr "type" "mmxadd,sselog,sselog,sselog")
|
||||
(set_attr "mode" "DI,TI,TI,TI")])
|
||||
|
||||
(define_expand "<code><mode>3"
|
||||
[(set (match_operand:VI_32 0 "register_operand")
|
||||
(any_logic:VI_32
|
||||
(match_operand:VI_32 1 "register_operand")
|
||||
(match_operand:VI_32 2 "register_operand")))]
|
||||
"TARGET_SSE2"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<code><mode>3"
|
||||
(define_insn "<code><mode>3"
|
||||
[(set (match_operand:VI_32 0 "register_operand" "=x,x,v")
|
||||
(any_logic:VI_32
|
||||
(match_operand:VI_32 1 "register_operand" "%0,x,v")
|
||||
(match_operand:VI_32 2 "register_operand" "x,x,v")))]
|
||||
"TARGET_SSE2
|
||||
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
p<logic>\t{%2, %0|%0, %2}
|
||||
vp<logic>\t{%2, %1, %0|%0, %1, %2}
|
||||
|
|
@ -2672,7 +2580,7 @@
|
|||
(match_operand:SI 2 "nonimmediate_operand" "rm,rm"))
|
||||
(match_operand:V2SI 1 "register_operand" "0,Yv")
|
||||
(match_operand:SI 3 "const_int_operand")))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSE4_1
|
||||
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
|
||||
&& ((unsigned) exact_log2 (INTVAL (operands[3]))
|
||||
< GET_MODE_NUNITS (V2SImode))"
|
||||
{
|
||||
|
|
@ -2752,7 +2660,7 @@
|
|||
(match_operand:QI 2 "nonimmediate_operand" "rm,rm"))
|
||||
(match_operand:V8QI 1 "register_operand" "0,YW")
|
||||
(match_operand:SI 3 "const_int_operand")))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSE4_1
|
||||
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
|
||||
&& ((unsigned) exact_log2 (INTVAL (operands[3]))
|
||||
< GET_MODE_NUNITS (V8QImode))"
|
||||
{
|
||||
|
|
@ -2822,7 +2730,7 @@
|
|||
(vec_select:QI
|
||||
(match_operand:V8QI 1 "register_operand" "YW,YW")
|
||||
(parallel [(match_operand:SI 2 "const_0_to_7_operand" "n,n")])))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
|
||||
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
|
||||
"@
|
||||
%vpextrb\t{%2, %1, %k0|%k0, %1, %2}
|
||||
%vpextrb\t{%2, %1, %0|%0, %1, %2}"
|
||||
|
|
@ -2839,7 +2747,7 @@
|
|||
(vec_select:QI
|
||||
(match_operand:V8QI 1 "register_operand" "YW")
|
||||
(parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
|
||||
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
|
||||
"%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
|
||||
[(set_attr "type" "sselog1")
|
||||
(set_attr "prefix_data16" "1")
|
||||
|
|
@ -3321,10 +3229,7 @@
|
|||
(match_dup 3))
|
||||
(const_int 1))))]
|
||||
"TARGET_MMX_WITH_SSE"
|
||||
{
|
||||
operands[3] = CONST1_RTX(<mmxdoublemode>mode);
|
||||
ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
|
||||
})
|
||||
"operands[3] = CONST1_RTX(<mmxdoublemode>mode);")
|
||||
|
||||
(define_insn "uavgv4qi3_ceil"
|
||||
[(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
|
||||
|
|
|
|||
|
|
@ -1999,8 +1999,7 @@
|
|||
[(set (match_operand:VF2 0 "register_operand")
|
||||
(div:VF2 (match_operand:VF2 1 "register_operand")
|
||||
(match_operand:VF2 2 "vector_operand")))]
|
||||
"TARGET_SSE2"
|
||||
"ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);")
|
||||
"TARGET_SSE2")
|
||||
|
||||
(define_expand "div<mode>3"
|
||||
[(set (match_operand:VF1 0 "register_operand")
|
||||
|
|
@ -2008,8 +2007,6 @@
|
|||
(match_operand:VF1 2 "vector_operand")))]
|
||||
"TARGET_SSE"
|
||||
{
|
||||
ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);
|
||||
|
||||
if (TARGET_SSE_MATH
|
||||
&& TARGET_RECIP_VEC_DIV
|
||||
&& !optimize_insn_for_size_p ()
|
||||
|
|
@ -12801,7 +12798,7 @@
|
|||
{
|
||||
if (TARGET_AVX512F
|
||||
&& (<MODE>mode == V8DImode || TARGET_AVX512VL))
|
||||
ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
|
||||
;
|
||||
else
|
||||
{
|
||||
enum rtx_code code;
|
||||
|
|
@ -17186,10 +17183,7 @@
|
|||
(match_dup 3))
|
||||
(const_int 1))))]
|
||||
"TARGET_MMX_WITH_SSE && TARGET_SSSE3"
|
||||
{
|
||||
operands[3] = CONST1_RTX(V4HImode);
|
||||
ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);
|
||||
})
|
||||
"operands[3] = CONST1_RTX(V4HImode);")
|
||||
|
||||
(define_expand "ssse3_pmulhrswv4hi3"
|
||||
[(set (match_operand:V4HI 0 "register_operand")
|
||||
|
|
@ -17254,10 +17248,7 @@
|
|||
(match_dup 3))
|
||||
(const_int 1))))]
|
||||
"TARGET_SSSE3"
|
||||
{
|
||||
operands[3] = CONST1_RTX(V2HImode);
|
||||
ix86_fixup_binary_operands_no_copy (MULT, V2HImode, operands);
|
||||
})
|
||||
"operands[3] = CONST1_RTX(V2HImode);")
|
||||
|
||||
(define_insn "*smulhrsv2hi3"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=x,Yv")
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue