Initial Lunar Lake, Arrow Lake and Arrow Lake S Support

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Lunar Lake, Arrow Lake and Arrow Lake S. * common/config/i386/i386-common.cc: (processor_name): Add arrowlake. (processor_alias_table): Add arrow lake, arrow lake s and lunar lake. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add INTEL_COREI7_ARROWLAKE and INTEL_COREI7_ARROWLAKE_S. * config.gcc: Add -march=arrowlake and -march=arrowlake-s. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle arrowlake-s. * config/i386/i386-c.cc (ix86_target_macros_internal): Add arrowlake. * config/i386/i386-options.cc (m_ARROWLAKE): New. (processor_cost_table): Add arrowlake. * config/i386/i386.h (enum processor_type): Add PROCESSOR_ARROWLAKE. * config/i386/x86-tune.def: Add m_ARROWLAKE. * doc/extend.texi: Add arrowlake and arrowlake-s. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Add arrowlake and arrowlake-s. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-07-17 10:53:36 +08:00 · 2023-07-17 10:53:36 +08:00 · a5088dc3f5
commit a5088dc3f5
parent 85c50b4a50
13 changed files with 136 additions and 41 deletions
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@ -586,6 +586,24 @@ get_intel_cpu (struct __processor_model *cpu_model,
      CHECK___builtin_cpu_is ("grandridge");
      cpu_model->__cpu_type = INTEL_GRANDRIDGE;
      break;
+    case 0xc5:
+      /* Arrow Lake.  */
+      cpu = "arrowlake";
+      CHECK___builtin_cpu_is ("corei7");
+      CHECK___builtin_cpu_is ("arrowlake");
+      cpu_model->__cpu_type = INTEL_COREI7;
+      cpu_model->__cpu_subtype = INTEL_COREI7_ARROWLAKE;
+      break;
+    case 0xc6:
+      /* Arrow Lake S.  */
+    case 0xbd:
+      /* Lunar Lake.  */
+      cpu = "arrowlake-s";
+      CHECK___builtin_cpu_is ("corei7");
+      CHECK___builtin_cpu_is ("arrowlake-s");
+      cpu_model->__cpu_type = INTEL_COREI7;
+      cpu_model->__cpu_subtype = INTEL_COREI7_ARROWLAKE_S;
+      break;
    case 0x17:
    case 0x1d:
      /* Penryn.  */
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@ -2044,6 +2044,7 @@ const char *const processor_names[] =
  "alderlake",
  "rocketlake",
  "graniterapids",
+  "arrowlake",
  "intel",
  "lujiazui",
  "geode",
@ -2169,6 +2170,12 @@ const pta processor_alias_table[] =
    M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX512F},
  {"graniterapids-d", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS_D,
    M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D), P_PROC_AVX512F},
+  {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE,
+    M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2},
+  {"arrowlake-s", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE_S,
+    M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
+  {"lunarlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE_S,
+    M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
    M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@ -99,6 +99,8 @@ enum processor_subtypes
  AMDFAM19H_ZNVER4,
  INTEL_COREI7_GRANITERAPIDS,
  INTEL_COREI7_GRANITERAPIDS_D,
+  INTEL_COREI7_ARROWLAKE,
+  INTEL_COREI7_ARROWLAKE_S,
  CPU_SUBTYPE_MAX
 };

--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@ -683,7 +683,8 @@ silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \
 skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \
 sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \
 nano-x2 eden-x4 nano-x4 lujiazui x86-64 x86-64-v2 x86-64-v3 x86-64-v4 \
-sierraforest graniterapids graniterapids-d grandridge native"
+sierraforest graniterapids graniterapids-d grandridge arrowlake arrowlake-s \
+native"

 # Additional x86 processors supported by --with-cpu=.  Each processor
 # MUST be separated by exactly one space.
--- a/gcc/config/i386/driver-i386.cc
+++ b/gcc/config/i386/driver-i386.cc
@ -591,8 +591,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	      /* This is unknown family 0x6 CPU.  */
 	      if (has_feature (FEATURE_AVX))
 		{
+		  /* Assume Arrow Lake S.  */
+		  if (has_feature (FEATURE_SM3))
+		    cpu = "arrowlake-s";
 		  /* Assume Grand Ridge.  */
-		  if (has_feature (FEATURE_RAOINT))
+		  else if (has_feature (FEATURE_RAOINT))
 		    cpu = "grandridge";
 		  /* Assume Granite Rapids D.  */
 		  else if (has_feature (FEATURE_AMX_COMPLEX))
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@ -266,6 +266,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
      def_or_undef (parse_in, "__rocketlake");
      def_or_undef (parse_in, "__rocketlake__");
      break;
+    case PROCESSOR_ARROWLAKE:
+      def_or_undef (parse_in, "__arrowlake");
+      def_or_undef (parse_in, "__arrowlake__");
+      break;
    /* use PROCESSOR_max to not set/unset the arch macro.  */
    case PROCESSOR_max:
      break;
@ -447,6 +451,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
    case PROCESSOR_GRANITERAPIDS:
      def_or_undef (parse_in, "__tune_graniterapids__");
      break;
+    case PROCESSOR_ARROWLAKE:
+      def_or_undef (parse_in, "__tune_arrowlake__");
+      break;
    case PROCESSOR_INTEL:
    case PROCESSOR_GENERIC:
      break;
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@ -139,6 +139,7 @@ along with GCC; see the file COPYING3.  If not see
 #define m_TREMONT (HOST_WIDE_INT_1U<<PROCESSOR_TREMONT)
 #define m_SIERRAFOREST (HOST_WIDE_INT_1U<<PROCESSOR_SIERRAFOREST)
 #define m_GRANDRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_GRANDRIDGE)
+#define m_ARROWLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ARROWLAKE)
 #define m_CORE_ATOM (m_SIERRAFOREST | m_GRANDRIDGE)
 #define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL)

@ -771,6 +772,7 @@ static const struct processor_costs *processor_cost_table[] =
  &alderlake_cost,
  &icelake_cost,
  &icelake_cost,
+  &alderlake_cost,
  &intel_cost,
  &lujiazui_cost,
  &geode_cost,
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@ -2233,6 +2233,7 @@ enum processor_type
  PROCESSOR_ALDERLAKE,
  PROCESSOR_ROCKETLAKE,
  PROCESSOR_GRANITERAPIDS,
+  PROCESSOR_ARROWLAKE,
  PROCESSOR_INTEL,
  PROCESSOR_LUJIAZUI,
  PROCESSOR_GEODE,
@ -2347,6 +2348,9 @@ constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16
 constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS
  | PTA_AMX_COMPLEX;
 constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT;
+constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_SIERRAFOREST;
+constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16
+  | PTA_SHA512 | PTA_SM3 | PTA_SM4;
 constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
 constexpr wide_int_bitmask PTA_ZNVER1 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@ -42,8 +42,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
          m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
 	  | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
-	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM
-	  | m_GENERIC)
+	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
   on modern chips.  Prefer stores affecting whole integer register
@ -53,7 +53,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
          m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2
 	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
 	  | m_KNL | m_KNM | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT
-	  | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)
+	  | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
   destinations to be 128bit to allow register renaming on 128bit SSE units,
@ -64,7 +64,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
 	  | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE
-	  | m_CORE_ATOM | m_GENERIC)
+	  | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
   partial write to the destination in scalar SSE conversion from FP
@ -72,22 +72,22 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY,
 	  "sse_partial_reg_fp_converts_dependency",
 	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
-	  | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_CORE_ATOM
-	  | m_GENERIC)
+	  | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
   write to the destination in scalar SSE conversion from integer to FP.  */
 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY,
 	  "sse_partial_reg_converts_dependency",
 	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
-	  | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_CORE_ATOM
-	  | m_GENERIC)
+	  | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before
   several insns to break false dependency on the dest register for GLC
   micro-architecture.  */
 DEF_TUNE (X86_TUNE_DEST_FALSE_DEP_FOR_GLC,
-	  "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_ALDERLAKE
+	  "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_ALDERLAKE | m_ARROWLAKE
 	  | m_CORE_ATOM)

 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
@ -114,14 +114,16 @@ DEF_TUNE (X86_TUNE_MOVX, "movx",
          m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
 	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL
 	  | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
-	  | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)
+	  | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
   full sized loads.  */
 DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
          m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
 	  | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE
-	  | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)
+	  | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
   conditional jump instruction for 32 bit TARGET.  */
@ -177,14 +179,15 @@ DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
 /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits.  */
 DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
 	  m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
-	  | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)
+	  | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
   Some chips, like 486 and Pentium works faster with separate load
   and push instructions.  */
 DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
          m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
-	  | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)
+	  | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
   over esp subtraction.  */
@ -254,8 +257,8 @@ DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
 DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
          ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
 	    | m_BONNELL | m_SILVERMONT | m_INTEL |  m_KNL | m_KNM | m_GOLDMONT
-	    | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM
-	    | m_LUJIAZUI | m_GENERIC))
+	    | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
+	    | m_CORE_ATOM | m_LUJIAZUI | m_GENERIC))

 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
   for DFmode copies */
@ -263,7 +266,7 @@ DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
          ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
 	    | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
 	    | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
-	    | m_CORE_ATOM | m_GENERIC))
+	    | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC))

 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
   will impact LEA instruction selection. */
@ -301,8 +304,8 @@ DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
   move/set sequences of bytes with known size.  */
 DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
 	  "prefer_known_rep_movsb_stosb",
-	  m_SKYLAKE | m_ALDERLAKE | m_CORE_ATOM | m_TREMONT | m_CORE_AVX512
-	  | m_LUJIAZUI)
+	  m_SKYLAKE | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM
+	  | m_TREMONT | m_CORE_AVX512 | m_LUJIAZUI)

 /* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
   compact prologues and epilogues by issuing a misaligned moves.  This
@ -312,14 +315,15 @@ DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
 DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
 	  "misaligned_move_string_pro_epilogues",
 	  m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT
-	  | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)
+	  | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_USE_SAHF: Controls use of SAHF.  */
 DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
 	  | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
 	  | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS
-	  | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)
+	  | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM
+	  | m_GENERIC)

 /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions.  */
 DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
@ -330,7 +334,8 @@ DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
 DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
          m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
 	  | m_LAKEMONT | m_AMD_MULTIPLE | m_LUJIAZUI | m_GOLDMONT
-	  | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)
+	  | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
   for bit-manipulation instructions.  */
@ -349,13 +354,13 @@ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
   if-converted sequence to one.  */
 DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
 	  m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
-	  | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_LUJIAZUI
-	  | m_GENERIC)
+	  | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_LUJIAZUI | m_GENERIC)

 /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence.  */
 DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
 	 m_CORE_ALL | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE
-	 | m_CORE_ATOM | m_GENERIC)
+	 | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
   generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
@ -380,7 +385,8 @@ DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
          ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
 	    | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE
 	    | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
-	    | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC))
+	    | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM
+	    | m_GENERIC))

 /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp.  */
 DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI)
@ -389,8 +395,8 @@ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI)
 DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
 	  | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_LUJIAZUI
-	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM
-	  | m_GENERIC)
+	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_GENERIC)

 /*****************************************************************************/
 /* SSE instruction selection tuning                                          */
@ -406,15 +412,16 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
 	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
 	  | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
-	  | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI
-	  | m_GENERIC)
+	  | m_ARROWLAKE | m_CORE_ATOM | m_AMDFAM10 | m_BDVER
+	  | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GENERIC)

 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
   instead of a sequence loading registers by parts.  */
 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
 	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
 	  | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
-	  | m_CORE_ATOM | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC)
+	  | m_ARROWLAKE | m_CORE_ATOM | m_BDVER | m_ZNVER
+	  | m_LUJIAZUI | m_GENERIC)

 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
   precision 128bit instructions instead of double where possible.   */
@ -424,13 +431,14 @@ DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optim
 /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
 DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
 	  m_AMD_MULTIPLE | m_LUJIAZUI | m_CORE_ALL | m_TREMONT | m_ALDERLAKE
-	  | m_CORE_ATOM | m_GENERIC)
+	  | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
   xorps/xorpd and other variants.  */
 DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
 	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
-	  | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)
+	  | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
+	  | m_CORE_ATOM | m_GENERIC)

 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
   to SSE registers.  If disabled, the moves will be done by storing
@ -477,12 +485,13 @@ DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
 /* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes.  */
 DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
 	  m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
-	  | m_CORE_ATOM | m_INTEL)
+	  | m_ARROWLAKE | m_CORE_ATOM | m_INTEL)

 /* X86_TUNE_USE_GATHER_2PARTS: Use gather instructions for vectors with 2
   elements.  */
 DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts",
-	  ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC))
+	  ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE
+	    | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC))

 /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
   elements.  */
@ -492,7 +501,8 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
 /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4
   elements.  */
 DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts",
-	  ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC))
+	  ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE
+	    | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC))

 /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
   elements.  */
@ -502,7 +512,8 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
 /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more
   elements.  */
 DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather",
-	  ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER4 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC))
+	  ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER4 | m_ALDERLAKE | m_ARROWLAKE
+	    | m_CORE_ATOM | m_GENERIC))

 /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
   elements.  */
@ -516,7 +527,8 @@ DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER1 | m_ZNVER2
 /* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
   smaller FMA chain.  */
 DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains", m_ZNVER2 | m_ZNVER3
-	  | m_ALDERLAKE | m_SAPPHIRERAPIDS | m_CORE_ATOM)
+	  | m_ALDERLAKE | m_ARROWLAKE | m_SAPPHIRERAPIDS
+	  | m_CORE_ATOM)

 /* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or
   smaller FMA chain.  */
@ -560,12 +572,14 @@ DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4)
 /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
   AVX instructions.  */
 DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
-	  m_ALDERLAKE | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3)
+	  m_ALDERLAKE | m_ARROWLAKE | m_CORE_AVX2 | m_ZNVER1
+	  | m_ZNVER2 | m_ZNVER3)

 /* X86_TUNE_AVX256_STORE_BY_PIECES: Optimize store_by_pieces with 256-bit
   AVX instructions.  */
 DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces",
-	  m_ALDERLAKE | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3)
+	  m_ALDERLAKE | m_ARROWLAKE | m_CORE_AVX2 | m_ZNVER1
+	  | m_ZNVER2 | m_ZNVER3)

 /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
   AVX instructions.  */
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@ -22269,6 +22269,12 @@ Intel Atom Sierra Forest CPU.
@item grandridge
 Intel Atom Grand Ridge CPU.

+@item arrowlake
+Intel Core i7 Arrow Lake CPU.
+
+@item arrowlake-s
+Intel Core i7 Arrow Lake S CPU.
+
@item knl
 Intel Knights Landing CPU.

--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@ -32578,6 +32578,23 @@ PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
 AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD, UINTR and RAOINT
 instruction set support.

+@item arrowlake
+Intel Arrow Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
+XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
+MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
+PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
+AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support.
+
+@item arrowlake-s
+Intel Arrow Lake S CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
+XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
+MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
+PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
+AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3
+and SM4 instruction set support.
+
@item knl
 Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
 SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,
--- a/gcc/testsuite/g++.target/i386/mv16.C
+++ b/gcc/testsuite/g++.target/i386/mv16.C
@ -108,6 +108,14 @@ int __attribute__ ((target("arch=graniterapids-d"))) foo () {
  return 28;
 }

+int __attribute__ ((target("arch=arrowlake"))) foo () {
+  return 29;
+}
+
+int __attribute__ ((target("arch=arrowlake-s"))) foo () {
+  return 30;
+}
+
 int main ()
 {
  int val = foo ();
@ -154,6 +162,10 @@ int main ()
    assert (val == 27);
  else if (__builtin_cpu_is ("graniterapids-d"))
    assert (val == 28);
+  else if (__builtin_cpu_is ("arrowlake"))
+    assert (val == 29);
+  else if (__builtin_cpu_is ("arrowlake-s"))
+    assert (val == 30);
  else
    assert (val == 0);

--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@ -212,6 +212,8 @@ extern void test_arch_alderlake (void)          __attribute__((__target__("arch=
 extern void test_arch_rocketlake (void)         __attribute__((__target__("arch=rocketlake")));
 extern void test_arch_graniterapids (void)	__attribute__((__target__("arch=graniterapids")));
 extern void test_arch_graniterapids_d (void)	__attribute__((__target__("arch=graniterapids-d")));
+extern void test_arch_arrowlake (void)		__attribute__((__target__("arch=arrowlake")));
+extern void test_arch_arrowlake_s (void)	__attribute__((__target__("arch=arrowlake-s")));
 extern void test_arch_lujiazui (void)			__attribute__((__target__("arch=lujiazui")));
 extern void test_arch_k8 (void)			__attribute__((__target__("arch=k8")));
 extern void test_arch_k8_sse3 (void)		__attribute__((__target__("arch=k8-sse3")));