[NDS32] Implement more C ISR extension.
gcc/ * config.gcc (nds32*): Add nds32_isr.h and nds32_init.inc in extra_headers. * common/config/nds32/nds32-common.c (nds32_handle_option): Handle OPT_misr_secure_ case. * config/nds32/nds32-isr.c: Implementation of backward compatibility. * config/nds32/nds32-protos.h (nds32_isr_function_critical_p): New. * config/nds32/nds32.c (nds32_attribute_table): Add critical and secure attribute. * config/nds32/nds32.h (nds32_isr_nested_type): Add NDS32_CRITICAL. (nds32_isr_info): New field security_level. (TARGET_ISR_VECTOR_SIZE_4_BYTE): New macro. * config/nds32/nds32.md (return_internal): Consider critical attribute. * config/nds32/nds32.opt (misr-secure): New option. * config/nds32/nds32_init.inc: New file. * config/nds32/nds32_isr.h: New file. libgcc/ * config/nds32/t-nds32-isr: Rearrange object dependency. * config/nds32/initfini.c: Add dwarf2 unwinding support. * config/nds32/isr-library/adj_intr_lvl.inc: Consider new extensions and registers usage. * config/nds32/isr-library/excp_isr.S: Ditto. * config/nds32/isr-library/intr_isr.S: Ditto. * config/nds32/isr-library/reset.S: Ditto. * config/nds32/isr-library/restore_all.inc: Ditto. * config/nds32/isr-library/restore_mac_regs.inc: Ditto. * config/nds32/isr-library/restore_partial.inc: Ditto. * config/nds32/isr-library/restore_usr_regs.inc: Ditto. * config/nds32/isr-library/save_all.inc: Ditto. * config/nds32/isr-library/save_mac_regs.inc: Ditto. * config/nds32/isr-library/save_partial.inc: Ditto. * config/nds32/isr-library/save_usr_regs.inc: Ditto. * config/nds32/isr-library/vec_vid*.S: Consider 4-byte vector size. From-SVN: r263493
This commit is contained in:
Chung-Ju Wu
Chung-Ju Wu
parent
39d2c7ed9f
commit
a493174524
99 changed files with 2021 additions and 275 deletions
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@ -1,3 +1,21 @@
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2018-08-12 Chung-Ju Wu <jasonwucj@gmail.com>
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* config.gcc (nds32*): Add nds32_isr.h and nds32_init.inc in
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extra_headers.
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* common/config/nds32/nds32-common.c (nds32_handle_option): Handle
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OPT_misr_secure_ case.
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* config/nds32/nds32-isr.c: Implementation of backward compatibility.
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* config/nds32/nds32-protos.h (nds32_isr_function_critical_p): New.
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* config/nds32/nds32.c (nds32_attribute_table): Add critical and
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secure attribute.
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* config/nds32/nds32.h (nds32_isr_nested_type): Add NDS32_CRITICAL.
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(nds32_isr_info): New field security_level.
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(TARGET_ISR_VECTOR_SIZE_4_BYTE): New macro.
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* config/nds32/nds32.md (return_internal): Consider critical attribute.
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* config/nds32/nds32.opt (misr-secure): New option.
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* config/nds32/nds32_init.inc: New file.
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* config/nds32/nds32_isr.h: New file.
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2018-08-11 John David Anglin <danglin@gcc.gnu.org>
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* config/pa/pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum.
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@ -53,6 +53,16 @@ nds32_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
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return true;
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case OPT_misr_secure_:
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/* Check the valid security level: 0 1 2 3. */
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if (value < 0 || value > 3)
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{
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error_at (loc, "for the option -misr-secure=X, the valid X "
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"must be: 0, 1, 2, or 3");
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return false;
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}
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return true;
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case OPT_mcache_block_size_:
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/* Check valid value: 4 8 16 32 64 128 256 512. */
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if (exact_log2 (value) < 2 || exact_log2 (value) > 9)
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@ -447,7 +447,7 @@ mips*-*-*)
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;;
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nds32*)
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cpu_type=nds32
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extra_headers="nds32_intrinsic.h"
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extra_headers="nds32_intrinsic.h nds32_isr.h nds32_init.inc"
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case ${target} in
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nds32*-*-linux*)
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extra_options="${extra_options} nds32/nds32-linux.opt"
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@ -43,7 +43,260 @@
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We use an array to record essential information for each vector. */
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static struct nds32_isr_info nds32_isr_vectors[NDS32_N_ISR_VECTORS];
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/* ------------------------------------------------------------------------ */
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/* ------------------------------------------------------------- */
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/* FIXME:
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FOR BACKWARD COMPATIBILITY, we need to support following patterns:
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__attribute__((interrupt("XXX;YYY;id=ZZZ")))
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__attribute__((exception("XXX;YYY;id=ZZZ")))
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__attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ")))
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We provide several functions to parse the strings. */
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static void
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nds32_interrupt_attribute_parse_string (const char *original_str,
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const char *func_name,
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unsigned int s_level)
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{
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char target_str[100];
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enum nds32_isr_save_reg save_reg;
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enum nds32_isr_nested_type nested_type;
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char *save_all_regs_str, *save_caller_regs_str;
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char *nested_str, *not_nested_str, *ready_nested_str, *critical_str;
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char *id_str, *value_str;
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/* Copy original string into a character array so that
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the string APIs can handle it. */
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strcpy (target_str, original_str);
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/* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL
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'save_caller_regs' : NDS32_PARTIAL_SAVE */
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save_all_regs_str = strstr (target_str, "save_all_regs");
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save_caller_regs_str = strstr (target_str, "save_caller_regs");
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/* Note that if no argument is found,
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use NDS32_PARTIAL_SAVE by default. */
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if (save_all_regs_str)
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save_reg = NDS32_SAVE_ALL;
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else if (save_caller_regs_str)
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save_reg = NDS32_PARTIAL_SAVE;
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else
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save_reg = NDS32_PARTIAL_SAVE;
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/* 2. Detect 'nested' : NDS32_NESTED
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'not_nested' : NDS32_NOT_NESTED
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'ready_nested' : NDS32_NESTED_READY
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'critical' : NDS32_CRITICAL */
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nested_str = strstr (target_str, "nested");
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not_nested_str = strstr (target_str, "not_nested");
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ready_nested_str = strstr (target_str, "ready_nested");
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critical_str = strstr (target_str, "critical");
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/* Note that if no argument is found,
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use NDS32_NOT_NESTED by default.
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Also, since 'not_nested' and 'ready_nested' both contains
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'nested' string, we check 'nested' with lowest priority. */
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if (not_nested_str)
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nested_type = NDS32_NOT_NESTED;
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else if (ready_nested_str)
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nested_type = NDS32_NESTED_READY;
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else if (nested_str)
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nested_type = NDS32_NESTED;
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else if (critical_str)
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nested_type = NDS32_CRITICAL;
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else
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nested_type = NDS32_NOT_NESTED;
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/* 3. Traverse each id value and set corresponding information. */
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id_str = strstr (target_str, "id=");
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/* If user forgets to assign 'id', issue an error message. */
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if (id_str == NULL)
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error ("require id argument in the string");
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/* Extract the value_str first. */
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id_str = strtok (id_str, "=");
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value_str = strtok (NULL, ";");
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/* Pick up the first id value token. */
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value_str = strtok (value_str, ",");
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while (value_str != NULL)
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{
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int i;
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i = atoi (value_str);
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/* For interrupt(0..63), the actual vector number is (9..72). */
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i = i + 9;
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if (i < 9 || i > 72)
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error ("invalid id value for interrupt attribute");
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/* Setup nds32_isr_vectors[] array. */
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nds32_isr_vectors[i].category = NDS32_ISR_INTERRUPT;
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strcpy (nds32_isr_vectors[i].func_name, func_name);
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nds32_isr_vectors[i].save_reg = save_reg;
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nds32_isr_vectors[i].nested_type = nested_type;
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nds32_isr_vectors[i].security_level = s_level;
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/* Fetch next token. */
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value_str = strtok (NULL, ",");
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}
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return;
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}
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static void
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nds32_exception_attribute_parse_string (const char *original_str,
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const char *func_name,
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unsigned int s_level)
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{
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char target_str[100];
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enum nds32_isr_save_reg save_reg;
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enum nds32_isr_nested_type nested_type;
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char *save_all_regs_str, *save_caller_regs_str;
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char *nested_str, *not_nested_str, *ready_nested_str, *critical_str;
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char *id_str, *value_str;
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/* Copy original string into a character array so that
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the string APIs can handle it. */
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strcpy (target_str, original_str);
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/* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL
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'save_caller_regs' : NDS32_PARTIAL_SAVE */
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save_all_regs_str = strstr (target_str, "save_all_regs");
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save_caller_regs_str = strstr (target_str, "save_caller_regs");
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/* Note that if no argument is found,
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use NDS32_PARTIAL_SAVE by default. */
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if (save_all_regs_str)
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save_reg = NDS32_SAVE_ALL;
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else if (save_caller_regs_str)
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save_reg = NDS32_PARTIAL_SAVE;
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else
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save_reg = NDS32_PARTIAL_SAVE;
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/* 2. Detect 'nested' : NDS32_NESTED
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'not_nested' : NDS32_NOT_NESTED
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'ready_nested' : NDS32_NESTED_READY
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'critical' : NDS32_CRITICAL */
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nested_str = strstr (target_str, "nested");
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not_nested_str = strstr (target_str, "not_nested");
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ready_nested_str = strstr (target_str, "ready_nested");
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critical_str = strstr (target_str, "critical");
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/* Note that if no argument is found,
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use NDS32_NOT_NESTED by default.
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Also, since 'not_nested' and 'ready_nested' both contains
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'nested' string, we check 'nested' with lowest priority. */
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if (not_nested_str)
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nested_type = NDS32_NOT_NESTED;
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else if (ready_nested_str)
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nested_type = NDS32_NESTED_READY;
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else if (nested_str)
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nested_type = NDS32_NESTED;
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else if (critical_str)
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nested_type = NDS32_CRITICAL;
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else
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nested_type = NDS32_NOT_NESTED;
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/* 3. Traverse each id value and set corresponding information. */
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id_str = strstr (target_str, "id=");
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/* If user forgets to assign 'id', issue an error message. */
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if (id_str == NULL)
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error ("require id argument in the string");
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/* Extract the value_str first. */
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id_str = strtok (id_str, "=");
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value_str = strtok (NULL, ";");
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/* Pick up the first id value token. */
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value_str = strtok (value_str, ",");
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while (value_str != NULL)
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{
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int i;
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i = atoi (value_str);
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/* For exception(1..8), the actual vector number is (1..8). */
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if (i < 1 || i > 8)
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error ("invalid id value for exception attribute");
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/* Setup nds32_isr_vectors[] array. */
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nds32_isr_vectors[i].category = NDS32_ISR_EXCEPTION;
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strcpy (nds32_isr_vectors[i].func_name, func_name);
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nds32_isr_vectors[i].save_reg = save_reg;
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nds32_isr_vectors[i].nested_type = nested_type;
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nds32_isr_vectors[i].security_level = s_level;
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/* Fetch next token. */
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value_str = strtok (NULL, ",");
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}
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return;
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}
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static void
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nds32_reset_attribute_parse_string (const char *original_str,
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const char *func_name)
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{
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char target_str[100];
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char *vectors_str, *nmi_str, *warm_str, *value_str;
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/* Deal with reset attribute. Its vector number is always 0. */
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nds32_isr_vectors[0].category = NDS32_ISR_RESET;
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/* 1. Parse 'vectors=XXXX'. */
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/* Copy original string into a character array so that
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the string APIs can handle it. */
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strcpy (target_str, original_str);
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vectors_str = strstr (target_str, "vectors=");
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/* The total vectors = interrupt + exception numbers + reset.
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There are 8 exception and 1 reset in nds32 architecture.
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If user forgets to assign 'vectors', user default 16 interrupts. */
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if (vectors_str != NULL)
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{
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/* Extract the value_str. */
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vectors_str = strtok (vectors_str, "=");
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value_str = strtok (NULL, ";");
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nds32_isr_vectors[0].total_n_vectors = atoi (value_str) + 8 + 1;
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}
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else
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nds32_isr_vectors[0].total_n_vectors = 16 + 8 + 1;
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strcpy (nds32_isr_vectors[0].func_name, func_name);
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/* 2. Parse 'nmi_func=YYYY'. */
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/* Copy original string into a character array so that
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the string APIs can handle it. */
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strcpy (target_str, original_str);
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nmi_str = strstr (target_str, "nmi_func=");
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if (nmi_str != NULL)
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{
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/* Extract the value_str. */
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nmi_str = strtok (nmi_str, "=");
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value_str = strtok (NULL, ";");
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strcpy (nds32_isr_vectors[0].nmi_name, value_str);
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}
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/* 3. Parse 'warm_func=ZZZZ'. */
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/* Copy original string into a character array so that
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the string APIs can handle it. */
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strcpy (target_str, original_str);
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warm_str = strstr (target_str, "warm_func=");
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if (warm_str != NULL)
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{
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/* Extract the value_str. */
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warm_str = strtok (warm_str, "=");
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value_str = strtok (NULL, ";");
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strcpy (nds32_isr_vectors[0].warm_name, value_str);
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}
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return;
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}
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/* ------------------------------------------------------------- */
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/* A helper function to emit section head template. */
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static void
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@ -79,6 +332,15 @@ nds32_emit_isr_jmptbl_section (int vector_id)
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char section_name[100];
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char symbol_name[100];
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/* A critical isr does not need jump table section because
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its behavior is not performed by two-level handler. */
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if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL)
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{
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fprintf (asm_out_file, "\t! The vector %02d is a critical isr !\n",
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vector_id);
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return;
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}
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/* Prepare jmptbl section and symbol name. */
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snprintf (section_name, sizeof (section_name),
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".nds32_jmptbl.%02d", vector_id);
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@ -99,7 +361,6 @@ nds32_emit_isr_vector_section (int vector_id)
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const char *c_str = "CATEGORY";
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const char *sr_str = "SR";
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const char *nt_str = "NT";
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const char *vs_str = "VS";
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char first_level_handler_name[100];
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char section_name[100];
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char symbol_name[100];
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@ -147,30 +408,47 @@ nds32_emit_isr_vector_section (int vector_id)
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case NDS32_NESTED_READY:
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nt_str = "nr";
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break;
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case NDS32_CRITICAL:
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/* The critical isr is not performed by two-level handler. */
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nt_str = "";
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break;
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}
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/* Currently we have 4-byte or 16-byte size for each vector.
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If it is 4-byte, the first level handler name has suffix string "_4b". */
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vs_str = (nds32_isr_vector_size == 4) ? "_4b" : "";
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/* Now we can create first level handler name. */
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snprintf (first_level_handler_name, sizeof (first_level_handler_name),
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"_nds32_%s_%s_%s%s", c_str, sr_str, nt_str, vs_str);
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if (nds32_isr_vectors[vector_id].security_level == 0)
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{
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/* For security level 0, use normal first level handler name. */
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snprintf (first_level_handler_name, sizeof (first_level_handler_name),
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"_nds32_%s_%s_%s", c_str, sr_str, nt_str);
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}
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else
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{
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/* For security level 1-3, use corresponding spl_1, spl_2, or spl_3. */
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snprintf (first_level_handler_name, sizeof (first_level_handler_name),
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"_nds32_spl_%d", nds32_isr_vectors[vector_id].security_level);
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}
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/* Prepare vector section and symbol name. */
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snprintf (section_name, sizeof (section_name),
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".nds32_vector.%02d", vector_id);
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snprintf (symbol_name, sizeof (symbol_name),
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"_nds32_vector_%02d%s", vector_id, vs_str);
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"_nds32_vector_%02d", vector_id);
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/* Everything is ready. We can start emit vector section content. */
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nds32_emit_section_head_template (section_name, symbol_name,
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floor_log2 (nds32_isr_vector_size), false);
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/* According to the vector size, the instructions in the
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vector section may be different. */
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if (nds32_isr_vector_size == 4)
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/* First we check if it is a critical isr.
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If so, jump to user handler directly; otherwise, the instructions
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in the vector section may be different according to the vector size. */
|
||||
if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL)
|
||||
{
|
||||
/* This block is for critical isr. Jump to user handler directly. */
|
||||
fprintf (asm_out_file, "\tj\t%s ! jump to user handler directly\n",
|
||||
nds32_isr_vectors[vector_id].func_name);
|
||||
}
|
||||
else if (nds32_isr_vector_size == 4)
|
||||
{
|
||||
/* This block is for 4-byte vector size.
|
||||
Hardware $VID support is necessary and only one instruction
|
||||
|
|
@ -239,13 +517,11 @@ nds32_emit_isr_reset_content (void)
|
|||
{
|
||||
unsigned int i;
|
||||
unsigned int total_n_vectors;
|
||||
const char *vs_str;
|
||||
char reset_handler_name[100];
|
||||
char section_name[100];
|
||||
char symbol_name[100];
|
||||
|
||||
total_n_vectors = nds32_isr_vectors[0].total_n_vectors;
|
||||
vs_str = (nds32_isr_vector_size == 4) ? "_4b" : "";
|
||||
|
||||
fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - BEGIN !\n");
|
||||
|
||||
|
|
@ -261,7 +537,7 @@ nds32_emit_isr_reset_content (void)
|
|||
/* Emit vector references. */
|
||||
fprintf (asm_out_file, "\t ! references to vector section entries\n");
|
||||
for (i = 0; i < total_n_vectors; i++)
|
||||
fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d%s\n", i, vs_str);
|
||||
fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d\n", i);
|
||||
|
||||
/* Emit jmptbl_00 section. */
|
||||
snprintf (section_name, sizeof (section_name), ".nds32_jmptbl.00");
|
||||
|
|
@ -275,9 +551,9 @@ nds32_emit_isr_reset_content (void)
|
|||
|
||||
/* Emit vector_00 section. */
|
||||
snprintf (section_name, sizeof (section_name), ".nds32_vector.00");
|
||||
snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00%s", vs_str);
|
||||
snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00");
|
||||
snprintf (reset_handler_name, sizeof (reset_handler_name),
|
||||
"_nds32_reset%s", vs_str);
|
||||
"_nds32_reset");
|
||||
|
||||
fprintf (asm_out_file, "\t! ....................................\n");
|
||||
nds32_emit_section_head_template (section_name, symbol_name,
|
||||
|
|
@ -323,12 +599,12 @@ void
|
|||
nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs)
|
||||
{
|
||||
int save_all_p, partial_save_p;
|
||||
int nested_p, not_nested_p, nested_ready_p;
|
||||
int nested_p, not_nested_p, nested_ready_p, critical_p;
|
||||
int intr_p, excp_p, reset_p;
|
||||
|
||||
/* Initialize variables. */
|
||||
save_all_p = partial_save_p = 0;
|
||||
nested_p = not_nested_p = nested_ready_p = 0;
|
||||
nested_p = not_nested_p = nested_ready_p = critical_p = 0;
|
||||
intr_p = excp_p = reset_p = 0;
|
||||
|
||||
/* We must check at MOST one attribute to set save-reg. */
|
||||
|
|
@ -347,8 +623,10 @@ nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs)
|
|||
not_nested_p = 1;
|
||||
if (lookup_attribute ("nested_ready", func_attrs))
|
||||
nested_ready_p = 1;
|
||||
if (lookup_attribute ("critical", func_attrs))
|
||||
critical_p = 1;
|
||||
|
||||
if ((nested_p + not_nested_p + nested_ready_p) > 1)
|
||||
if ((nested_p + not_nested_p + nested_ready_p + critical_p) > 1)
|
||||
error ("multiple nested types attributes to function %qD", func_decl);
|
||||
|
||||
/* We must check at MOST one attribute to
|
||||
|
|
@ -362,6 +640,17 @@ nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs)
|
|||
|
||||
if ((intr_p + excp_p + reset_p) > 1)
|
||||
error ("multiple interrupt attributes to function %qD", func_decl);
|
||||
|
||||
/* Do not allow isr attributes under linux toolchain. */
|
||||
if (TARGET_LINUX_ABI && intr_p)
|
||||
error ("cannot use interrupt attributes to function %qD "
|
||||
"under linux toolchain", func_decl);
|
||||
if (TARGET_LINUX_ABI && excp_p)
|
||||
error ("cannot use exception attributes to function %qD "
|
||||
"under linux toolchain", func_decl);
|
||||
if (TARGET_LINUX_ABI && reset_p)
|
||||
error ("cannot use reset attributes to function %qD "
|
||||
"under linux toolchain", func_decl);
|
||||
}
|
||||
|
||||
/* Function to construct isr vectors information array.
|
||||
|
|
@ -373,15 +662,21 @@ nds32_construct_isr_vectors_information (tree func_attrs,
|
|||
const char *func_name)
|
||||
{
|
||||
tree save_all, partial_save;
|
||||
tree nested, not_nested, nested_ready;
|
||||
tree nested, not_nested, nested_ready, critical;
|
||||
tree intr, excp, reset;
|
||||
|
||||
tree secure;
|
||||
tree security_level_list;
|
||||
tree security_level;
|
||||
unsigned int s_level;
|
||||
|
||||
save_all = lookup_attribute ("save_all", func_attrs);
|
||||
partial_save = lookup_attribute ("partial_save", func_attrs);
|
||||
|
||||
nested = lookup_attribute ("nested", func_attrs);
|
||||
not_nested = lookup_attribute ("not_nested", func_attrs);
|
||||
nested_ready = lookup_attribute ("nested_ready", func_attrs);
|
||||
critical = lookup_attribute ("critical", func_attrs);
|
||||
|
||||
intr = lookup_attribute ("interrupt", func_attrs);
|
||||
excp = lookup_attribute ("exception", func_attrs);
|
||||
|
|
@ -391,6 +686,63 @@ nds32_construct_isr_vectors_information (tree func_attrs,
|
|||
if (!intr && !excp && !reset)
|
||||
return;
|
||||
|
||||
/* At first, we need to retrieve security level. */
|
||||
secure = lookup_attribute ("secure", func_attrs);
|
||||
if (secure != NULL)
|
||||
{
|
||||
security_level_list = TREE_VALUE (secure);
|
||||
security_level = TREE_VALUE (security_level_list);
|
||||
s_level = TREE_INT_CST_LOW (security_level);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If there is no secure attribute, the security level is set by
|
||||
nds32_isr_secure_level, which is controlled by -misr-secure=X option.
|
||||
By default nds32_isr_secure_level should be 0. */
|
||||
s_level = nds32_isr_secure_level;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------- */
|
||||
/* FIXME:
|
||||
FOR BACKWARD COMPATIBILITY, we need to support following patterns:
|
||||
|
||||
__attribute__((interrupt("XXX;YYY;id=ZZZ")))
|
||||
__attribute__((exception("XXX;YYY;id=ZZZ")))
|
||||
__attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ")))
|
||||
|
||||
If interrupt/exception/reset appears and its argument is a
|
||||
STRING_CST, we will parse string with some auxiliary functions
|
||||
which set necessary isr information in the nds32_isr_vectors[] array.
|
||||
After that, we can return immediately to avoid new-syntax isr
|
||||
information construction. */
|
||||
if (intr != NULL_TREE
|
||||
&& TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST)
|
||||
{
|
||||
tree string_arg = TREE_VALUE (TREE_VALUE (intr));
|
||||
nds32_interrupt_attribute_parse_string (TREE_STRING_POINTER (string_arg),
|
||||
func_name,
|
||||
s_level);
|
||||
return;
|
||||
}
|
||||
if (excp != NULL_TREE
|
||||
&& TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST)
|
||||
{
|
||||
tree string_arg = TREE_VALUE (TREE_VALUE (excp));
|
||||
nds32_exception_attribute_parse_string (TREE_STRING_POINTER (string_arg),
|
||||
func_name,
|
||||
s_level);
|
||||
return;
|
||||
}
|
||||
if (reset != NULL_TREE
|
||||
&& TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST)
|
||||
{
|
||||
tree string_arg = TREE_VALUE (TREE_VALUE (reset));
|
||||
nds32_reset_attribute_parse_string (TREE_STRING_POINTER (string_arg),
|
||||
func_name);
|
||||
return;
|
||||
}
|
||||
/* ------------------------------------------------------------- */
|
||||
|
||||
/* If we are here, either we have interrupt/exception,
|
||||
or reset attribute. */
|
||||
if (intr || excp)
|
||||
|
|
@ -417,6 +769,9 @@ nds32_construct_isr_vectors_information (tree func_attrs,
|
|||
/* Add vector_number_offset to get actual vector number. */
|
||||
vector_id = TREE_INT_CST_LOW (id) + vector_number_offset;
|
||||
|
||||
/* Set security level. */
|
||||
nds32_isr_vectors[vector_id].security_level = s_level;
|
||||
|
||||
/* Enable corresponding vector and set function name. */
|
||||
nds32_isr_vectors[vector_id].category = (intr)
|
||||
? (NDS32_ISR_INTERRUPT)
|
||||
|
|
@ -436,6 +791,8 @@ nds32_construct_isr_vectors_information (tree func_attrs,
|
|||
nds32_isr_vectors[vector_id].nested_type = NDS32_NOT_NESTED;
|
||||
else if (nested_ready)
|
||||
nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED_READY;
|
||||
else if (critical)
|
||||
nds32_isr_vectors[vector_id].nested_type = NDS32_CRITICAL;
|
||||
|
||||
/* Advance to next id. */
|
||||
id_list = TREE_CHAIN (id_list);
|
||||
|
|
@ -492,7 +849,6 @@ nds32_construct_isr_vectors_information (tree func_attrs,
|
|||
}
|
||||
}
|
||||
|
||||
/* A helper function to handle isr stuff at the beginning of asm file. */
|
||||
void
|
||||
nds32_asm_file_start_for_isr (void)
|
||||
{
|
||||
|
|
@ -505,15 +861,14 @@ nds32_asm_file_start_for_isr (void)
|
|||
strcpy (nds32_isr_vectors[i].func_name, "");
|
||||
nds32_isr_vectors[i].save_reg = NDS32_PARTIAL_SAVE;
|
||||
nds32_isr_vectors[i].nested_type = NDS32_NOT_NESTED;
|
||||
nds32_isr_vectors[i].security_level = 0;
|
||||
nds32_isr_vectors[i].total_n_vectors = 0;
|
||||
strcpy (nds32_isr_vectors[i].nmi_name, "");
|
||||
strcpy (nds32_isr_vectors[i].warm_name, "");
|
||||
}
|
||||
}
|
||||
|
||||
/* A helper function to handle isr stuff at the end of asm file. */
|
||||
void
|
||||
nds32_asm_file_end_for_isr (void)
|
||||
void nds32_asm_file_end_for_isr (void)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -547,6 +902,8 @@ nds32_asm_file_end_for_isr (void)
|
|||
/* Found one vector which is interupt or exception.
|
||||
Output its jmptbl and vector section content. */
|
||||
fprintf (asm_out_file, "\t! interrupt/exception vector %02d\n", i);
|
||||
fprintf (asm_out_file, "\t! security level: %d\n",
|
||||
nds32_isr_vectors[i].security_level);
|
||||
fprintf (asm_out_file, "\t! ------------------------------------\n");
|
||||
nds32_emit_isr_jmptbl_section (i);
|
||||
fprintf (asm_out_file, "\t! ....................................\n");
|
||||
|
|
@ -580,4 +937,65 @@ nds32_isr_function_p (tree func)
|
|||
|| (t_reset != NULL_TREE));
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------ */
|
||||
/* Return true if FUNC is a isr function with critical attribute. */
|
||||
bool
|
||||
nds32_isr_function_critical_p (tree func)
|
||||
{
|
||||
tree t_intr;
|
||||
tree t_excp;
|
||||
tree t_critical;
|
||||
|
||||
tree attrs;
|
||||
|
||||
if (TREE_CODE (func) != FUNCTION_DECL)
|
||||
abort ();
|
||||
|
||||
attrs = DECL_ATTRIBUTES (func);
|
||||
|
||||
t_intr = lookup_attribute ("interrupt", attrs);
|
||||
t_excp = lookup_attribute ("exception", attrs);
|
||||
|
||||
t_critical = lookup_attribute ("critical", attrs);
|
||||
|
||||
/* If both interrupt and exception attribute does not appear,
|
||||
we can return false immediately. */
|
||||
if ((t_intr == NULL_TREE) && (t_excp == NULL_TREE))
|
||||
return false;
|
||||
|
||||
/* Here we can guarantee either interrupt or ecxception attribute
|
||||
does exist, so further check critical attribute.
|
||||
If it also appears, we can return true. */
|
||||
if (t_critical != NULL_TREE)
|
||||
return true;
|
||||
|
||||
/* ------------------------------------------------------------- */
|
||||
/* FIXME:
|
||||
FOR BACKWARD COMPATIBILITY, we need to handle string type.
|
||||
If the string 'critical' appears in the interrupt/exception
|
||||
string argument, we can return true. */
|
||||
if (t_intr != NULL_TREE || t_excp != NULL_TREE)
|
||||
{
|
||||
char target_str[100];
|
||||
char *critical_str;
|
||||
tree t_check;
|
||||
tree string_arg;
|
||||
|
||||
t_check = t_intr ? t_intr : t_excp;
|
||||
if (TREE_CODE (TREE_VALUE (TREE_VALUE (t_check))) == STRING_CST)
|
||||
{
|
||||
string_arg = TREE_VALUE (TREE_VALUE (t_check));
|
||||
strcpy (target_str, TREE_STRING_POINTER (string_arg));
|
||||
critical_str = strstr (target_str, "critical");
|
||||
|
||||
/* Found 'critical' string, so return true. */
|
||||
if (critical_str)
|
||||
return true;
|
||||
}
|
||||
}
|
||||
/* ------------------------------------------------------------- */
|
||||
|
||||
/* Other cases, this isr function is not critical type. */
|
||||
return false;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -307,6 +307,7 @@ extern void nds32_construct_isr_vectors_information (tree, const char *);
|
|||
extern void nds32_asm_file_start_for_isr (void);
|
||||
extern void nds32_asm_file_end_for_isr (void);
|
||||
extern bool nds32_isr_function_p (tree);
|
||||
extern bool nds32_isr_function_critical_p (tree);
|
||||
|
||||
/* Auxiliary functions for cost calculation. */
|
||||
|
||||
|
|
|
|||
|
|
@ -305,6 +305,7 @@ static const struct attribute_spec nds32_attribute_table[] =
|
|||
{ "nested", 0, 0, false, false, false, false, NULL, NULL },
|
||||
{ "not_nested", 0, 0, false, false, false, false, NULL, NULL },
|
||||
{ "nested_ready", 0, 0, false, false, false, false, NULL, NULL },
|
||||
{ "critical", 0, 0, false, false, false, false, NULL, NULL },
|
||||
|
||||
/* The attributes describing isr register save scheme. */
|
||||
{ "save_all", 0, 0, false, false, false, false, NULL, NULL },
|
||||
|
|
@ -314,6 +315,9 @@ static const struct attribute_spec nds32_attribute_table[] =
|
|||
{ "nmi", 1, 1, false, false, false, false, NULL, NULL },
|
||||
{ "warm", 1, 1, false, false, false, false, NULL, NULL },
|
||||
|
||||
/* The attributes describing isr security level. */
|
||||
{ "secure", 1, 1, false, false, false, false, NULL, NULL },
|
||||
|
||||
/* The attribute telling no prologue/epilogue. */
|
||||
{ "naked", 0, 0, false, false, false, false, NULL, NULL },
|
||||
|
||||
|
|
@ -518,7 +522,7 @@ nds32_compute_stack_frame (void)
|
|||
}
|
||||
|
||||
/* Check if this function can omit prologue/epilogue code fragment.
|
||||
If there is 'no_prologue'/'naked' attribute in this function,
|
||||
If there is 'no_prologue'/'naked'/'secure' attribute in this function,
|
||||
we can set 'naked_p' flag to indicate that
|
||||
we do not have to generate prologue/epilogue.
|
||||
Or, if all the following conditions succeed,
|
||||
|
|
@ -533,6 +537,7 @@ nds32_compute_stack_frame (void)
|
|||
we do not need to adjust $sp. */
|
||||
if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl))
|
||||
|| lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
|
||||
|| lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl))
|
||||
|| (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM
|
||||
&& cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM
|
||||
&& cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM
|
||||
|
|
@ -2307,14 +2312,17 @@ nds32_function_ok_for_sibcall (tree decl,
|
|||
|
||||
/* 1. Do not apply sibling call if -mv3push is enabled,
|
||||
because pop25 instruction also represents return behavior.
|
||||
2. If this function is a variadic function, do not apply sibling call
|
||||
2. If this function is a isr function, do not apply sibling call
|
||||
because it may perform the behavior that user does not expect.
|
||||
3. If this function is a variadic function, do not apply sibling call
|
||||
because the stack layout may be a mess.
|
||||
3. We don't want to apply sibling call optimization for indirect
|
||||
4. We don't want to apply sibling call optimization for indirect
|
||||
sibcall because the pop behavior in epilogue may pollute the
|
||||
content of caller-saved regsiter when the register is used for
|
||||
indirect sibcall.
|
||||
4. In pic mode, it may use some registers for PLT call. */
|
||||
5. In pic mode, it may use some registers for PLT call. */
|
||||
return (!TARGET_V3PUSH
|
||||
&& !nds32_isr_function_p (current_function_decl)
|
||||
&& (cfun->machine->va_args_size == 0)
|
||||
&& decl
|
||||
&& !flag_pic);
|
||||
|
|
@ -3968,6 +3976,38 @@ nds32_insert_attributes (tree decl, tree *attributes)
|
|||
excp = lookup_attribute ("exception", func_attrs);
|
||||
reset = lookup_attribute ("reset", func_attrs);
|
||||
|
||||
/* The following code may use attribute arguments. If there is no
|
||||
argument from source code, it will cause segmentation fault.
|
||||
Therefore, return dircetly and report error message later. */
|
||||
if ((intr && TREE_VALUE (intr) == NULL)
|
||||
|| (excp && TREE_VALUE (excp) == NULL)
|
||||
|| (reset && TREE_VALUE (reset) == NULL))
|
||||
return;
|
||||
|
||||
/* ------------------------------------------------------------- */
|
||||
/* FIXME:
|
||||
FOR BACKWARD COMPATIBILITY, we need to support following patterns:
|
||||
|
||||
__attribute__((interrupt("XXX;YYY;id=ZZZ")))
|
||||
__attribute__((exception("XXX;YYY;id=ZZZ")))
|
||||
__attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ")))
|
||||
|
||||
If interrupt/exception/reset appears and its argument is a
|
||||
STRING_CST, we will use other functions to parse string in the
|
||||
nds32_construct_isr_vectors_information() and then set necessary
|
||||
isr information in the nds32_isr_vectors[] array. Here we can
|
||||
just return immediately to avoid new-syntax checking. */
|
||||
if (intr != NULL_TREE
|
||||
&& TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST)
|
||||
return;
|
||||
if (excp != NULL_TREE
|
||||
&& TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST)
|
||||
return;
|
||||
if (reset != NULL_TREE
|
||||
&& TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST)
|
||||
return;
|
||||
/* ------------------------------------------------------------- */
|
||||
|
||||
if (intr || excp)
|
||||
{
|
||||
/* Deal with interrupt/exception. */
|
||||
|
|
@ -4211,6 +4251,16 @@ nds32_cpu_cpp_builtins(struct cpp_reader *pfile)
|
|||
builtin_define ("__nds32__");
|
||||
builtin_define ("__NDS32__");
|
||||
|
||||
/* We need to provide builtin macro to describe the size of
|
||||
each vector for interrupt handler under elf toolchain. */
|
||||
if (!TARGET_LINUX_ABI)
|
||||
{
|
||||
if (TARGET_ISR_VECTOR_SIZE_4_BYTE)
|
||||
builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__");
|
||||
else
|
||||
builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__");
|
||||
}
|
||||
|
||||
if (TARGET_HARD_FLOAT)
|
||||
builtin_define ("__NDS32_ABI_2FP_PLUS__");
|
||||
else
|
||||
|
|
|
|||
|
|
@ -367,7 +367,8 @@ enum nds32_isr_nested_type
|
|||
{
|
||||
NDS32_NESTED,
|
||||
NDS32_NOT_NESTED,
|
||||
NDS32_NESTED_READY
|
||||
NDS32_NESTED_READY,
|
||||
NDS32_CRITICAL
|
||||
};
|
||||
|
||||
/* Define structure to record isr information.
|
||||
|
|
@ -395,6 +396,13 @@ struct nds32_isr_info
|
|||
unless user specifies attribute to change it. */
|
||||
enum nds32_isr_nested_type nested_type;
|
||||
|
||||
/* Secure isr level.
|
||||
Currently we have 0-3 security level.
|
||||
It should be set to 0 by default.
|
||||
For security processors, this is determined by secure
|
||||
attribute or compiler options. */
|
||||
unsigned int security_level;
|
||||
|
||||
/* Total vectors.
|
||||
The total vectors = interrupt + exception numbers + reset.
|
||||
It should be set to 0 by default.
|
||||
|
|
@ -849,8 +857,10 @@ enum nds32_builtins
|
|||
|
||||
/* ------------------------------------------------------------------------ */
|
||||
|
||||
#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
|
||||
#define TARGET_ISR_VECTOR_SIZE_4_BYTE \
|
||||
(nds32_isr_vector_size == 4)
|
||||
|
||||
#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
|
||||
#define TARGET_ISA_V3 \
|
||||
(nds32_arch_option == ARCH_V3 \
|
||||
|| nds32_arch_option == ARCH_V3J \
|
||||
|
|
|
|||
|
|
@ -1993,6 +1993,9 @@
|
|||
[(simple_return)]
|
||||
""
|
||||
{
|
||||
if (nds32_isr_function_critical_p (current_function_decl))
|
||||
return "iret";
|
||||
|
||||
if (TARGET_16_BIT)
|
||||
return "ret5";
|
||||
else
|
||||
|
|
@ -2001,9 +2004,11 @@
|
|||
[(set_attr "type" "branch")
|
||||
(set_attr "enabled" "yes")
|
||||
(set (attr "length")
|
||||
(if_then_else (match_test "TARGET_16_BIT")
|
||||
(const_int 2)
|
||||
(const_int 4)))])
|
||||
(if_then_else (match_test "nds32_isr_function_critical_p (current_function_decl)")
|
||||
(const_int 4)
|
||||
(if_then_else (match_test "TARGET_16_BIT")
|
||||
(const_int 2)
|
||||
(const_int 4))))])
|
||||
|
||||
|
||||
;; ----------------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -158,6 +158,10 @@ misr-vector-size=
|
|||
Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
|
||||
Specify the size of each interrupt vector, which must be 4 or 16.
|
||||
|
||||
misr-secure=
|
||||
Target RejectNegative Joined UInteger Var(nds32_isr_secure_level) Init(0)
|
||||
Specify the security level of c-isr for the whole file.
|
||||
|
||||
mcache-block-size=
|
||||
Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
|
||||
Specify the size of each cache block, which must be a power of 2 between 4 and 512.
|
||||
|
|
|
|||
43
gcc/config/nds32/nds32_init.inc
Normal file
43
gcc/config/nds32/nds32_init.inc
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* nds32_init.inc
|
||||
*
|
||||
* NDS32 architecture startup assembler header file
|
||||
*
|
||||
*/
|
||||
|
||||
.macro nds32_init
|
||||
|
||||
! Initialize GP for data access
|
||||
la $gp, _SDA_BASE_
|
||||
|
||||
#if defined(__NDS32_EXT_EX9__)
|
||||
! Check HW for EX9
|
||||
mfsr $r0, $MSC_CFG
|
||||
li $r1, (1 << 24)
|
||||
and $r2, $r0, $r1
|
||||
beqz $r2, 1f
|
||||
|
||||
! Initialize the table base of EX9 instruction
|
||||
la $r0, _ITB_BASE_
|
||||
mtusr $r0, $ITB
|
||||
1:
|
||||
#endif
|
||||
|
||||
#if defined(__NDS32_EXT_FPU_DP__) || defined(__NDS32_EXT_FPU_SP__)
|
||||
! Enable FPU
|
||||
mfsr $r0, $FUCOP_CTL
|
||||
ori $r0, $r0, #0x1
|
||||
mtsr $r0, $FUCOP_CTL
|
||||
dsb
|
||||
|
||||
! Enable denormalized flush-to-Zero mode
|
||||
fmfcsr $r0
|
||||
ori $r0,$r0,#0x1000
|
||||
fmtcsr $r0
|
||||
dsb
|
||||
#endif
|
||||
|
||||
! Initialize default stack pointer
|
||||
la $sp, _stack
|
||||
|
||||
.endm
|
||||
526
gcc/config/nds32/nds32_isr.h
Normal file
526
gcc/config/nds32/nds32_isr.h
Normal file
|
|
@ -0,0 +1,526 @@
|
|||
/* Intrinsic definitions of Andes NDS32 cpu for GNU compiler
|
||||
Copyright (C) 2012-2018 Free Software Foundation, Inc.
|
||||
Contributed by Andes Technology Corporation.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef _NDS32_ISR_H
|
||||
#define _NDS32_ISR_H
|
||||
|
||||
/* Attribute of a interrupt or exception handler:
|
||||
|
||||
NDS32_READY_NESTED: This handler is interruptible if user re-enable GIE bit.
|
||||
NDS32_NESTED : This handler is interruptible. This is not suitable
|
||||
exception handler.
|
||||
NDS32_NOT_NESTED : This handler is NOT interruptible. Users have to do
|
||||
some work if nested is wanted
|
||||
NDS32_CRITICAL : This handler is critical ISR, which means it is small
|
||||
and efficient. */
|
||||
#define NDS32_READY_NESTED 0
|
||||
#define NDS32_NESTED 1
|
||||
#define NDS32_NOT_NESTED 2
|
||||
#define NDS32_CRITICAL 3
|
||||
|
||||
/* Attribute of a interrupt or exception handler:
|
||||
|
||||
NDS32_SAVE_ALL_REGS : Save all registers in a table.
|
||||
NDS32_SAVE_PARTIAL_REGS: Save partial registers. */
|
||||
#define NDS32_SAVE_CALLER_REGS 0
|
||||
#define NDS32_SAVE_ALL_REGS 1
|
||||
|
||||
/* There are two version of Register table for interrupt and exception handler,
|
||||
one for 16-register CPU the other for 32-register CPU. These structures are
|
||||
used for context switching or system call handling. The address of this
|
||||
data can be get from the input argument of the handler functions.
|
||||
|
||||
For system call handling, r0 to r5 are used to pass arguments. If more
|
||||
arguments are used they are put into the stack and its starting address is
|
||||
in sp. Return value of system call can be put into r0 and r1 upon exit from
|
||||
system call handler. System call ID is in a system register and it can be
|
||||
fetched via intrinsic function. For more information please read ABI and
|
||||
other related documents.
|
||||
|
||||
For context switching, at least 2 values need to saved in kernel. One is
|
||||
IPC and the other is the stack address of current task. Use intrinsic
|
||||
function to get IPC and the input argument of the handler functions + 8 to
|
||||
get stack address of current task. To do context switching, you replace
|
||||
new_sp with the stack address of new task and replace IPC system register
|
||||
with IPC of new task, then, just return from handler. The context switching
|
||||
will happen. */
|
||||
|
||||
/* Register table for exception handler; 32-register version. */
|
||||
typedef struct
|
||||
{
|
||||
int r0;
|
||||
int r1;
|
||||
int r2;
|
||||
int r3;
|
||||
int r4;
|
||||
int r5;
|
||||
int r6;
|
||||
int r7;
|
||||
int r8;
|
||||
int r9;
|
||||
int r10;
|
||||
int r11;
|
||||
int r12;
|
||||
int r13;
|
||||
int r14;
|
||||
int r15;
|
||||
int r16;
|
||||
int r17;
|
||||
int r18;
|
||||
int r19;
|
||||
int r20;
|
||||
int r21;
|
||||
int r22;
|
||||
int r23;
|
||||
int r24;
|
||||
int r25;
|
||||
int r26;
|
||||
int r27;
|
||||
int fp;
|
||||
int gp;
|
||||
int lp;
|
||||
int sp;
|
||||
} NDS32_GPR32;
|
||||
|
||||
/* Register table for exception handler; 16-register version. */
|
||||
typedef struct
|
||||
{
|
||||
int r0;
|
||||
int r1;
|
||||
int r2;
|
||||
int r3;
|
||||
int r4;
|
||||
int r5;
|
||||
int r6;
|
||||
int r7;
|
||||
int r8;
|
||||
int r9;
|
||||
int r10;
|
||||
int r15;
|
||||
int fp;
|
||||
int gp;
|
||||
int lp;
|
||||
int sp;
|
||||
} NDS32_GPR16;
|
||||
|
||||
|
||||
/* Use NDS32_REG32_TAB or NDS32_REG16_TAB in your program to
|
||||
access register table. */
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
int reg_a[32] ;
|
||||
NDS32_GPR32 reg_s ;
|
||||
} u ;
|
||||
} NDS32_REG32_TAB;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
int reg_a[16] ;
|
||||
NDS32_GPR16 reg_s ;
|
||||
} u ;
|
||||
} NDS32_REG16_TAB;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int d0lo;
|
||||
int d0hi;
|
||||
int d1lo;
|
||||
int d1hi;
|
||||
} NDS32_DX_TAB;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
#ifdef __NDS32_EB__
|
||||
float fsr0;
|
||||
float fsr1;
|
||||
float fsr2;
|
||||
float fsr3;
|
||||
float fsr4;
|
||||
float fsr5;
|
||||
float fsr6;
|
||||
float fsr7;
|
||||
#else
|
||||
float fsr1;
|
||||
float fsr0;
|
||||
float fsr3;
|
||||
float fsr2;
|
||||
float fsr5;
|
||||
float fsr4;
|
||||
float fsr7;
|
||||
float fsr6;
|
||||
#endif
|
||||
} NDS32_FSR8;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
double dsr0;
|
||||
double dsr1;
|
||||
double dsr2;
|
||||
double dsr3;
|
||||
} NDS32_DSR4;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
#ifdef __NDS32_EB__
|
||||
float fsr0;
|
||||
float fsr1;
|
||||
float fsr2;
|
||||
float fsr3;
|
||||
float fsr4;
|
||||
float fsr5;
|
||||
float fsr6;
|
||||
float fsr7;
|
||||
float fsr8;
|
||||
float fsr9;
|
||||
float fsr10;
|
||||
float fsr11;
|
||||
float fsr12;
|
||||
float fsr13;
|
||||
float fsr14;
|
||||
float fsr15;
|
||||
#else
|
||||
float fsr1;
|
||||
float fsr0;
|
||||
float fsr3;
|
||||
float fsr2;
|
||||
float fsr5;
|
||||
float fsr4;
|
||||
float fsr7;
|
||||
float fsr6;
|
||||
float fsr9;
|
||||
float fsr8;
|
||||
float fsr11;
|
||||
float fsr10;
|
||||
float fsr13;
|
||||
float fsr12;
|
||||
float fsr15;
|
||||
float fsr14;
|
||||
#endif
|
||||
} NDS32_FSR16;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
double dsr0;
|
||||
double dsr1;
|
||||
double dsr2;
|
||||
double dsr3;
|
||||
double dsr4;
|
||||
double dsr5;
|
||||
double dsr6;
|
||||
double dsr7;
|
||||
} NDS32_DSR8;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
#ifdef __NDS32_EB__
|
||||
float fsr0;
|
||||
float fsr1;
|
||||
float fsr2;
|
||||
float fsr3;
|
||||
float fsr4;
|
||||
float fsr5;
|
||||
float fsr6;
|
||||
float fsr7;
|
||||
float fsr8;
|
||||
float fsr9;
|
||||
float fsr10;
|
||||
float fsr11;
|
||||
float fsr12;
|
||||
float fsr13;
|
||||
float fsr14;
|
||||
float fsr15;
|
||||
float fsr16;
|
||||
float fsr17;
|
||||
float fsr18;
|
||||
float fsr19;
|
||||
float fsr20;
|
||||
float fsr21;
|
||||
float fsr22;
|
||||
float fsr23;
|
||||
float fsr24;
|
||||
float fsr25;
|
||||
float fsr26;
|
||||
float fsr27;
|
||||
float fsr28;
|
||||
float fsr29;
|
||||
float fsr30;
|
||||
float fsr31;
|
||||
#else
|
||||
float fsr1;
|
||||
float fsr0;
|
||||
float fsr3;
|
||||
float fsr2;
|
||||
float fsr5;
|
||||
float fsr4;
|
||||
float fsr7;
|
||||
float fsr6;
|
||||
float fsr9;
|
||||
float fsr8;
|
||||
float fsr11;
|
||||
float fsr10;
|
||||
float fsr13;
|
||||
float fsr12;
|
||||
float fsr15;
|
||||
float fsr14;
|
||||
float fsr17;
|
||||
float fsr16;
|
||||
float fsr19;
|
||||
float fsr18;
|
||||
float fsr21;
|
||||
float fsr20;
|
||||
float fsr23;
|
||||
float fsr22;
|
||||
float fsr25;
|
||||
float fsr24;
|
||||
float fsr27;
|
||||
float fsr26;
|
||||
float fsr29;
|
||||
float fsr28;
|
||||
float fsr31;
|
||||
float fsr30;
|
||||
#endif
|
||||
} NDS32_FSR32;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
double dsr0;
|
||||
double dsr1;
|
||||
double dsr2;
|
||||
double dsr3;
|
||||
double dsr4;
|
||||
double dsr5;
|
||||
double dsr6;
|
||||
double dsr7;
|
||||
double dsr8;
|
||||
double dsr9;
|
||||
double dsr10;
|
||||
double dsr11;
|
||||
double dsr12;
|
||||
double dsr13;
|
||||
double dsr14;
|
||||
double dsr15;
|
||||
} NDS32_DSR16;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
double dsr0;
|
||||
double dsr1;
|
||||
double dsr2;
|
||||
double dsr3;
|
||||
double dsr4;
|
||||
double dsr5;
|
||||
double dsr6;
|
||||
double dsr7;
|
||||
double dsr8;
|
||||
double dsr9;
|
||||
double dsr10;
|
||||
double dsr11;
|
||||
double dsr12;
|
||||
double dsr13;
|
||||
double dsr14;
|
||||
double dsr15;
|
||||
double dsr16;
|
||||
double dsr17;
|
||||
double dsr18;
|
||||
double dsr19;
|
||||
double dsr20;
|
||||
double dsr21;
|
||||
double dsr22;
|
||||
double dsr23;
|
||||
double dsr24;
|
||||
double dsr25;
|
||||
double dsr26;
|
||||
double dsr27;
|
||||
double dsr28;
|
||||
double dsr29;
|
||||
double dsr30;
|
||||
double dsr31;
|
||||
} NDS32_DSR32;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
NDS32_FSR8 fsr_s ;
|
||||
NDS32_DSR4 dsr_s ;
|
||||
} u ;
|
||||
} NDS32_FPU8_TAB;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
NDS32_FSR16 fsr_s ;
|
||||
NDS32_DSR8 dsr_s ;
|
||||
} u ;
|
||||
} NDS32_FPU16_TAB;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
NDS32_FSR32 fsr_s ;
|
||||
NDS32_DSR16 dsr_s ;
|
||||
} u ;
|
||||
} NDS32_FPU32_TAB;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
NDS32_FSR32 fsr_s ;
|
||||
NDS32_DSR32 dsr_s ;
|
||||
} u ;
|
||||
} NDS32_FPU64_TAB;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int ipc;
|
||||
int ipsw;
|
||||
#if defined(NDS32_EXT_FPU_CONFIG_0)
|
||||
NDS32_FPU8_TAB fpr;
|
||||
#elif defined(NDS32_EXT_FPU_CONFIG_1)
|
||||
NDS32_FPU16_TAB fpr;
|
||||
#elif defined(NDS32_EXT_FPU_CONFIG_2)
|
||||
NDS32_FPU32_TAB fpr;
|
||||
#elif defined(NDS32_EXT_FPU_CONFIG_3)
|
||||
NDS32_FPU64_TAB fpr;
|
||||
#endif
|
||||
#if __NDS32_DX_REGS__
|
||||
NDS32_DX_TAB dxr;
|
||||
#endif
|
||||
#if __NDS32_EXT_IFC__
|
||||
int ifc_lp;
|
||||
int filler;
|
||||
#endif
|
||||
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
|
||||
NDS32_REG16_TAB gpr;
|
||||
#else
|
||||
NDS32_REG32_TAB gpr;
|
||||
#endif
|
||||
} NDS32_CONTEXT;
|
||||
|
||||
/* Predefined Vector Definition.
|
||||
|
||||
For IVIC Mode: 9 to 14 are for hardware interrupt
|
||||
and 15 is for software interrupt.
|
||||
For EVIC Mode: 9 to 72 are for hardware interrupt
|
||||
and software interrupt can be routed to any one of them.
|
||||
|
||||
You may want to define your hardware interrupts in the following way
|
||||
for easy maintainance.
|
||||
|
||||
IVIC mode:
|
||||
#define MY_HW_IVIC_TIMER NDS32_VECTOR_INTERRUPT_HW0 + 1
|
||||
#define MY_HW_IVIC_USB NDS32_VECTOR_INTERRUPT_HW0 + 3
|
||||
EVIC mode:
|
||||
#define MY_HW_EVIC_DMA NDS32_VECTOR_INTERRUPT_HW0 + 2
|
||||
#define MY_HW_EVIC_SWI NDS32_VECTOR_INTERRUPT_HW0 + 10 */
|
||||
#define NDS32_VECTOR_RESET 0
|
||||
#define NDS32_VECTOR_TLB_FILL 1
|
||||
#define NDS32_VECTOR_PTE_NOT_PRESENT 2
|
||||
#define NDS32_VECTOR_TLB_MISC 3
|
||||
#define NDS32_VECTOR_TLB_VLPT_MISS 4
|
||||
#define NDS32_VECTOR_MACHINE_ERROR 5
|
||||
#define NDS32_VECTOR_DEBUG_RELATED 6
|
||||
#define NDS32_VECTOR_GENERAL_EXCEPTION 7
|
||||
#define NDS32_VECTOR_SYSCALL 8
|
||||
#define NDS32_VECTOR_INTERRUPT_HW0 9
|
||||
#define NDS32_VECTOR_INTERRUPT_HW1 10
|
||||
#define NDS32_VECTOR_INTERRUPT_HW2 11
|
||||
#define NDS32_VECTOR_INTERRUPT_HW3 12
|
||||
#define NDS32_VECTOR_INTERRUPT_HW4 13
|
||||
#define NDS32_VECTOR_INTERRUPT_HW5 14
|
||||
#define NDS32_VECTOR_INTERRUPT_HW6 15
|
||||
#define NDS32_VECTOR_SWI 15 /* THIS IS FOR IVIC MODE ONLY */
|
||||
#define NDS32_VECTOR_INTERRUPT_HW7 16
|
||||
#define NDS32_VECTOR_INTERRUPT_HW8 17
|
||||
#define NDS32_VECTOR_INTERRUPT_HW9 18
|
||||
#define NDS32_VECTOR_INTERRUPT_HW10 19
|
||||
#define NDS32_VECTOR_INTERRUPT_HW11 20
|
||||
#define NDS32_VECTOR_INTERRUPT_HW12 21
|
||||
#define NDS32_VECTOR_INTERRUPT_HW13 22
|
||||
#define NDS32_VECTOR_INTERRUPT_HW14 23
|
||||
#define NDS32_VECTOR_INTERRUPT_HW15 24
|
||||
#define NDS32_VECTOR_INTERRUPT_HW16 25
|
||||
#define NDS32_VECTOR_INTERRUPT_HW17 26
|
||||
#define NDS32_VECTOR_INTERRUPT_HW18 27
|
||||
#define NDS32_VECTOR_INTERRUPT_HW19 28
|
||||
#define NDS32_VECTOR_INTERRUPT_HW20 29
|
||||
#define NDS32_VECTOR_INTERRUPT_HW21 30
|
||||
#define NDS32_VECTOR_INTERRUPT_HW22 31
|
||||
#define NDS32_VECTOR_INTERRUPT_HW23 32
|
||||
#define NDS32_VECTOR_INTERRUPT_HW24 33
|
||||
#define NDS32_VECTOR_INTERRUPT_HW25 34
|
||||
#define NDS32_VECTOR_INTERRUPT_HW26 35
|
||||
#define NDS32_VECTOR_INTERRUPT_HW27 36
|
||||
#define NDS32_VECTOR_INTERRUPT_HW28 37
|
||||
#define NDS32_VECTOR_INTERRUPT_HW29 38
|
||||
#define NDS32_VECTOR_INTERRUPT_HW30 39
|
||||
#define NDS32_VECTOR_INTERRUPT_HW31 40
|
||||
#define NDS32_VECTOR_INTERRUPT_HW32 41
|
||||
#define NDS32_VECTOR_INTERRUPT_HW33 42
|
||||
#define NDS32_VECTOR_INTERRUPT_HW34 43
|
||||
#define NDS32_VECTOR_INTERRUPT_HW35 44
|
||||
#define NDS32_VECTOR_INTERRUPT_HW36 45
|
||||
#define NDS32_VECTOR_INTERRUPT_HW37 46
|
||||
#define NDS32_VECTOR_INTERRUPT_HW38 47
|
||||
#define NDS32_VECTOR_INTERRUPT_HW39 48
|
||||
#define NDS32_VECTOR_INTERRUPT_HW40 49
|
||||
#define NDS32_VECTOR_INTERRUPT_HW41 50
|
||||
#define NDS32_VECTOR_INTERRUPT_HW42 51
|
||||
#define NDS32_VECTOR_INTERRUPT_HW43 52
|
||||
#define NDS32_VECTOR_INTERRUPT_HW44 53
|
||||
#define NDS32_VECTOR_INTERRUPT_HW45 54
|
||||
#define NDS32_VECTOR_INTERRUPT_HW46 55
|
||||
#define NDS32_VECTOR_INTERRUPT_HW47 56
|
||||
#define NDS32_VECTOR_INTERRUPT_HW48 57
|
||||
#define NDS32_VECTOR_INTERRUPT_HW49 58
|
||||
#define NDS32_VECTOR_INTERRUPT_HW50 59
|
||||
#define NDS32_VECTOR_INTERRUPT_HW51 60
|
||||
#define NDS32_VECTOR_INTERRUPT_HW52 61
|
||||
#define NDS32_VECTOR_INTERRUPT_HW53 62
|
||||
#define NDS32_VECTOR_INTERRUPT_HW54 63
|
||||
#define NDS32_VECTOR_INTERRUPT_HW55 64
|
||||
#define NDS32_VECTOR_INTERRUPT_HW56 65
|
||||
#define NDS32_VECTOR_INTERRUPT_HW57 66
|
||||
#define NDS32_VECTOR_INTERRUPT_HW58 67
|
||||
#define NDS32_VECTOR_INTERRUPT_HW59 68
|
||||
#define NDS32_VECTOR_INTERRUPT_HW60 69
|
||||
#define NDS32_VECTOR_INTERRUPT_HW61 70
|
||||
#define NDS32_VECTOR_INTERRUPT_HW62 71
|
||||
#define NDS32_VECTOR_INTERRUPT_HW63 72
|
||||
|
||||
#define NDS32ATTR_RESET(option) __attribute__((reset(option)))
|
||||
#define NDS32ATTR_EXCEPT(type) __attribute__((exception(type)))
|
||||
#define NDS32ATTR_EXCEPTION(type) __attribute__((exception(type)))
|
||||
#define NDS32ATTR_INTERRUPT(type) __attribute__((interrupt(type)))
|
||||
#define NDS32ATTR_ISR(type) __attribute__((interrupt(type)))
|
||||
|
||||
#endif /* nds32_isr.h */
|
||||
|
|
@ -1,3 +1,22 @@
|
|||
2018-08-12 Chung-Ju Wu <jasonwucj@gmail.com>
|
||||
|
||||
* config/nds32/t-nds32-isr: Rearrange object dependency.
|
||||
* config/nds32/initfini.c: Add dwarf2 unwinding support.
|
||||
* config/nds32/isr-library/adj_intr_lvl.inc: Consider new extensions
|
||||
and registers usage.
|
||||
* config/nds32/isr-library/excp_isr.S: Ditto.
|
||||
* config/nds32/isr-library/intr_isr.S: Ditto.
|
||||
* config/nds32/isr-library/reset.S: Ditto.
|
||||
* config/nds32/isr-library/restore_all.inc: Ditto.
|
||||
* config/nds32/isr-library/restore_mac_regs.inc: Ditto.
|
||||
* config/nds32/isr-library/restore_partial.inc: Ditto.
|
||||
* config/nds32/isr-library/restore_usr_regs.inc: Ditto.
|
||||
* config/nds32/isr-library/save_all.inc: Ditto.
|
||||
* config/nds32/isr-library/save_mac_regs.inc: Ditto.
|
||||
* config/nds32/isr-library/save_partial.inc: Ditto.
|
||||
* config/nds32/isr-library/save_usr_regs.inc: Ditto.
|
||||
* config/nds32/isr-library/vec_vid*.S: Consider 4-byte vector size.
|
||||
|
||||
2018-08-11 John David Anglin <danglin@gcc.gnu.org>
|
||||
|
||||
* config/pa/linux-atomic.c: Update comment.
|
||||
|
|
|
|||
|
|
@ -25,6 +25,10 @@
|
|||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include <stddef.h>
|
||||
/* Need header file for `struct object' type. */
|
||||
#include "../libgcc/unwind-dw2-fde.h"
|
||||
|
||||
/* Declare a pointer to void function type. */
|
||||
typedef void (*func_ptr) (void);
|
||||
|
||||
|
|
@ -42,11 +46,59 @@ typedef void (*func_ptr) (void);
|
|||
refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__
|
||||
symbol in crtinit.o, where they are defined. */
|
||||
|
||||
static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors")))
|
||||
= { (func_ptr) (-1) };
|
||||
static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"), used))
|
||||
= { (func_ptr) 0 };
|
||||
|
||||
static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors")))
|
||||
= { (func_ptr) (-1) };
|
||||
static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"), used))
|
||||
= { (func_ptr) 0 };
|
||||
|
||||
|
||||
#ifdef SUPPORT_UNWINDING_DWARF2
|
||||
/* Preparation of exception handling with dwar2 mechanism registration. */
|
||||
|
||||
asm ("\n\
|
||||
.section .eh_frame,\"aw\",@progbits\n\
|
||||
.global __EH_FRAME_BEGIN__\n\
|
||||
.type __EH_FRAME_BEGIN__, @object\n\
|
||||
.align 2\n\
|
||||
__EH_FRAME_BEGIN__:\n\
|
||||
! Beginning location of eh_frame section\n\
|
||||
.previous\n\
|
||||
");
|
||||
|
||||
extern func_ptr __EH_FRAME_BEGIN__[];
|
||||
|
||||
|
||||
/* Note that the following two functions are going to be chained into
|
||||
constructor and destructor list, repectively. So these two declarations
|
||||
must be placed after __CTOR_LIST__ and __DTOR_LIST. */
|
||||
extern void __nds32_register_eh(void) __attribute__((constructor, used));
|
||||
extern void __nds32_deregister_eh(void) __attribute__((destructor, used));
|
||||
|
||||
/* Register the exception handling table as the first constructor. */
|
||||
void
|
||||
__nds32_register_eh (void)
|
||||
{
|
||||
static struct object object;
|
||||
if (__register_frame_info)
|
||||
__register_frame_info (__EH_FRAME_BEGIN__, &object);
|
||||
}
|
||||
|
||||
/* Unregister the exception handling table as a deconstructor. */
|
||||
void
|
||||
__nds32_deregister_eh (void)
|
||||
{
|
||||
static int completed = 0;
|
||||
|
||||
if (completed)
|
||||
return;
|
||||
|
||||
if (__deregister_frame_info)
|
||||
__deregister_frame_info (__EH_FRAME_BEGIN__);
|
||||
|
||||
completed = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Run all the global destructors on exit from the program. */
|
||||
|
||||
|
|
@ -63,7 +115,7 @@ static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors")))
|
|||
same particular root executable or shared library file. */
|
||||
|
||||
static void __do_global_dtors (void)
|
||||
asm ("__do_global_dtors") __attribute__ ((section (".text")));
|
||||
asm ("__do_global_dtors") __attribute__ ((section (".text"), used));
|
||||
|
||||
static void
|
||||
__do_global_dtors (void)
|
||||
|
|
@ -116,23 +168,37 @@ void *__dso_handle = 0;
|
|||
last, these words naturally end up at the very ends of the two lists
|
||||
contained in these two sections. */
|
||||
|
||||
static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors")))
|
||||
static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"), used))
|
||||
= { (func_ptr) 0 };
|
||||
|
||||
static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors")))
|
||||
static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"), used))
|
||||
= { (func_ptr) 0 };
|
||||
|
||||
#ifdef SUPPORT_UNWINDING_DWARF2
|
||||
/* ZERO terminator in .eh_frame section. */
|
||||
asm ("\n\
|
||||
.section .eh_frame,\"aw\",@progbits\n\
|
||||
.global __EH_FRAME_END__\n\
|
||||
.type __EH_FRAME_END__, @object\n\
|
||||
.align 2\n\
|
||||
__EH_FRAME_END__:\n\
|
||||
! End location of eh_frame section with ZERO terminator\n\
|
||||
.word 0\n\
|
||||
.previous\n\
|
||||
");
|
||||
#endif
|
||||
|
||||
/* Run all global constructors for the program.
|
||||
Note that they are run in reverse order. */
|
||||
|
||||
static void __do_global_ctors (void)
|
||||
asm ("__do_global_ctors") __attribute__ ((section (".text")));
|
||||
asm ("__do_global_ctors") __attribute__ ((section (".text"), used));
|
||||
|
||||
static void
|
||||
__do_global_ctors (void)
|
||||
{
|
||||
func_ptr *p;
|
||||
for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--)
|
||||
for (p = __CTOR_END__ - 1; *p; p--)
|
||||
(*p) ();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -26,13 +26,26 @@
|
|||
.macro ADJ_INTR_LVL
|
||||
#if defined(NDS32_NESTED) /* Nested handler. */
|
||||
mfsr $r3, $PSW
|
||||
/* By substracting 1 from $PSW, we can lower PSW.INTL
|
||||
and enable GIE simultaneously. */
|
||||
addi $r3, $r3, #-0x1
|
||||
#if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
|
||||
ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */
|
||||
#endif
|
||||
mtsr $r3, $PSW
|
||||
#elif defined(NDS32_NESTED_READY) /* Nested ready handler. */
|
||||
/* Save ipc and ipsw and lower INT level. */
|
||||
mfsr $r3, $PSW
|
||||
addi $r3, $r3, #-0x2
|
||||
#if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
|
||||
ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */
|
||||
#endif
|
||||
mtsr $r3, $PSW
|
||||
#else /* Not nested handler. */
|
||||
#if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
|
||||
mfsr $r3, $PSW
|
||||
ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */
|
||||
mtsr $r3, $PSW
|
||||
#endif
|
||||
#endif
|
||||
.endm
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "save_usr_regs.inc"
|
||||
#include "save_mac_regs.inc"
|
||||
#include "save_fpu_regs.inc"
|
||||
#include "save_fpu_regs_00.inc"
|
||||
|
|
@ -32,35 +33,33 @@
|
|||
#include "save_all.inc"
|
||||
#include "save_partial.inc"
|
||||
#include "adj_intr_lvl.inc"
|
||||
#include "restore_mac_regs.inc"
|
||||
#include "restore_fpu_regs_00.inc"
|
||||
#include "restore_fpu_regs_01.inc"
|
||||
#include "restore_fpu_regs_02.inc"
|
||||
#include "restore_fpu_regs_03.inc"
|
||||
#include "restore_fpu_regs.inc"
|
||||
#include "restore_mac_regs.inc"
|
||||
#include "restore_usr_regs.inc"
|
||||
#include "restore_all.inc"
|
||||
#include "restore_partial.inc"
|
||||
|
||||
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
|
||||
.align 1
|
||||
/*
|
||||
First Level Handlers
|
||||
1. First Level Handlers are invokded in vector section via jump instruction
|
||||
with specific names for different configurations.
|
||||
2. Naming Format: _nds32_e_SR_NT for exception handlers.
|
||||
_nds32_i_SR_NT for interrupt handlers.
|
||||
2.1 All upper case letters are replaced with specific lower case letters encodings.
|
||||
2.2 SR: Saved Registers
|
||||
sa: Save All regs (context)
|
||||
ps: Partial Save (all caller-saved regs)
|
||||
2.3 NT: Nested Type
|
||||
ns: nested
|
||||
nn: not nested
|
||||
nr: nested ready
|
||||
*/
|
||||
|
||||
/*
|
||||
This is original 16-byte vector size version.
|
||||
*/
|
||||
/* First Level Handlers
|
||||
1. First Level Handlers are invokded in vector section via jump instruction
|
||||
with specific names for different configurations.
|
||||
2. Naming Format: _nds32_e_SR_NT for exception handlers.
|
||||
_nds32_i_SR_NT for interrupt handlers.
|
||||
2.1 All upper case letters are replaced with specific lower case letters encodings.
|
||||
2.2 SR -- Saved Registers
|
||||
sa: Save All regs (context)
|
||||
ps: Partial Save (all caller-saved regs)
|
||||
2.3 NT -- Nested Type
|
||||
ns: nested
|
||||
nn: not nested
|
||||
nr: nested ready */
|
||||
|
||||
#ifdef NDS32_SAVE_ALL_REGS
|
||||
#if defined(NDS32_NESTED)
|
||||
.globl _nds32_e_sa_ns
|
||||
|
|
@ -91,21 +90,26 @@ _nds32_e_ps_nn:
|
|||
#endif /* endif for Nest Type */
|
||||
#endif /* not NDS32_SAVE_ALL_REGS */
|
||||
|
||||
/*
|
||||
This is 16-byte vector size version.
|
||||
The vector id was restored into $r0 in vector by compiler.
|
||||
*/
|
||||
|
||||
/* For 4-byte vector size version, the vector id is
|
||||
extracted from $ITYPE and is set into $r0 by library.
|
||||
For 16-byte vector size version, the vector id
|
||||
is set into $r0 in vector section by compiler. */
|
||||
|
||||
/* Save used registers. */
|
||||
#ifdef NDS32_SAVE_ALL_REGS
|
||||
SAVE_ALL
|
||||
#else
|
||||
SAVE_PARTIAL
|
||||
#endif
|
||||
|
||||
/* Prepare to call 2nd level handler. */
|
||||
la $r2, _nds32_jmptbl_00
|
||||
lw $r2, [$r2 + $r0 << #2]
|
||||
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
|
||||
jral $r2
|
||||
/* Restore used registers. */
|
||||
|
||||
/* Restore used registers. */
|
||||
#ifdef NDS32_SAVE_ALL_REGS
|
||||
RESTORE_ALL
|
||||
#else
|
||||
|
|
@ -113,6 +117,7 @@ _nds32_e_ps_nn:
|
|||
#endif
|
||||
iret
|
||||
|
||||
|
||||
#ifdef NDS32_SAVE_ALL_REGS
|
||||
#if defined(NDS32_NESTED)
|
||||
.size _nds32_e_sa_ns, .-_nds32_e_sa_ns
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "save_usr_regs.inc"
|
||||
#include "save_mac_regs.inc"
|
||||
#include "save_fpu_regs.inc"
|
||||
#include "save_fpu_regs_00.inc"
|
||||
|
|
@ -32,35 +33,33 @@
|
|||
#include "save_all.inc"
|
||||
#include "save_partial.inc"
|
||||
#include "adj_intr_lvl.inc"
|
||||
#include "restore_mac_regs.inc"
|
||||
#include "restore_fpu_regs_00.inc"
|
||||
#include "restore_fpu_regs_01.inc"
|
||||
#include "restore_fpu_regs_02.inc"
|
||||
#include "restore_fpu_regs_03.inc"
|
||||
#include "restore_fpu_regs.inc"
|
||||
#include "restore_mac_regs.inc"
|
||||
#include "restore_usr_regs.inc"
|
||||
#include "restore_all.inc"
|
||||
#include "restore_partial.inc"
|
||||
|
||||
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
|
||||
.align 1
|
||||
/*
|
||||
First Level Handlers
|
||||
1. First Level Handlers are invokded in vector section via jump instruction
|
||||
with specific names for different configurations.
|
||||
2. Naming Format: _nds32_e_SR_NT for exception handlers.
|
||||
_nds32_i_SR_NT for interrupt handlers.
|
||||
2.1 All upper case letters are replaced with specific lower case letters encodings.
|
||||
2.2 SR: Saved Registers
|
||||
sa: Save All regs (context)
|
||||
ps: Partial Save (all caller-saved regs)
|
||||
2.3 NT: Nested Type
|
||||
ns: nested
|
||||
nn: not nested
|
||||
nr: nested ready
|
||||
*/
|
||||
|
||||
/*
|
||||
This is original 16-byte vector size version.
|
||||
*/
|
||||
/* First Level Handlers
|
||||
1. First Level Handlers are invokded in vector section via jump instruction
|
||||
with specific names for different configurations.
|
||||
2. Naming Format: _nds32_e_SR_NT for exception handlers.
|
||||
_nds32_i_SR_NT for interrupt handlers.
|
||||
2.1 All upper case letters are replaced with specific lower case letters encodings.
|
||||
2.2 SR -- Saved Registers
|
||||
sa: Save All regs (context)
|
||||
ps: Partial Save (all caller-saved regs)
|
||||
2.3 NT -- Nested Type
|
||||
ns: nested
|
||||
nn: not nested
|
||||
nr: nested ready */
|
||||
|
||||
#ifdef NDS32_SAVE_ALL_REGS
|
||||
#if defined(NDS32_NESTED)
|
||||
.globl _nds32_i_sa_ns
|
||||
|
|
@ -91,21 +90,36 @@ _nds32_i_ps_nn:
|
|||
#endif /* endif for Nest Type */
|
||||
#endif /* not NDS32_SAVE_ALL_REGS */
|
||||
|
||||
/*
|
||||
This is 16-byte vector size version.
|
||||
The vector id was restored into $r0 in vector by compiler.
|
||||
*/
|
||||
|
||||
/* For 4-byte vector size version, the vector id is
|
||||
extracted from $ITYPE and is set into $r0 by library.
|
||||
For 16-byte vector size version, the vector id
|
||||
is set into $r0 in vector section by compiler. */
|
||||
|
||||
/* Save used registers first. */
|
||||
#ifdef NDS32_SAVE_ALL_REGS
|
||||
SAVE_ALL
|
||||
#else
|
||||
SAVE_PARTIAL
|
||||
#endif
|
||||
/* Prepare to call 2nd level handler. */
|
||||
|
||||
/* According to vector size, we need to have different implementation. */
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* Prepare to call 2nd level handler. */
|
||||
la $r2, _nds32_jmptbl_00
|
||||
lw $r2, [$r2 + $r0 << #2]
|
||||
addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */
|
||||
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
|
||||
jral $r2
|
||||
#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
|
||||
/* Prepare to call 2nd level handler. */
|
||||
la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */
|
||||
lw $r2, [$r2 + $r0 << #2]
|
||||
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
|
||||
jral $r2
|
||||
/* Restore used registers. */
|
||||
#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
|
||||
|
||||
/* Restore used registers. */
|
||||
#ifdef NDS32_SAVE_ALL_REGS
|
||||
RESTORE_ALL
|
||||
#else
|
||||
|
|
@ -113,6 +127,7 @@ _nds32_i_ps_nn:
|
|||
#endif
|
||||
iret
|
||||
|
||||
|
||||
#ifdef NDS32_SAVE_ALL_REGS
|
||||
#if defined(NDS32_NESTED)
|
||||
.size _nds32_i_sa_ns, .-_nds32_i_sa_ns
|
||||
|
|
|
|||
|
|
@ -26,22 +26,18 @@
|
|||
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
|
||||
.align 1
|
||||
.weak _SDA_BASE_ /* For reset handler only. */
|
||||
.weak _FP_BASE_ /* For reset handler only. */
|
||||
.weak _nds32_init_mem /* User defined memory initialization function. */
|
||||
.globl _start
|
||||
.globl _nds32_reset
|
||||
.type _nds32_reset, @function
|
||||
_nds32_reset:
|
||||
_start:
|
||||
#ifdef NDS32_EXT_EX9
|
||||
.no_ex9_begin
|
||||
#endif
|
||||
/* Handle NMI and warm boot if any of them exists. */
|
||||
beqz $sp, 1f /* Reset, NMI or warm boot? */
|
||||
/* Either NMI or warm boot; save all regs. */
|
||||
|
||||
/* Preserve registers for context-switching. */
|
||||
#ifdef __NDS32_REDUCED_REGS__
|
||||
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
|
||||
/* For 16-reg mode. */
|
||||
smw.adm $r0, [$sp], $r10, #0x0
|
||||
smw.adm $r15, [$sp], $r15, #0xf
|
||||
|
|
@ -49,10 +45,9 @@ _start:
|
|||
/* For 32-reg mode. */
|
||||
smw.adm $r0, [$sp], $r27, #0xf
|
||||
#endif
|
||||
#ifdef NDS32_EXT_IFC
|
||||
#if __NDS32_EXT_IFC__
|
||||
mfusr $r1, $IFC_LP
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
|
||||
stack 8-byte alignment. */
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte alignment. */
|
||||
#endif
|
||||
|
||||
la $gp, _SDA_BASE_ /* Init GP for small data access. */
|
||||
|
|
@ -71,12 +66,11 @@ _start:
|
|||
bnez $r0, 1f /* If fail to resume, do cold boot. */
|
||||
|
||||
/* Restore registers for context-switching. */
|
||||
#ifdef NDS32_EXT_IFC
|
||||
lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
|
||||
stack 8-byte alignment. */
|
||||
#if __NDS32_EXT_IFC__
|
||||
lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep stack 8-byte alignment. */
|
||||
mtusr $r1, $IFC_LP
|
||||
#endif
|
||||
#ifdef __NDS32_REDUCED_REGS__
|
||||
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
|
||||
/* For 16-reg mode. */
|
||||
lmw.bim $r15, [$sp], $r15, #0xf
|
||||
lmw.bim $r0, [$sp], $r10, #0x0
|
||||
|
|
@ -88,6 +82,17 @@ _start:
|
|||
|
||||
|
||||
1: /* Cold boot. */
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* With vector ID feature for v3 architecture, default vector size is 4-byte. */
|
||||
/* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */
|
||||
mfsr $r0, $IVB
|
||||
li $r1, #0xc000
|
||||
or $r0, $r0, $r1
|
||||
xor $r0, $r0, $r1
|
||||
mtsr $r0, $IVB
|
||||
dsb
|
||||
#else
|
||||
/* There is no vector ID feature, so the vector size must be 16-byte. */
|
||||
/* Set IVB.ESZ = 1 (vector table entry size = 16 bytes) */
|
||||
mfsr $r0, $IVB
|
||||
li $r1, #0xffff3fff
|
||||
|
|
@ -95,36 +100,54 @@ _start:
|
|||
ori $r0, $r0, #0x4000
|
||||
mtsr $r0, $IVB
|
||||
dsb
|
||||
#endif
|
||||
|
||||
la $gp, _SDA_BASE_ /* Init $gp. */
|
||||
la $fp, _FP_BASE_ /* Init $fp. */
|
||||
la $sp, _stack /* Init $sp. */
|
||||
#ifdef NDS32_EXT_EX9
|
||||
/*
|
||||
* Initialize the table base of EX9 instruction
|
||||
* ex9 generation needs to disable before the ITB is set
|
||||
*/
|
||||
mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */
|
||||
|
||||
#if __NDS32_EXT_EX9__
|
||||
.L_init_itb:
|
||||
/* Initialization for Instruction Table Base (ITB).
|
||||
The symbol _ITB_BASE_ is determined by Linker.
|
||||
Set $ITB only if MSC_CFG.EIT (cr4.b'24) is set. */
|
||||
mfsr $r0, $MSC_CFG
|
||||
srli $r0, $r0, 24
|
||||
andi $r0, $r0, 0x1
|
||||
beqz $r0, 4f /* Zero means HW does not support EX9. */
|
||||
la $r0, _ITB_BASE_ /* Init $ITB. */
|
||||
beqz $r0, 4f /* Fall through ? */
|
||||
la $r0, _ITB_BASE_
|
||||
mtusr $r0, $ITB
|
||||
.no_ex9_end
|
||||
4:
|
||||
#endif
|
||||
la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem
|
||||
may written by C language. */
|
||||
|
||||
#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__
|
||||
.L_init_fpu:
|
||||
/* Initialize FPU
|
||||
Set FUCOP_CTL.CP0EN (fucpr.b'0). */
|
||||
mfsr $r0, $FUCOP_CTL
|
||||
ori $r0, $r0, 0x1
|
||||
mtsr $r0, $FUCOP_CTL
|
||||
dsb
|
||||
/* According to [bugzilla #9425], set flush-to-zero mode.
|
||||
That is, set $FPCSR.DNZ(b'12) = 1. */
|
||||
FMFCSR $r0
|
||||
ori $r0, $r0, 0x1000
|
||||
FMTCSR $r0
|
||||
dsb
|
||||
#endif
|
||||
|
||||
/* Call DRAM init. _nds32_init_mem may written by C language. */
|
||||
la $r15, _nds32_init_mem
|
||||
beqz $r15, 6f
|
||||
jral $r15
|
||||
6:
|
||||
l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */
|
||||
jral $r15
|
||||
/* Reset handler() should never return in a RTOS or non-OS system.
|
||||
In case it does return, an exception will be generated.
|
||||
This exception will be caught either by default break handler or by EDM.
|
||||
Default break handle may just do an infinite loop.
|
||||
EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
|
||||
|
||||
/* Reset handler() should never return in a RTOS or non-OS system.
|
||||
In case it does return, an exception will be generated.
|
||||
This exception will be caught either by default break handler or by EDM.
|
||||
Default break handle may just do an infinite loop.
|
||||
EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
|
||||
5:
|
||||
break #0x7fff
|
||||
.size _nds32_reset, .-_nds32_reset
|
||||
|
|
|
|||
|
|
@ -31,15 +31,11 @@
|
|||
mtsr $r2, $IPSW
|
||||
RESTORE_FPU_REGS
|
||||
RESTORE_MAC_REGS
|
||||
#ifdef NDS32_EXT_IFC
|
||||
lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
|
||||
stack 8-byte alignment. */
|
||||
mtusr $r1, $IFC_LP
|
||||
#endif
|
||||
#ifdef __NDS32_REDUCED_REGS__
|
||||
RESTORE_USR_REGS
|
||||
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
|
||||
lmw.bim $r0, [$sp], $r10, #0x0 /* Restore all regs. */
|
||||
lmw.bim $r15, [$sp], $r15, #0xf
|
||||
#else /* not __NDS32_REDUCED_REGS__ */
|
||||
#else
|
||||
lmw.bim $r0, [$sp], $r27, #0xf /* Restore all regs. */
|
||||
#endif
|
||||
.endm
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.macro RESTORE_MAC_REGS
|
||||
#ifdef NDS32_DX_REGS
|
||||
#if __NDS32_DX_REGS__
|
||||
lmw.bim $r1, [$sp], $r4, #0x0
|
||||
mtusr $r1, $d0.lo
|
||||
mtusr $r2, $d0.hi
|
||||
|
|
|
|||
|
|
@ -31,15 +31,11 @@
|
|||
mtsr $r1, $IPC /* Set IPC. */
|
||||
mtsr $r2, $IPSW /* Set IPSW. */
|
||||
#endif
|
||||
RESTORE_FPU_REGS
|
||||
RESTORE_MAC_REGS
|
||||
#ifdef NDS32_EXT_IFC
|
||||
lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
|
||||
stack 8-byte alignment. */
|
||||
mtusr $r1, $IFC_LP
|
||||
#endif
|
||||
RESTORE_FPU_REGS
|
||||
RESTORE_MAC_REGS
|
||||
RESTORE_USR_REGS
|
||||
lmw.bim $r0, [$sp], $r5, #0x0 /* Restore all regs. */
|
||||
#ifdef __NDS32_REDUCED_REGS__
|
||||
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
|
||||
lmw.bim $r15, [$sp], $r15, #0x2
|
||||
#else
|
||||
lmw.bim $r15, [$sp], $r27, #0x2 /* Restore all regs. */
|
||||
|
|
|
|||
42
libgcc/config/nds32/isr-library/restore_usr_regs.inc
Normal file
42
libgcc/config/nds32/isr-library/restore_usr_regs.inc
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
|
||||
Copyright (C) 2012-2018 Free Software Foundation, Inc.
|
||||
Contributed by Andes Technology Corporation.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.macro RESTORE_USR_REGS
|
||||
#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__)
|
||||
lmw.bim $r1, [$sp], $r4, #0x0
|
||||
mtusr $r1, $IFC_LP
|
||||
mtusr $r2, $LB
|
||||
mtusr $r3, $LE
|
||||
mtusr $r4, $LC
|
||||
#elif __NDS32_EXT_IFC__
|
||||
lmw.bim $r1, [$sp], $r2, #0x0
|
||||
mtusr $r1, $IFC_LP
|
||||
#elif __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
|
||||
lmw.bim $r1, [$sp], $r4, #0x0
|
||||
mtusr $r1, $LB
|
||||
mtusr $r2, $LE
|
||||
mtusr $r3, $LC
|
||||
#endif
|
||||
.endm
|
||||
|
|
@ -23,45 +23,42 @@
|
|||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.macro SAVE_ALL_4B
|
||||
#ifdef __NDS32_REDUCED_REGS__
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
|
||||
/* If vector size is 4-byte, we have to save registers
|
||||
in the macro implementation. */
|
||||
.macro SAVE_ALL
|
||||
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
|
||||
smw.adm $r15, [$sp], $r15, #0xf
|
||||
smw.adm $r0, [$sp], $r10, #0x0
|
||||
#else /* not __NDS32_REDUCED_REGS__ */
|
||||
#else
|
||||
smw.adm $r0, [$sp], $r27, #0xf
|
||||
#endif /* not __NDS32_REDUCED_REGS__ */
|
||||
#ifdef NDS32_EXT_IFC
|
||||
mfusr $r1, $IFC_LP
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
|
||||
stack 8-byte alignment. */
|
||||
#endif
|
||||
SAVE_MAC_REGS
|
||||
SAVE_FPU_REGS
|
||||
SAVE_USR_REGS
|
||||
SAVE_MAC_REGS
|
||||
SAVE_FPU_REGS
|
||||
mfsr $r1, $IPC /* Get IPC. */
|
||||
mfsr $r2, $IPSW /* Get IPSW. */
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
|
||||
move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
|
||||
mfsr $r0, $ITYPE /* Get VID to $r0. */
|
||||
srli $r0, $r0, #5
|
||||
#ifdef __NDS32_ISA_V2__
|
||||
andi $r0, $r0, #127
|
||||
#else
|
||||
fexti33 $r0, #6
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
|
||||
|
||||
/* If vector size is 16-byte, some works can be done in
|
||||
the vector section generated by compiler, so that we
|
||||
can implement less in the macro. */
|
||||
.macro SAVE_ALL
|
||||
/* SAVE_REG_TBL code has been moved to
|
||||
vector table generated by compiler. */
|
||||
#ifdef NDS32_EXT_IFC
|
||||
mfusr $r1, $IFC_LP
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
|
||||
stack 8-byte alignment. */
|
||||
#endif
|
||||
SAVE_MAC_REGS
|
||||
SAVE_FPU_REGS
|
||||
SAVE_USR_REGS
|
||||
SAVE_MAC_REGS
|
||||
SAVE_FPU_REGS
|
||||
mfsr $r1, $IPC /* Get IPC. */
|
||||
mfsr $r2, $IPSW /* Get IPSW. */
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
|
||||
move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
|
||||
.endm
|
||||
|
||||
#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.macro SAVE_MAC_REGS
|
||||
#ifdef NDS32_DX_REGS
|
||||
#if __NDS32_DX_REGS__
|
||||
mfusr $r1, $d0.lo
|
||||
mfusr $r2, $d0.hi
|
||||
mfusr $r3, $d1.lo
|
||||
|
|
|
|||
|
|
@ -23,20 +23,20 @@
|
|||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.macro SAVE_PARTIAL_4B
|
||||
#ifdef __NDS32_REDUCED_REGS__
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
|
||||
/* If vector size is 4-byte, we have to save registers
|
||||
in the macro implementation. */
|
||||
.macro SAVE_PARTIAL
|
||||
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
|
||||
smw.adm $r15, [$sp], $r15, #0x2
|
||||
#else /* not __NDS32_REDUCED_REGS__ */
|
||||
#else
|
||||
smw.adm $r15, [$sp], $r27, #0x2
|
||||
#endif /* not __NDS32_REDUCED_REGS__ */
|
||||
smw.adm $r0, [$sp], $r5, #0x0
|
||||
#ifdef NDS32_EXT_IFC
|
||||
mfusr $r1, $IFC_LP
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
|
||||
stack 8-byte alignment. */
|
||||
#endif
|
||||
SAVE_MAC_REGS
|
||||
SAVE_FPU_REGS
|
||||
smw.adm $r0, [$sp], $r5, #0x0
|
||||
SAVE_USR_REGS
|
||||
SAVE_MAC_REGS
|
||||
SAVE_FPU_REGS
|
||||
#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
|
||||
mfsr $r1, $IPC /* Get IPC. */
|
||||
mfsr $r2, $IPSW /* Get IPSW. */
|
||||
|
|
@ -44,26 +44,24 @@
|
|||
#endif
|
||||
mfsr $r0, $ITYPE /* Get VID to $r0. */
|
||||
srli $r0, $r0, #5
|
||||
#ifdef __NDS32_ISA_V2__
|
||||
andi $r0, $r0, #127
|
||||
#else
|
||||
fexti33 $r0, #6
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
|
||||
|
||||
/* If vector size is 16-byte, some works can be done in
|
||||
the vector section generated by compiler, so that we
|
||||
can implement less in the macro. */
|
||||
|
||||
.macro SAVE_PARTIAL
|
||||
/* SAVE_CALLER_REGS code has been moved to
|
||||
vector table generated by compiler. */
|
||||
#ifdef NDS32_EXT_IFC
|
||||
mfusr $r1, $IFC_LP
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
|
||||
stack 8-byte alignment. */
|
||||
#endif
|
||||
SAVE_MAC_REGS
|
||||
SAVE_FPU_REGS
|
||||
SAVE_USR_REGS
|
||||
SAVE_MAC_REGS
|
||||
SAVE_FPU_REGS
|
||||
#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
|
||||
mfsr $r1, $IPC /* Get IPC. */
|
||||
mfsr $r2, $IPSW /* Get IPSW. */
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
|
||||
|
|
|
|||
44
libgcc/config/nds32/isr-library/save_usr_regs.inc
Normal file
44
libgcc/config/nds32/isr-library/save_usr_regs.inc
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
|
||||
Copyright (C) 2012-2018 Free Software Foundation, Inc.
|
||||
Contributed by Andes Technology Corporation.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.macro SAVE_USR_REGS
|
||||
/* Store User Special Registers according to supported ISA extension
|
||||
!!! WATCH OUT !!! Take care of 8-byte alignment issue. */
|
||||
#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__)
|
||||
mfusr $r1, $IFC_LP
|
||||
mfusr $r2, $LB
|
||||
mfusr $r3, $LE
|
||||
mfusr $r4, $LC
|
||||
smw.adm $r1, [$sp], $r4, #0x0 /* Save even. Ok! */
|
||||
#elif __NDS32_EXT_IFC__
|
||||
mfusr $r1, $IFC_LP
|
||||
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte aligned. */
|
||||
#elif (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__)
|
||||
mfusr $r1, $LB
|
||||
mfusr $r2, $LE
|
||||
mfusr $r3, $LC
|
||||
smw.adm $r1, [$sp], $r4, #0x0 /* Save extra $r4 to keep stack 8-byte aligned. */
|
||||
#endif
|
||||
.endm
|
||||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.00, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_00
|
||||
.type _nds32_vector_00, @function
|
||||
_nds32_vector_00:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.01, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_01
|
||||
.type _nds32_vector_01, @function
|
||||
_nds32_vector_01:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.02, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_02
|
||||
.type _nds32_vector_02, @function
|
||||
_nds32_vector_02:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.03, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_03
|
||||
.type _nds32_vector_03, @function
|
||||
_nds32_vector_03:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.04, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_04
|
||||
.type _nds32_vector_04, @function
|
||||
_nds32_vector_04:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.05, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_05
|
||||
.type _nds32_vector_05, @function
|
||||
_nds32_vector_05:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.06, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_06
|
||||
.type _nds32_vector_06, @function
|
||||
_nds32_vector_06:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.07, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_07
|
||||
.type _nds32_vector_07, @function
|
||||
_nds32_vector_07:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.08, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_08
|
||||
.type _nds32_vector_08, @function
|
||||
_nds32_vector_08:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.09, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_09
|
||||
.type _nds32_vector_09, @function
|
||||
_nds32_vector_09:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.10, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_10
|
||||
.type _nds32_vector_10, @function
|
||||
_nds32_vector_10:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.11, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_11
|
||||
.type _nds32_vector_11, @function
|
||||
_nds32_vector_11:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.12, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_12
|
||||
.type _nds32_vector_12, @function
|
||||
_nds32_vector_12:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.13, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_13
|
||||
.type _nds32_vector_13, @function
|
||||
_nds32_vector_13:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.14, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_14
|
||||
.type _nds32_vector_14, @function
|
||||
_nds32_vector_14:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.15, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_15
|
||||
.type _nds32_vector_15, @function
|
||||
_nds32_vector_15:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.16, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_16
|
||||
.type _nds32_vector_16, @function
|
||||
_nds32_vector_16:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.17, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_17
|
||||
.type _nds32_vector_17, @function
|
||||
_nds32_vector_17:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.18, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_18
|
||||
.type _nds32_vector_18, @function
|
||||
_nds32_vector_18:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.19, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_19
|
||||
.type _nds32_vector_19, @function
|
||||
_nds32_vector_19:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.20, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_20
|
||||
.type _nds32_vector_20, @function
|
||||
_nds32_vector_20:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.21, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_21
|
||||
.type _nds32_vector_21, @function
|
||||
_nds32_vector_21:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.22, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_22
|
||||
.type _nds32_vector_22, @function
|
||||
_nds32_vector_22:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.23, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_23
|
||||
.type _nds32_vector_23, @function
|
||||
_nds32_vector_23:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.24, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_24
|
||||
.type _nds32_vector_24, @function
|
||||
_nds32_vector_24:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.25, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_25
|
||||
.type _nds32_vector_25, @function
|
||||
_nds32_vector_25:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.26, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_26
|
||||
.type _nds32_vector_26, @function
|
||||
_nds32_vector_26:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.27, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_27
|
||||
.type _nds32_vector_27, @function
|
||||
_nds32_vector_27:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.28, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_28
|
||||
.type _nds32_vector_28, @function
|
||||
_nds32_vector_28:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.29, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_29
|
||||
.type _nds32_vector_29, @function
|
||||
_nds32_vector_29:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.30, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_30
|
||||
.type _nds32_vector_30, @function
|
||||
_nds32_vector_30:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.31, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_31
|
||||
.type _nds32_vector_31, @function
|
||||
_nds32_vector_31:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.32, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_32
|
||||
.type _nds32_vector_32, @function
|
||||
_nds32_vector_32:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.33, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_33
|
||||
.type _nds32_vector_33, @function
|
||||
_nds32_vector_33:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.34, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_34
|
||||
.type _nds32_vector_34, @function
|
||||
_nds32_vector_34:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.35, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_35
|
||||
.type _nds32_vector_35, @function
|
||||
_nds32_vector_35:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.36, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_36
|
||||
.type _nds32_vector_36, @function
|
||||
_nds32_vector_36:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.37, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_37
|
||||
.type _nds32_vector_37, @function
|
||||
_nds32_vector_37:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.38, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_38
|
||||
.type _nds32_vector_38, @function
|
||||
_nds32_vector_38:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.39, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_39
|
||||
.type _nds32_vector_39, @function
|
||||
_nds32_vector_39:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.40, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_40
|
||||
.type _nds32_vector_40, @function
|
||||
_nds32_vector_40:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.41, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_41
|
||||
.type _nds32_vector_41, @function
|
||||
_nds32_vector_41:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.42, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_42
|
||||
.type _nds32_vector_42, @function
|
||||
_nds32_vector_42:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.43, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_43
|
||||
.type _nds32_vector_43, @function
|
||||
_nds32_vector_43:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.44, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_44
|
||||
.type _nds32_vector_44, @function
|
||||
_nds32_vector_44:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.45, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_45
|
||||
.type _nds32_vector_45, @function
|
||||
_nds32_vector_45:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.46, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_46
|
||||
.type _nds32_vector_46, @function
|
||||
_nds32_vector_46:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.47, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_47
|
||||
.type _nds32_vector_47, @function
|
||||
_nds32_vector_47:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.48, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_48
|
||||
.type _nds32_vector_48, @function
|
||||
_nds32_vector_48:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.49, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_49
|
||||
.type _nds32_vector_49, @function
|
||||
_nds32_vector_49:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.50, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_50
|
||||
.type _nds32_vector_50, @function
|
||||
_nds32_vector_50:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.51, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_51
|
||||
.type _nds32_vector_51, @function
|
||||
_nds32_vector_51:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.52, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_52
|
||||
.type _nds32_vector_52, @function
|
||||
_nds32_vector_52:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.53, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_53
|
||||
.type _nds32_vector_53, @function
|
||||
_nds32_vector_53:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.54, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_54
|
||||
.type _nds32_vector_54, @function
|
||||
_nds32_vector_54:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.55, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_55
|
||||
.type _nds32_vector_55, @function
|
||||
_nds32_vector_55:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.56, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_56
|
||||
.type _nds32_vector_56, @function
|
||||
_nds32_vector_56:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.57, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_57
|
||||
.type _nds32_vector_57, @function
|
||||
_nds32_vector_57:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.58, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_58
|
||||
.type _nds32_vector_58, @function
|
||||
_nds32_vector_58:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.59, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_59
|
||||
.type _nds32_vector_59, @function
|
||||
_nds32_vector_59:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.60, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_60
|
||||
.type _nds32_vector_60, @function
|
||||
_nds32_vector_60:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.61, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_61
|
||||
.type _nds32_vector_61, @function
|
||||
_nds32_vector_61:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.62, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_62
|
||||
.type _nds32_vector_62, @function
|
||||
_nds32_vector_62:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.63, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_63
|
||||
.type _nds32_vector_63, @function
|
||||
_nds32_vector_63:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.64, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_64
|
||||
.type _nds32_vector_64, @function
|
||||
_nds32_vector_64:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.65, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_65
|
||||
.type _nds32_vector_65, @function
|
||||
_nds32_vector_65:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.66, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_66
|
||||
.type _nds32_vector_66, @function
|
||||
_nds32_vector_66:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.67, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_67
|
||||
.type _nds32_vector_67, @function
|
||||
_nds32_vector_67:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.68, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_68
|
||||
.type _nds32_vector_68, @function
|
||||
_nds32_vector_68:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.69, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_69
|
||||
.type _nds32_vector_69, @function
|
||||
_nds32_vector_69:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.70, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_70
|
||||
.type _nds32_vector_70, @function
|
||||
_nds32_vector_70:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.71, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_71
|
||||
.type _nds32_vector_71, @function
|
||||
_nds32_vector_71:
|
||||
|
|
|
|||
|
|
@ -24,8 +24,15 @@
|
|||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
.section .nds32_vector.72, "ax"
|
||||
#if __NDS32_ISR_VECTOR_SIZE_4__
|
||||
/* The vector size is default 4-byte for v3 architecture. */
|
||||
.vec_size 4
|
||||
.align 2
|
||||
#else
|
||||
/* The vector size is default 16-byte for other architectures. */
|
||||
.vec_size 16
|
||||
.align 4
|
||||
#endif
|
||||
.weak _nds32_vector_72
|
||||
.type _nds32_vector_72, @function
|
||||
_nds32_vector_72:
|
||||
|
|
|
|||
|
|
@ -23,11 +23,11 @@
|
|||
# Makfile fragment rules for libnds32_isr.a to support ISR attribute extension
|
||||
###############################################################################
|
||||
|
||||
# basic flags setting
|
||||
# Basic flags setting.
|
||||
ISR_CFLAGS = $(CFLAGS) -c
|
||||
|
||||
# the object files we would like to create
|
||||
LIBNDS32_ISR_16B_OBJS = \
|
||||
# The object files we would like to create.
|
||||
LIBNDS32_ISR_VEC_OBJS = \
|
||||
vec_vid00.o vec_vid01.o vec_vid02.o vec_vid03.o \
|
||||
vec_vid04.o vec_vid05.o vec_vid06.o vec_vid07.o \
|
||||
vec_vid08.o vec_vid09.o vec_vid10.o vec_vid11.o \
|
||||
|
|
@ -46,40 +46,9 @@ LIBNDS32_ISR_16B_OBJS = \
|
|||
vec_vid60.o vec_vid61.o vec_vid62.o vec_vid63.o \
|
||||
vec_vid64.o vec_vid65.o vec_vid66.o vec_vid67.o \
|
||||
vec_vid68.o vec_vid69.o vec_vid70.o vec_vid71.o \
|
||||
vec_vid72.o \
|
||||
excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \
|
||||
excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \
|
||||
intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \
|
||||
intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \
|
||||
reset.o
|
||||
vec_vid72.o
|
||||
|
||||
LIBNDS32_ISR_4B_OBJS = \
|
||||
vec_vid00_4b.o vec_vid01_4b.o vec_vid02_4b.o vec_vid03_4b.o \
|
||||
vec_vid04_4b.o vec_vid05_4b.o vec_vid06_4b.o vec_vid07_4b.o \
|
||||
vec_vid08_4b.o vec_vid09_4b.o vec_vid10_4b.o vec_vid11_4b.o \
|
||||
vec_vid12_4b.o vec_vid13_4b.o vec_vid14_4b.o vec_vid15_4b.o \
|
||||
vec_vid16_4b.o vec_vid17_4b.o vec_vid18_4b.o vec_vid19_4b.o \
|
||||
vec_vid20_4b.o vec_vid21_4b.o vec_vid22_4b.o vec_vid23_4b.o \
|
||||
vec_vid24_4b.o vec_vid25_4b.o vec_vid26_4b.o vec_vid27_4b.o \
|
||||
vec_vid28_4b.o vec_vid29_4b.o vec_vid30_4b.o vec_vid31_4b.o \
|
||||
vec_vid32_4b.o vec_vid33_4b.o vec_vid34_4b.o vec_vid35_4b.o \
|
||||
vec_vid36_4b.o vec_vid37_4b.o vec_vid38_4b.o vec_vid39_4b.o \
|
||||
vec_vid40_4b.o vec_vid41_4b.o vec_vid42_4b.o vec_vid43_4b.o \
|
||||
vec_vid44_4b.o vec_vid45_4b.o vec_vid46_4b.o vec_vid47_4b.o \
|
||||
vec_vid48_4b.o vec_vid49_4b.o vec_vid50_4b.o vec_vid51_4b.o \
|
||||
vec_vid52_4b.o vec_vid53_4b.o vec_vid54_4b.o vec_vid55_4b.o \
|
||||
vec_vid56_4b.o vec_vid57_4b.o vec_vid58_4b.o vec_vid59_4b.o \
|
||||
vec_vid60_4b.o vec_vid61_4b.o vec_vid62_4b.o vec_vid63_4b.o \
|
||||
vec_vid64_4b.o vec_vid65_4b.o vec_vid66_4b.o vec_vid67_4b.o \
|
||||
vec_vid68_4b.o vec_vid69_4b.o vec_vid70_4b.o vec_vid71_4b.o \
|
||||
vec_vid72_4b.o \
|
||||
excp_isr_ps_nn_4b.o excp_isr_ps_ns_4b.o excp_isr_ps_nr_4b.o \
|
||||
excp_isr_sa_nn_4b.o excp_isr_sa_ns_4b.o excp_isr_sa_nr_4b.o \
|
||||
intr_isr_ps_nn_4b.o intr_isr_ps_ns_4b.o intr_isr_ps_nr_4b.o \
|
||||
intr_isr_sa_nn_4b.o intr_isr_sa_ns_4b.o intr_isr_sa_nr_4b.o \
|
||||
reset_4b.o
|
||||
|
||||
LIBNDS32_ISR_COMMON_OBJS = \
|
||||
LIBNDS32_ISR_JMP_OBJS = \
|
||||
jmptbl_vid00.o jmptbl_vid01.o jmptbl_vid02.o jmptbl_vid03.o \
|
||||
jmptbl_vid04.o jmptbl_vid05.o jmptbl_vid06.o jmptbl_vid07.o \
|
||||
jmptbl_vid08.o jmptbl_vid09.o jmptbl_vid10.o jmptbl_vid11.o \
|
||||
|
|
@ -98,29 +67,32 @@ LIBNDS32_ISR_COMMON_OBJS = \
|
|||
jmptbl_vid60.o jmptbl_vid61.o jmptbl_vid62.o jmptbl_vid63.o \
|
||||
jmptbl_vid64.o jmptbl_vid65.o jmptbl_vid66.o jmptbl_vid67.o \
|
||||
jmptbl_vid68.o jmptbl_vid69.o jmptbl_vid70.o jmptbl_vid71.o \
|
||||
jmptbl_vid72.o \
|
||||
jmptbl_vid72.o
|
||||
|
||||
LIBNDS32_ISR_COMMON_OBJS = \
|
||||
excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \
|
||||
excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \
|
||||
intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \
|
||||
intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \
|
||||
reset.o \
|
||||
nmih.o \
|
||||
wrh.o
|
||||
|
||||
LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_16B_OBJS) $(LIBNDS32_ISR_4B_OBJS) $(LIBNDS32_ISR_COMMON_OBJS)
|
||||
LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_VEC_OBJS) $(LIBNDS32_ISR_JMP_OBJS) $(LIBNDS32_ISR_COMMON_OBJS)
|
||||
|
||||
|
||||
# Build common objects for ISR library
|
||||
nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o
|
||||
|
||||
wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o
|
||||
# Build vector vid objects for ISR library.
|
||||
vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
|
||||
|
||||
|
||||
# Build jump table objects for ISR library.
|
||||
jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
|
||||
|
||||
|
||||
|
||||
# Build 16b version objects for ISR library. (no "_4b" postfix string)
|
||||
vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
|
||||
|
||||
# Build commen objects for ISR library.
|
||||
excp_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nn.o
|
||||
|
||||
|
|
@ -160,48 +132,12 @@ intr_isr_sa_nr.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
|
|||
reset.o: $(srcdir)/config/nds32/isr-library/reset.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset.S -o reset.o
|
||||
|
||||
# Build 4b version objects for ISR library.
|
||||
vec_vid%_4b.o: $(srcdir)/config/nds32/isr-library/vec_vid%_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
|
||||
nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o
|
||||
|
||||
excp_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nn_4b.o
|
||||
wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o
|
||||
|
||||
excp_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_ns_4b.o
|
||||
|
||||
excp_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nr_4b.o
|
||||
|
||||
excp_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nn_4b.o
|
||||
|
||||
excp_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_ns_4b.o
|
||||
|
||||
excp_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nr_4b.o
|
||||
|
||||
intr_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nn_4b.o
|
||||
|
||||
intr_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_ns_4b.o
|
||||
|
||||
intr_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nr_4b.o
|
||||
|
||||
intr_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nn_4b.o
|
||||
|
||||
intr_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_ns_4b.o
|
||||
|
||||
intr_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nr_4b.o
|
||||
|
||||
reset_4b.o: $(srcdir)/config/nds32/isr-library/reset_4b.S
|
||||
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset_4b.S -o reset_4b.o
|
||||
|
||||
|
||||
# The rule to create libnds32_isr.a file
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue