sched: Change return type of predicate functions from int to bool
Also change some internal variables to bool. gcc/ChangeLog: * sched-int.h (struct haifa_sched_info): Change can_schedule_ready_p, scehdule_more_p and contributes_to_priority indirect frunction type from int to bool. (no_real_insns_p): Change return type from int to bool. (contributes_to_priority): Ditto. * haifa-sched.cc (no_real_insns_p): Change return type from int to bool and adjust function body accordingly. * modulo-sched.cc (try_scheduling_node_in_cycle): Change "success" variable type from int to bool. (ps_insn_advance_column): Change return type from int to bool. (ps_has_conflicts): Ditto. Change "has_conflicts" variable type from int to bool. * sched-deps.cc (deps_may_trap_p): Change return type from int to bool. (conditions_mutex_p): Ditto. * sched-ebb.cc (schedule_more_p): Ditto. (ebb_contributes_to_priority): Change return type from int to bool and adjust function body accordingly. * sched-rgn.cc (is_cfg_nonregular): Ditto. (check_live_1): Ditto. (is_pfree): Ditto. (find_conditional_protection): Ditto. (is_conditionally_protected): Ditto. (is_prisky): Ditto. (is_exception_free): Ditto. (haifa_find_rgns): Change "unreachable" and "too_large_failure" variables from int to bool. (extend_rgns): Change "rescan" variable from int to bool. (check_live): Change return type from int to bool and adjust function body accordingly. (can_schedule_ready_p): Ditto. (schedule_more_p): Ditto. (contributes_to_priority): Ditto.
This commit is contained in:
Uros Bizjak
parent
c30efd8cd6
commit
a4778dbd93
6 changed files with 131 additions and 125 deletions
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@ -5033,18 +5033,18 @@ get_ebb_head_tail (basic_block beg, basic_block end,
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*tailp = end_tail;
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}
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/* Return nonzero if there are no real insns in the range [ HEAD, TAIL ]. */
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/* Return true if there are no real insns in the range [ HEAD, TAIL ]. */
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int
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bool
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no_real_insns_p (const rtx_insn *head, const rtx_insn *tail)
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{
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while (head != NEXT_INSN (tail))
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{
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if (!NOTE_P (head) && !LABEL_P (head))
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return 0;
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return false;
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head = NEXT_INSN (head);
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}
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return 1;
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return true;
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}
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/* Restore-other-notes: NOTE_LIST is the end of a chain of notes
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@ -2119,7 +2119,7 @@ try_scheduling_node_in_cycle (partial_schedule_ptr ps,
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sbitmap must_follow)
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{
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ps_insn_ptr psi;
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bool success = 0;
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bool success = false;
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verify_partial_schedule (ps, sched_nodes);
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psi = ps_add_node_check_conflicts (ps, u, cycle, must_precede, must_follow);
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@ -2127,7 +2127,7 @@ try_scheduling_node_in_cycle (partial_schedule_ptr ps,
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{
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SCHED_TIME (u) = cycle;
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bitmap_set_bit (sched_nodes, u);
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success = 1;
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success = true;
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*num_splits = 0;
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if (dump_file)
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fprintf (dump_file, "Scheduled w/o split in %d\n", cycle);
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@ -3067,7 +3067,7 @@ ps_insn_find_column (partial_schedule_ptr ps, ps_insn_ptr ps_i,
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in failure and true in success. Bit N is set in MUST_FOLLOW if
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the node with cuid N must be come after the node pointed to by
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PS_I when scheduled in the same cycle. */
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static int
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static bool
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ps_insn_advance_column (partial_schedule_ptr ps, ps_insn_ptr ps_i,
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sbitmap must_follow)
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{
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@ -3158,7 +3158,7 @@ advance_one_cycle (void)
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/* Checks if PS has resource conflicts according to DFA, starting from
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FROM cycle to TO cycle; returns true if there are conflicts and false
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if there are no conflicts. Assumes DFA is being used. */
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static int
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static bool
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ps_has_conflicts (partial_schedule_ptr ps, int from, int to)
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{
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int cycle;
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@ -3214,7 +3214,8 @@ ps_add_node_check_conflicts (partial_schedule_ptr ps, int n,
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int c, sbitmap must_precede,
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sbitmap must_follow)
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{
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int i, first, amount, has_conflicts = 0;
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int i, first, amount;
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bool has_conflicts = false;
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ps_insn_ptr ps_i;
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/* First add the node to the PS, if this succeeds check for
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@ -472,7 +472,7 @@ static int cache_size;
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/* True if we should mark added dependencies as a non-register deps. */
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static bool mark_as_hard;
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static int deps_may_trap_p (const_rtx);
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static bool deps_may_trap_p (const_rtx);
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static void add_dependence_1 (rtx_insn *, rtx_insn *, enum reg_note);
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static void add_dependence_list (rtx_insn *, rtx_insn_list *, int,
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enum reg_note, bool);
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@ -488,7 +488,7 @@ static void sched_analyze_2 (class deps_desc *, rtx, rtx_insn *);
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static void sched_analyze_insn (class deps_desc *, rtx, rtx_insn *);
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static bool sched_has_condition_p (const rtx_insn *);
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static int conditions_mutex_p (const_rtx, const_rtx, bool, bool);
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static bool conditions_mutex_p (const_rtx, const_rtx, bool, bool);
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static enum DEPS_ADJUST_RESULT maybe_add_or_update_dep_1 (dep_t, bool,
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rtx, rtx);
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@ -497,9 +497,9 @@ static enum DEPS_ADJUST_RESULT add_or_update_dep_1 (dep_t, bool, rtx, rtx);
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static void check_dep (dep_t, bool);
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/* Return nonzero if a load of the memory reference MEM can cause a trap. */
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/* Return true if a load of the memory reference MEM can cause a trap. */
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static int
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static bool
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deps_may_trap_p (const_rtx mem)
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{
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const_rtx addr = XEXP (mem, 0);
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@ -617,8 +617,8 @@ sched_has_condition_p (const rtx_insn *insn)
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/* Return nonzero if conditions COND1 and COND2 can never be both true. */
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static int
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/* Return true if conditions COND1 and COND2 can never be both true. */
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static bool
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conditions_mutex_p (const_rtx cond1, const_rtx cond2, bool rev1, bool rev2)
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{
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if (COMPARISON_P (cond1)
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@ -629,8 +629,8 @@ conditions_mutex_p (const_rtx cond1, const_rtx cond2, bool rev1, bool rev2)
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: GET_CODE (cond2))
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&& rtx_equal_p (XEXP (cond1, 0), XEXP (cond2, 0))
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&& XEXP (cond1, 1) == XEXP (cond2, 1))
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return 1;
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return 0;
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return true;
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return false;
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}
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/* Return true if insn1 and insn2 can never depend on one another because
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@ -51,10 +51,10 @@ static basic_block last_bb;
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/* Implementations of the sched_info functions for region scheduling. */
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static void init_ready_list (void);
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static void begin_schedule_ready (rtx_insn *);
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static int schedule_more_p (void);
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static bool schedule_more_p (void);
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static const char *ebb_print_insn (const rtx_insn *, int);
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static int rank (rtx_insn *, rtx_insn *);
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static int ebb_contributes_to_priority (rtx_insn *, rtx_insn *);
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static bool ebb_contributes_to_priority (rtx_insn *, rtx_insn *);
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static basic_block earliest_block_with_similiar_load (basic_block, rtx);
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static void add_deps_for_risky_insns (rtx_insn *, rtx_insn *);
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static void debug_ebb_dependencies (rtx_insn *, rtx_insn *);
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@ -83,9 +83,9 @@ restore_ebb_state (void *p_)
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free (p_);
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}
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/* Return nonzero if there are more insns that should be scheduled. */
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/* Return true if there are more insns that should be scheduled. */
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static int
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static bool
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schedule_more_p (void)
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{
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return sched_rgn_n_insns < rgn_n_insns;
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@ -238,14 +238,14 @@ rank (rtx_insn *insn1, rtx_insn *insn2)
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}
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/* NEXT is an instruction that depends on INSN (a backward dependence);
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return nonzero if we should include this dependence in priority
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return true if we should include this dependence in priority
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calculations. */
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static int
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static bool
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ebb_contributes_to_priority (rtx_insn *next ATTRIBUTE_UNUSED,
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rtx_insn *insn ATTRIBUTE_UNUSED)
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{
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return 1;
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return true;
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}
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/* INSN is a JUMP_INSN. Store the set of registers that
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@ -585,11 +585,11 @@ struct haifa_sched_info
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/* Add all insns that are initially ready to the ready list. Called once
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before scheduling a set of insns. */
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void (*init_ready_list) (void);
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/* Called after taking an insn from the ready list. Returns nonzero if
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this insn can be scheduled, nonzero if we should silently discard it. */
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int (*can_schedule_ready_p) (rtx_insn *);
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/* Return nonzero if there are more insns that should be scheduled. */
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int (*schedule_more_p) (void);
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/* Called after taking an insn from the ready list. Returns true if
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this insn can be scheduled, false if we should silently discard it. */
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bool (*can_schedule_ready_p) (rtx_insn *);
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/* Return true if there are more insns that should be scheduled. */
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bool (*schedule_more_p) (void);
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/* Called after an insn has all its hard dependencies resolved.
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Adjusts status of instruction (which is passed through second parameter)
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to indicate if instruction should be moved to the ready list or the
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@ -605,9 +605,9 @@ struct haifa_sched_info
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static buffer for this. The ALIGNED parameter should cause the string
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to be formatted so that multiple output lines will line up nicely. */
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const char *(*print_insn) (const rtx_insn *, int);
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/* Return nonzero if an insn should be included in priority
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/* Return true if an insn should be included in priority
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calculations. */
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int (*contributes_to_priority) (rtx_insn *, rtx_insn *);
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bool (*contributes_to_priority) (rtx_insn *, rtx_insn *);
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/* Return true if scheduling insn (passed as the parameter) will trigger
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finish of scheduling current block. */
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@ -1397,7 +1397,7 @@ extern void free_global_sched_pressure_data (void);
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extern int haifa_classify_insn (const_rtx);
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extern void get_ebb_head_tail (basic_block, basic_block,
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rtx_insn **, rtx_insn **);
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extern int no_real_insns_p (const rtx_insn *, const rtx_insn *);
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extern bool no_real_insns_p (const rtx_insn *, const rtx_insn *);
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extern int insn_sched_cost (rtx_insn *);
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extern int dep_cost_1 (dep_t, dw_t);
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@ -1509,7 +1509,7 @@ extern void dump_rgn_dependencies_dot (FILE *);
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extern void dump_rgn_dependencies_dot (const char *);
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extern void free_rgn_deps (void);
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extern int contributes_to_priority (rtx_insn *, rtx_insn *);
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extern bool contributes_to_priority (rtx_insn *, rtx_insn *);
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extern void extend_rgns (int *, int *, sbitmap, int *);
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extern void deps_join (class deps_desc *, class deps_desc *);
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189
gcc/sched-rgn.cc
189
gcc/sched-rgn.cc
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@ -82,7 +82,7 @@ along with GCC; see the file COPYING3. If not see
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/* nr_inter/spec counts interblock/speculative motion for the function. */
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static int nr_inter, nr_spec;
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static int is_cfg_nonregular (void);
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static bool is_cfg_nonregular (void);
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/* Number of regions in the procedure. */
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int nr_regions = 0;
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@ -231,13 +231,13 @@ static edgeset *ancestor_edges;
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#define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (BLOCK_NUM (INSN))))
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/* Speculative scheduling functions. */
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static int check_live_1 (int, rtx);
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static bool check_live_1 (int, rtx);
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static void update_live_1 (int, rtx);
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static int is_pfree (rtx, int, int);
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static int find_conditional_protection (rtx_insn *, int);
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static int is_conditionally_protected (rtx, int, int);
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static int is_prisky (rtx, int, int);
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static int is_exception_free (rtx_insn *, int, int);
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static bool is_pfree (rtx, int, int);
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static bool find_conditional_protection (rtx_insn *, int);
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static bool is_conditionally_protected (rtx, int, int);
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static bool is_prisky (rtx, int, int);
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static bool is_exception_free (rtx_insn *, int, int);
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static bool sets_likely_spilled (rtx);
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static void sets_likely_spilled_1 (rtx, const_rtx, void *);
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@ -252,13 +252,14 @@ static void free_pending_lists (void);
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/* Functions for construction of the control flow graph. */
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/* Return 1 if control flow graph should not be constructed, 0 otherwise.
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/* Return true if control flow graph should not be constructed,
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false otherwise.
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We decide not to build the control flow graph if there is possibly more
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than one entry to the function, if computed branches exist, if we
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have nonlocal gotos, or if we have an unreachable loop. */
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static int
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static bool
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is_cfg_nonregular (void)
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{
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basic_block b;
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@ -267,17 +268,17 @@ is_cfg_nonregular (void)
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/* If we have a label that could be the target of a nonlocal goto, then
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the cfg is not well structured. */
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if (nonlocal_goto_handler_labels)
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return 1;
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return true;
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/* If we have any forced labels, then the cfg is not well structured. */
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if (forced_labels)
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return 1;
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return true;
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/* If we have exception handlers, then we consider the cfg not well
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structured. ?!? We should be able to handle this now that we
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compute an accurate cfg for EH. */
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if (current_function_has_exception_handlers ())
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return 1;
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return true;
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/* If we have insns which refer to labels as non-jumped-to operands,
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then we consider the cfg not well structured. */
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@ -290,7 +291,7 @@ is_cfg_nonregular (void)
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/* If this function has a computed jump, then we consider the cfg
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not well structured. */
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if (JUMP_P (insn) && computed_jump_p (insn))
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return 1;
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return true;
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if (!INSN_P (insn))
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continue;
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@ -310,15 +311,15 @@ is_cfg_nonregular (void)
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&& find_reg_note (next, REG_LABEL_TARGET,
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XEXP (note, 0)) == NULL_RTX)
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|| BLOCK_FOR_INSN (insn) != BLOCK_FOR_INSN (next))
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return 1;
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return true;
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set = single_set (insn);
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if (set == NULL_RTX)
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return 1;
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return true;
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dest = SET_DEST (set);
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if (!REG_P (dest) || !dead_or_set_p (next, dest))
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return 1;
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return true;
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}
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/* Unreachable loops with more than one basic block are detected
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@ -332,11 +333,11 @@ is_cfg_nonregular (void)
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if (EDGE_COUNT (b->preds) == 0
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|| (single_pred_p (b)
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&& single_pred (b) == b))
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return 1;
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return true;
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}
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/* All the tests passed. Consider the cfg well structured. */
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return 0;
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return false;
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}
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/* Extract list of edges from a bitmap containing EDGE_TO_BIT bits. */
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@ -627,8 +628,9 @@ haifa_find_rgns (void)
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int count = 0, sp, idx = 0;
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edge_iterator current_edge;
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edge_iterator *stack;
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int num_bbs, num_insns, unreachable;
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int too_large_failure;
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int num_bbs, num_insns;
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bool unreachable;
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bool too_large_failure;
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basic_block bb;
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/* Perform a DFS traversal of the cfg. Identify loop headers, inner loops
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@ -764,11 +766,11 @@ haifa_find_rgns (void)
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The DFS traversal will mark every block that is reachable from
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the entry node by placing a nonzero value in dfs_nr. Thus if
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dfs_nr is zero for any block, then it must be unreachable. */
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unreachable = 0;
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unreachable = false;
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FOR_EACH_BB_FN (bb, cfun)
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if (dfs_nr[bb->index] == 0)
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{
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unreachable = 1;
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unreachable = true;
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break;
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}
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@ -851,7 +853,7 @@ haifa_find_rgns (void)
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/* I is a header of an inner loop, or block 0 in a subroutine
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with no loops at all. */
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head = tail = -1;
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too_large_failure = 0;
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too_large_failure = false;
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loop_head = max_hdr[bb->index];
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if (extend_regions_p)
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@ -888,7 +890,7 @@ haifa_find_rgns (void)
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if (too_large (jbb->index, &num_bbs, &num_insns))
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{
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too_large_failure = 1;
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too_large_failure = true;
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break;
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}
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}
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@ -912,7 +914,7 @@ haifa_find_rgns (void)
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if (too_large (node, &num_bbs, &num_insns))
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{
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too_large_failure = 1;
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too_large_failure = true;
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break;
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}
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}
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@ -974,7 +976,7 @@ haifa_find_rgns (void)
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if (too_large (node, &num_bbs, &num_insns))
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{
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too_large_failure = 1;
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too_large_failure = true;
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break;
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}
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}
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@ -1157,8 +1159,9 @@ print_region_statistics (int *s1, int s1_sz, int *s2, int s2_sz)
|
|||
void
|
||||
extend_rgns (int *degree, int *idxp, sbitmap header, int *loop_hdr)
|
||||
{
|
||||
int *order, i, rescan = 0, idx = *idxp, iter = 0, max_iter, *max_hdr;
|
||||
int *order, i, idx = *idxp, iter = 0, max_iter, *max_hdr;
|
||||
int nblocks = n_basic_blocks_for_fn (cfun) - NUM_FIXED_BLOCKS;
|
||||
bool rescan = false;
|
||||
|
||||
max_iter = param_max_sched_extend_regions_iters;
|
||||
|
||||
|
|
@ -1173,7 +1176,7 @@ extend_rgns (int *degree, int *idxp, sbitmap header, int *loop_hdr)
|
|||
if (degree[bbn] >= 0)
|
||||
{
|
||||
max_hdr[bbn] = bbn;
|
||||
rescan = 1;
|
||||
rescan = true;
|
||||
}
|
||||
else
|
||||
/* This block already was processed in find_rgns. */
|
||||
|
|
@ -1193,7 +1196,7 @@ extend_rgns (int *degree, int *idxp, sbitmap header, int *loop_hdr)
|
|||
|
||||
while (rescan && iter < max_iter)
|
||||
{
|
||||
rescan = 0;
|
||||
rescan = false;
|
||||
|
||||
for (i = nblocks - 1; i >= 0; i--)
|
||||
{
|
||||
|
|
@ -1241,7 +1244,7 @@ extend_rgns (int *degree, int *idxp, sbitmap header, int *loop_hdr)
|
|||
/* If BB start its own region,
|
||||
update set of headers with BB. */
|
||||
bitmap_set_bit (header, bbn);
|
||||
rescan = 1;
|
||||
rescan = true;
|
||||
}
|
||||
else
|
||||
gcc_assert (hdr != -1);
|
||||
|
|
@ -1658,10 +1661,10 @@ debug_candidates (int trg)
|
|||
|
||||
static bitmap_head not_in_df;
|
||||
|
||||
/* Return 0 if x is a set of a register alive in the beginning of one
|
||||
of the split-blocks of src, otherwise return 1. */
|
||||
/* Return false if x is a set of a register alive in the beginning of one
|
||||
of the split-blocks of src, otherwise return true. */
|
||||
|
||||
static int
|
||||
static bool
|
||||
check_live_1 (int src, rtx x)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1669,7 +1672,7 @@ check_live_1 (int src, rtx x)
|
|||
rtx reg = SET_DEST (x);
|
||||
|
||||
if (reg == 0)
|
||||
return 1;
|
||||
return true;
|
||||
|
||||
while (GET_CODE (reg) == SUBREG
|
||||
|| GET_CODE (reg) == ZERO_EXTRACT
|
||||
|
|
@ -1683,20 +1686,20 @@ check_live_1 (int src, rtx x)
|
|||
for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
|
||||
if (XEXP (XVECEXP (reg, 0, i), 0) != 0)
|
||||
if (check_live_1 (src, XEXP (XVECEXP (reg, 0, i), 0)))
|
||||
return 1;
|
||||
return true;
|
||||
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!REG_P (reg))
|
||||
return 1;
|
||||
return true;
|
||||
|
||||
regno = REGNO (reg);
|
||||
|
||||
if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
|
||||
{
|
||||
/* Global registers are assumed live. */
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1717,7 +1720,7 @@ check_live_1 (int src, rtx x)
|
|||
!= CONTAINING_RGN (BB_TO_BLOCK (src))));
|
||||
|
||||
if (t || REGNO_REG_SET_P (df_get_live_in (b), regno + j))
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1733,12 +1736,12 @@ check_live_1 (int src, rtx x)
|
|||
!= CONTAINING_RGN (BB_TO_BLOCK (src))));
|
||||
|
||||
if (t || REGNO_REG_SET_P (df_get_live_in (b), regno))
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
/* If x is a set of a register R, mark that R is alive in the beginning
|
||||
|
|
@ -1789,11 +1792,11 @@ update_live_1 (int src, rtx x)
|
|||
}
|
||||
}
|
||||
|
||||
/* Return 1 if insn can be speculatively moved from block src to trg,
|
||||
otherwise return 0. Called before first insertion of insn to
|
||||
/* Return true if insn can be speculatively moved from block src to trg,
|
||||
otherwise return false. Called before first insertion of insn to
|
||||
ready-list or before the scheduling. */
|
||||
|
||||
static int
|
||||
static bool
|
||||
check_live (rtx_insn *insn, int src)
|
||||
{
|
||||
/* Find the registers set by instruction. */
|
||||
|
|
@ -1807,12 +1810,12 @@ check_live (rtx_insn *insn, int src)
|
|||
if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
|
||||
|| GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
|
||||
&& !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j)))
|
||||
return 0;
|
||||
return false;
|
||||
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Update the live registers info after insn was moved speculatively from
|
||||
|
|
@ -1835,13 +1838,15 @@ update_live (rtx_insn *insn, int src)
|
|||
}
|
||||
}
|
||||
|
||||
/* Nonzero if block bb_to is equal to, or reachable from block bb_from. */
|
||||
/* True if block bb_to is equal to, or reachable from block bb_from. */
|
||||
#define IS_REACHABLE(bb_from, bb_to) \
|
||||
(bb_from == bb_to \
|
||||
|| IS_RGN_ENTRY (bb_from) \
|
||||
|| (bitmap_bit_p (ancestor_edges[bb_to], \
|
||||
EDGE_TO_BIT (single_pred_edge (BASIC_BLOCK_FOR_FN (cfun, \
|
||||
BB_TO_BLOCK (bb_from)))))))
|
||||
|| (bitmap_bit_p \
|
||||
(ancestor_edges[bb_to], \
|
||||
EDGE_TO_BIT (single_pred_edge \
|
||||
(BASIC_BLOCK_FOR_FN (cfun, \
|
||||
BB_TO_BLOCK (bb_from)))))))
|
||||
|
||||
/* Turns on the fed_by_spec_load flag for insns fed by load_insn. */
|
||||
|
||||
|
|
@ -1857,9 +1862,9 @@ set_spec_fed (rtx load_insn)
|
|||
}
|
||||
|
||||
/* On the path from the insn to load_insn_bb, find a conditional
|
||||
branch depending on insn, that guards the speculative load. */
|
||||
branch depending on insn, that guards the speculative load. */
|
||||
|
||||
static int
|
||||
static bool
|
||||
find_conditional_protection (rtx_insn *insn, int load_insn_bb)
|
||||
{
|
||||
sd_iterator_def sd_it;
|
||||
|
|
@ -1877,12 +1882,12 @@ find_conditional_protection (rtx_insn *insn, int load_insn_bb)
|
|||
&& DEP_TYPE (dep) == REG_DEP_TRUE
|
||||
&& (JUMP_P (next)
|
||||
|| find_conditional_protection (next, load_insn_bb)))
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
return 0;
|
||||
return false;
|
||||
} /* find_conditional_protection */
|
||||
|
||||
/* Returns 1 if the same insn1 that participates in the computation
|
||||
/* Returns true if the same insn1 that participates in the computation
|
||||
of load_insn's address is feeding a conditional branch that is
|
||||
guarding on load_insn. This is true if we find two DEF-USE
|
||||
chains:
|
||||
|
|
@ -1896,7 +1901,7 @@ find_conditional_protection (rtx_insn *insn, int load_insn_bb)
|
|||
Locate insn1 by climbing on INSN_BACK_DEPS from load_insn.
|
||||
Locate the branch by following INSN_FORW_DEPS from insn1. */
|
||||
|
||||
static int
|
||||
static bool
|
||||
is_conditionally_protected (rtx load_insn, int bb_src, int bb_trg)
|
||||
{
|
||||
sd_iterator_def sd_it;
|
||||
|
|
@ -1921,17 +1926,17 @@ is_conditionally_protected (rtx load_insn, int bb_src, int bb_trg)
|
|||
|
||||
/* Now search for the conditional-branch. */
|
||||
if (find_conditional_protection (insn1, bb_src))
|
||||
return 1;
|
||||
return true;
|
||||
|
||||
/* Recursive step: search another insn1, "above" current insn1. */
|
||||
return is_conditionally_protected (insn1, bb_src, bb_trg);
|
||||
}
|
||||
|
||||
/* The chain does not exist. */
|
||||
return 0;
|
||||
return false;
|
||||
} /* is_conditionally_protected */
|
||||
|
||||
/* Returns 1 if a clue for "similar load" 'insn2' is found, and hence
|
||||
/* Returns true if a clue for "similar load" 'insn2' is found, and hence
|
||||
load_insn can move speculatively from bb_src to bb_trg. All the
|
||||
following must hold:
|
||||
|
||||
|
|
@ -1947,7 +1952,7 @@ is_conditionally_protected (rtx load_insn, int bb_src, int bb_trg)
|
|||
load_insn would cause an exception, it would have been caused by
|
||||
load2 anyhow. */
|
||||
|
||||
static int
|
||||
static bool
|
||||
is_pfree (rtx load_insn, int bb_src, int bb_trg)
|
||||
{
|
||||
sd_iterator_def back_sd_it;
|
||||
|
|
@ -1956,7 +1961,7 @@ is_pfree (rtx load_insn, int bb_src, int bb_trg)
|
|||
|
||||
if (candp->split_bbs.nr_members != 1)
|
||||
/* Must have exactly one escape block. */
|
||||
return 0;
|
||||
return false;
|
||||
|
||||
FOR_EACH_DEP (load_insn, SD_LIST_BACK, back_sd_it, back_dep)
|
||||
{
|
||||
|
|
@ -1981,45 +1986,45 @@ is_pfree (rtx load_insn, int bb_src, int bb_trg)
|
|||
|
||||
if (INSN_BB (insn2) == bb_trg)
|
||||
/* insn2 is the similar load, in the target block. */
|
||||
return 1;
|
||||
return true;
|
||||
|
||||
if (*(candp->split_bbs.first_member) == BLOCK_FOR_INSN (insn2))
|
||||
/* insn2 is a similar load, in a split-block. */
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Couldn't find a similar load. */
|
||||
return 0;
|
||||
return false;
|
||||
} /* is_pfree */
|
||||
|
||||
/* Return 1 if load_insn is prisky (i.e. if load_insn is fed by
|
||||
/* Return true if load_insn is prisky (i.e. if load_insn is fed by
|
||||
a load moved speculatively, or if load_insn is protected by
|
||||
a compare on load_insn's address). */
|
||||
|
||||
static int
|
||||
static bool
|
||||
is_prisky (rtx load_insn, int bb_src, int bb_trg)
|
||||
{
|
||||
if (FED_BY_SPEC_LOAD (load_insn))
|
||||
return 1;
|
||||
return true;
|
||||
|
||||
if (sd_lists_empty_p (load_insn, SD_LIST_BACK))
|
||||
/* Dependence may 'hide' out of the region. */
|
||||
return 1;
|
||||
return true;
|
||||
|
||||
if (is_conditionally_protected (load_insn, bb_src, bb_trg))
|
||||
return 1;
|
||||
return true;
|
||||
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Insn is a candidate to be moved speculatively from bb_src to bb_trg.
|
||||
Return 1 if insn is exception-free (and the motion is valid)
|
||||
and 0 otherwise. */
|
||||
Return true if insn is exception-free (and the motion is valid)
|
||||
and false otherwise. */
|
||||
|
||||
static int
|
||||
static bool
|
||||
is_exception_free (rtx_insn *insn, int bb_src, int bb_trg)
|
||||
{
|
||||
int insn_class = haifa_classify_insn (insn);
|
||||
|
|
@ -2028,31 +2033,31 @@ is_exception_free (rtx_insn *insn, int bb_src, int bb_trg)
|
|||
switch (insn_class)
|
||||
{
|
||||
case TRAP_FREE:
|
||||
return 1;
|
||||
return true;
|
||||
case TRAP_RISKY:
|
||||
return 0;
|
||||
return false;
|
||||
default:;
|
||||
}
|
||||
|
||||
/* Handle loads. */
|
||||
if (!flag_schedule_speculative_load)
|
||||
return 0;
|
||||
return false;
|
||||
IS_LOAD_INSN (insn) = 1;
|
||||
switch (insn_class)
|
||||
{
|
||||
case IFREE:
|
||||
return (1);
|
||||
return true;
|
||||
case IRISKY:
|
||||
return 0;
|
||||
return false;
|
||||
case PFREE_CANDIDATE:
|
||||
if (is_pfree (insn, bb_src, bb_trg))
|
||||
return 1;
|
||||
return true;
|
||||
/* Don't 'break' here: PFREE-candidate is also PRISKY-candidate. */
|
||||
/* FALLTHRU */
|
||||
case PRISKY_CANDIDATE:
|
||||
if (!flag_schedule_speculative_load_dangerous
|
||||
|| is_prisky (insn, bb_src, bb_trg))
|
||||
return 0;
|
||||
return false;
|
||||
break;
|
||||
default:;
|
||||
}
|
||||
|
|
@ -2069,10 +2074,10 @@ static int sched_n_insns;
|
|||
|
||||
/* Implementations of the sched_info functions for region scheduling. */
|
||||
static void init_ready_list (void);
|
||||
static int can_schedule_ready_p (rtx_insn *);
|
||||
static bool can_schedule_ready_p (rtx_insn *);
|
||||
static void begin_schedule_ready (rtx_insn *);
|
||||
static ds_t new_ready (rtx_insn *, ds_t);
|
||||
static int schedule_more_p (void);
|
||||
static bool schedule_more_p (void);
|
||||
static const char *rgn_print_insn (const rtx_insn *, int);
|
||||
static int rgn_rank (rtx_insn *, rtx_insn *);
|
||||
static void compute_jump_reg_dependencies (rtx, regset);
|
||||
|
|
@ -2083,9 +2088,9 @@ static void rgn_add_block (basic_block, basic_block);
|
|||
static void rgn_fix_recovery_cfg (int, int, int);
|
||||
static basic_block advance_target_bb (basic_block, rtx_insn *);
|
||||
|
||||
/* Return nonzero if there are more insns that should be scheduled. */
|
||||
/* Return true if there are more insns that should be scheduled. */
|
||||
|
||||
static int
|
||||
static bool
|
||||
schedule_more_p (void)
|
||||
{
|
||||
return sched_target_n_insns < target_n_insns;
|
||||
|
|
@ -2151,10 +2156,10 @@ init_ready_list (void)
|
|||
}
|
||||
}
|
||||
|
||||
/* Called after taking INSN from the ready list. Returns nonzero if this
|
||||
/* Called after taking INSN from the ready list. Returns true if this
|
||||
insn can be scheduled, nonzero if we should silently discard it. */
|
||||
|
||||
static int
|
||||
static bool
|
||||
can_schedule_ready_p (rtx_insn *insn)
|
||||
{
|
||||
/* An interblock motion? */
|
||||
|
|
@ -2162,15 +2167,15 @@ can_schedule_ready_p (rtx_insn *insn)
|
|||
{
|
||||
/* Cannot schedule this insn unless all operands are live. */
|
||||
if (!check_live (insn, INSN_BB (insn)))
|
||||
return 0;
|
||||
return false;
|
||||
|
||||
/* Should not move expensive instructions speculatively. */
|
||||
if (GET_CODE (PATTERN (insn)) != CLOBBER
|
||||
&& !targetm.sched.can_speculate_insn (insn))
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Updates counter and other information. Split from can_schedule_ready_p ()
|
||||
|
|
@ -2311,10 +2316,10 @@ rgn_rank (rtx_insn *insn1, rtx_insn *insn2)
|
|||
}
|
||||
|
||||
/* NEXT is an instruction that depends on INSN (a backward dependence);
|
||||
return nonzero if we should include this dependence in priority
|
||||
return true if we should include this dependence in priority
|
||||
calculations. */
|
||||
|
||||
int
|
||||
bool
|
||||
contributes_to_priority (rtx_insn *next, rtx_insn *insn)
|
||||
{
|
||||
/* NEXT and INSN reside in one ebb. */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue