procyberian/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

re PR target/67967 (ICE in i386_pe_seh_unwind_emit)

Browse source 
PR target/67967
	* config/i386/i386.c (ix86_emit_save_reg_using_mov): Do not add
	REG_CFA_EXPRESSION to aligned SSE stores.

From-SVN: r228826
This commit is contained in:
Uros Bizjak 2015-10-14 23:18:19 +02:00 • committed by Uros Bizjak
parent 3837c6d66f
commit a409ca75d6
2 changed files with 10 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
gcc/ChangeLog
View file

@ -1,3 +1,9 @@
2015-10-14 Uros Bizjak <ubizjak@gmail.com>
PR target/67967
* config/i386/i386.c (ix86_emit_save_reg_using_mov): Do not add
REG_CFA_EXPRESSION to aligned SSE stores.
2015-10-14 Jeff Law <law@redhat.com>
* tree-ssa-threadupdate.c (thread_through_all_blocks): Bump

11
gcc/config/i386/i386.c
View file

@ -11612,6 +11612,7 @@ ix86_emit_save_reg_using_mov (machine_mode mode, unsigned int regno,
{
struct machine_function *m = cfun->machine;
rtx reg = gen_rtx_REG (mode, regno);
rtx unspec = NULL_RTX;
rtx mem, addr, base, insn;
unsigned int align;
@ -11626,13 +11627,9 @@ ix86_emit_save_reg_using_mov (machine_mode mode, unsigned int regno,
In case INCOMING_STACK_BOUNDARY is misaligned, we have
to emit unaligned store. */
if (mode == V4SFmode && align < 128)
{
rtx unspec = gen_rtx_UNSPEC (mode, gen_rtvec (1, reg), UNSPEC_STOREU);
insn = emit_insn (gen_rtx_SET (mem, unspec));
}
else
insn = emit_insn (gen_rtx_SET (mem, reg));
unspec = gen_rtx_UNSPEC (mode, gen_rtvec (1, reg), UNSPEC_STOREU);
insn = emit_insn (gen_rtx_SET (mem, unspec ? unspec : reg));
RTX_FRAME_RELATED_P (insn) = 1;
base = addr;
@ -11679,7 +11676,7 @@ ix86_emit_save_reg_using_mov (machine_mode mode, unsigned int regno,
mem = gen_rtx_MEM (mode, addr);
add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, reg));
}
else
else if (unspec)
add_reg_note (insn, REG_CFA_EXPRESSION, gen_rtx_SET (mem, reg));
}