re PR target/66217 (PowerPC rotate/shift/mask instructions not optimal)
PR target/66217 * config/rs6000/rs6000-protos.h (rs6000_emit_2insn_and): Change prototype. * config/rs6000/rs6000.c (rs6000_emit_dot_insn): New function. (rs6000_emit_2insn_and): Handle dot forms. * config/rs6000/rs6000.md (and<mode>3): Adjust. (*and<mode>3_2insn): Remove TODO. Adjust. Add "type" attr. (*and<mode>3_2insn_dot, *and<mode>3_2insn_dot2): New. From-SVN: r226112
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
d057c8669b
commit
a34f4f6468
4 changed files with 109 additions and 15 deletions
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@ -1,3 +1,14 @@
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2015-07-23 Segher Boessenkool <segher@kernel.crashing.org>
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PR target/66217
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* config/rs6000/rs6000-protos.h (rs6000_emit_2insn_and): Change
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prototype.
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* config/rs6000/rs6000.c (rs6000_emit_dot_insn): New function.
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(rs6000_emit_2insn_and): Handle dot forms.
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* config/rs6000/rs6000.md (and<mode>3): Adjust.
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(*and<mode>3_2insn): Remove TODO. Adjust. Add "type" attr.
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(*and<mode>3_2insn_dot, *and<mode>3_2insn_dot2): New.
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2015-07-23 Richard Biener <rguenther@suse.de>
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* generic-match-head.c: Include cgraph.h.
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@ -77,7 +77,7 @@ extern const char *rs6000_insn_for_and_mask (machine_mode, rtx *, bool);
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extern const char *rs6000_insn_for_shift_mask (machine_mode, rtx *, bool);
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extern const char *rs6000_insn_for_insert_mask (machine_mode, rtx *, bool);
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extern bool rs6000_is_valid_2insn_and (rtx, machine_mode);
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extern void rs6000_emit_2insn_and (machine_mode, rtx *, bool, bool);
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extern void rs6000_emit_2insn_and (machine_mode, rtx *, bool, int);
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extern int registers_ok_for_quad_peep (rtx, rtx);
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extern int mems_ok_for_quad_peep (rtx, rtx);
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extern bool gpr_or_gpr_p (rtx, rtx);
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@ -16735,20 +16735,54 @@ rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
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return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
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}
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/* Emit a potentially record-form instruction, setting DST from SRC.
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If DOT is 0, that is all; otherwise, set CCREG to the result of the
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signed comparison of DST with zero. If DOT is 1, the generated RTL
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doesn't care about the DST result; if DOT is 2, it does. If CCREG
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is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
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a separate COMPARE. */
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static void
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rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
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{
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if (dot == 0)
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{
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emit_move_insn (dst, src);
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return;
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}
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if (cc_reg_not_cr0_operand (ccreg, CCmode))
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{
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emit_move_insn (dst, src);
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emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
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return;
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}
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rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
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if (dot == 1)
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{
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rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
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emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
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}
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else
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{
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rtx set = gen_rtx_SET (dst, src);
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emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
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}
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}
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/* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
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If EXPAND is true, split rotate-and-mask instructions we generate to
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their constituent parts as well (this is used during expand); if DOT
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is true, make the last insn a record-form instruction. */
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is 1, make the last insn a record-form instruction clobbering the
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destination GPR and setting the CC reg (from operands[3]); if 2, set
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that GPR as well as the CC reg. */
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void
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rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, bool dot)
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rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
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{
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gcc_assert (!(expand && dot));
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/* We do not actually handle record form yet. */
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if (dot)
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gcc_unreachable ();
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unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
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/* If it is one stretch of ones, it is DImode; shift left, mask, then
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@ -16773,7 +16807,8 @@ rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, bool dot)
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rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
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tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
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emit_move_insn (operands[0], tmp);
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emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (shift)));
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tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
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rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
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}
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return;
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}
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@ -16799,7 +16834,7 @@ rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, bool dot)
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rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
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emit_move_insn (reg, tmp);
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tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
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emit_move_insn (operands[0], tmp);
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rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
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return;
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}
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@ -16816,7 +16851,7 @@ rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, bool dot)
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rtx reg_low = gen_lowpart (SImode, reg);
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emit_move_insn (reg_low, tmp);
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tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
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emit_move_insn (operands[0], tmp);
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rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
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return;
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}
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@ -16845,7 +16880,7 @@ rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, bool dot)
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emit_move_insn (operands[0], tmp);
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tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
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tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
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emit_move_insn (operands[0], tmp);
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rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
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}
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}
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@ -2913,7 +2913,7 @@
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if (rs6000_is_valid_2insn_and (operands[2], <MODE>mode))
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{
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rs6000_emit_2insn_and (<MODE>mode, operands, true, false);
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rs6000_emit_2insn_and (<MODE>mode, operands, true, 0);
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DONE;
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}
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@ -3139,7 +3139,6 @@
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(set_attr "length" "4,8")])
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; TODO: dots of this
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(define_insn_and_split "*and<mode>3_2insn"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
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@ -3152,10 +3151,59 @@
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"&& 1"
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[(pc)]
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{
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rs6000_emit_2insn_and (<MODE>mode, operands, false, false);
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rs6000_emit_2insn_and (<MODE>mode, operands, false, 0);
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DONE;
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}
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[(set_attr "length" "8")])
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[(set_attr "type" "shift")
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(set_attr "length" "8")])
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(define_insn_and_split "*and<mode>3_2insn_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
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(match_operand:GPR 2 "const_int_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
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&& rs6000_gen_cell_microcode
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&& rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
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&& !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
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|| (logical_const_operand (operands[2], <MODE>mode)
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&& rs6000_gen_cell_microcode))"
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"#"
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"&& reload_completed"
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[(pc)]
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{
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rs6000_emit_2insn_and (<MODE>mode, operands, false, 1);
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DONE;
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}
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")
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(set_attr "length" "8,12")])
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(define_insn_and_split "*and<mode>3_2insn_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
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(match_operand:GPR 2 "const_int_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(and:GPR (match_dup 1)
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(match_dup 2)))]
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"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
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&& rs6000_gen_cell_microcode
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&& rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
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&& !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
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|| (logical_const_operand (operands[2], <MODE>mode)
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&& rs6000_gen_cell_microcode))"
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"#"
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"&& reload_completed"
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[(pc)]
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{
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rs6000_emit_2insn_and (<MODE>mode, operands, false, 2);
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DONE;
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}
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")
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(set_attr "length" "8,12")])
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(define_expand "<code><mode>3"
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