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RISC-V: Fix register class subset checks for CLASS_MAX_NREGS

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Fix the register class subset checks in the determination of the maximum
number of consecutive registers needed to hold a value of a given mode.

The number depends on whether a register is a general-purpose or a
floating-point register, so check whether the register class requested
is a subset (argument 1 to `reg_class_subset_p') rather than superset
(argument 2) of GR_REGS or FP_REGS class respectively.

	gcc/
	* config/riscv/riscv.c (riscv_class_max_nregs): Swap the
	arguments to `reg_class_subset_p'.
This commit is contained in:
Maciej W. Rozycki 2021-11-03 17:04:19 +00:00
parent 1e7a269856
commit a31056e919
1 changed files with 2 additions and 2 deletions
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4
gcc/config/riscv/riscv.c
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@ -4810,10 +4810,10 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
static unsigned char
riscv_class_max_nregs (reg_class_t rclass, machine_mode mode)
{
if (reg_class_subset_p (FP_REGS, rclass))
if (reg_class_subset_p (rclass, FP_REGS))
return riscv_hard_regno_nregs (FP_REG_FIRST, mode);
if (reg_class_subset_p (GR_REGS, rclass))
if (reg_class_subset_p (rclass, GR_REGS))
return riscv_hard_regno_nregs (GP_REG_FIRST, mode);
return 0;