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RISC-V: Add Zawrs ISA extension support

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This patch adds support for the Zawrs ISA extension.
Zawrs has been ratified by the RISC-V BoD on Oct 20th, 2022.

Binutils support has been merged as:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=eb668e50036e979fb0a74821df4eee0307b44e66

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add zawrs extension.
	* config/riscv/riscv-opts.h (MASK_ZAWRS): New.
	(TARGET_ZAWRS): New.
	* config/riscv/riscv.opt: New.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zawrs.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner 2022-10-27 20:42:30 +02:00 • committed by Philipp Tomsich
parent abaa32c738
commit a1a6b912b5
4 changed files with 23 additions and 0 deletions
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4
gcc/common/config/riscv/riscv-common.cc
View file

@ -163,6 +163,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
@ -1180,6 +1182,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
{"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
{"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
{"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA},
{"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB},
{"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC},

3
gcc/config/riscv/riscv-opts.h
View file

@ -73,6 +73,9 @@ enum stack_protector_guard {
#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
#define MASK_ZAWRS (1 << 0)
#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
#define MASK_ZBA (1 << 0)
#define MASK_ZBB (1 << 1)
#define MASK_ZBC (1 << 2)

3
gcc/config/riscv/riscv.opt
View file

@ -203,6 +203,9 @@ long riscv_stack_protector_guard_offset = 0
TargetVariable
int riscv_zi_subext
TargetVariable
int riscv_za_subext
TargetVariable
int riscv_zb_subext

13
gcc/testsuite/gcc.target/riscv/zawrs.c Normal file
View file

@ -0,0 +1,13 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gc_zawrs" { target { rv64 } } } */
/* { dg-options "-march=rv32gc_zawrs" { target { rv32 } } } */
#ifndef __riscv_zawrs
#error Feature macro not defined
#endif
int
foo (int a)
{
return a;
}