sparc.h (SPARC_V9,SPARC_ARCH64): Delete.
* sparc/sparc.h (SPARC_V9,SPARC_ARCH64): Delete.
(DEFAULT_ARCH32_P): New macro.
(TARGET_ARCH{32,64}): Allow compile time or runtime selection.
(enum cmodel): Declare.
(sparc_cmodel_string,sparc_cmodel): Declare.
(SPARC_DEFAULT_CMODEL): Provide default.
(TARGET_{MEDLOW,MEDANY}): Renamed to TARGET_CM_{MEDLOW,MEDANY}.
(TARGET_FULLANY): Deleted.
(TARGET_CM_MEDMID): New macro.
(CPP_CPU_DEFAULT_SPEC): Renamed from CPP_DEFAULT_SPEC.
(ASM_CPU_DEFAULT_SPEC): Renamed from ASM_DEFAULT_SPEC.
(CPP_PREDEFINES): Take out stuff now handled by %(cpp_arch).
(CPP_SPEC): Rewrite.
(CPP_ARCH{,32,64,_DEFAULT}_SPEC): New macros.
(CPP_{ENDIAN,SUBTARGET}_SPEC): New macros.
(ASM_ARCH{,32,64,_DEFAULT}_SPEC): New macros.
(ASM_SPEC): Add %(asm_arch).
(EXTRA_SPECS): Rename cpp_default to cpp_cpu_default.
Rename asm_default to asm_cpu_default.
Add cpp_arch32, cpp_arch64, cpp_arch_default, cpp_arch, cpp_endian,
cpp_subtarget, asm_arch32, asm_arch64, asm_arch_default, asm_arch.
(NO_BUILTIN_{PTRDIFF,SIZE}_TYPE): Define ifdef SPARC_BI_ARCH.
({PTRDIFF,SIZE}_TYPE): Provide 32 and 64 bit values.
(MASK_INT64,MASK_LONG64): Delete.
(MASK_ARCH64): Renamed to MASK_64BIT.
(MASK_{MEDLOW,MEDANY,FULLANY,CODE_MODEL}): Delete.
(EMBMEDANY_BASE_REG): Renamed from MEDANY_BASE_REG.
(TARGET_SWITCHES): Always provide 64 bit options.
(ARCH64_SWITCHES): Delete.
(TARGET_OPTIONS): New option -mcmodel=.
(INT_TYPE_SIZE): Always 32.
(MAX_LONG_TYPE_SIZE): Define ifdef SPARC_BI_ARCH.
(INIT_EXPANDERS): sparc64_init_expanders renamed to sparc_init_....
(FUNCTION_{,BLOCK_}PROFILER): Delete TARGET_EMBMEDANY support.
(PRINT_OPERAND_PUNCT_VALID_P): Add '_'.
* sparc/linux-aout.h (CPP_PREDEFINES): Take out stuff handled by
CPP_SPEC.
(CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC.
* sparc/linux.h: Likewise.
* sparc/linux64.h (SPARC_V9,SPARC_ARCH64): Delete.
(ASM_CPU_DEFAULT_SPEC): Renamed from ASM_DEFAULT_SPEC.
(TARGET_DEFAULT): Delete MASK_LONG64, MASK_MEDANY, add MASK_64BIT.
(SPARC_DEFAULT_CMODEL): Define.
(CPP_PREDEFINES): Take out stuff handled by CPP_SPEC.
(CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC.
(LONG_DOUBLE_TYPE_SIZE): Define.
(ASM_SPEC): Add %(asm_arch).
* sparc/sol2.h (CPP_PREDEFINES): Take out stuff handled by CPP_SPEC.
(CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC.
(TARGET_CPU_DEFAULT): Add ultrasparc case.
* sparc/sp64-aout.h (SPARC_V9,SPARC_ARCH64): Delete.
(TARGET_DEFAULT): MASK_ARCH64 renamed to MASK_64BIT.
(SPARC_DEFAULT_CMODEL): Define.
* sparc/sp64-elf.h (SPARC_V9,SPARC_ARCH64): Delete.
(TARGET_DEFAULT): MASK_ARCH64 renamed to MASK_64BIT. Delete
MASK_LONG64, MASK_MEDANY.
(SPARC_DEFAULT_CMODEL): Define.
(CPP_PREDEFINES): Delete.
(CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC.
(ASM_SPEC): Add %(asm_arch).
(LONG_DOUBLE_TYPE_SIZE): Define.
(DWARF2_DEBUGGING_INFO): Define.
* sparc/splet.h (CPP_SPEC): Delete.
* sparc/sysv4.h (CPP_PREDEFINES): Take out stuff handled by CPP_SPEC.
(FUNCTION_BLOCK_PROFILER): Delete TARGET_EMBMEDANY support.
(BLOCK_PROFILER): Likewise.
* sparc/sparc.c (sparc_cmodel_string,sparc_cmodel): New globals.
(sparc_override_options): Handle code model selection.
(sparc_init_expanders): Renamed from sparc64_init_expanders.
* sparc/sparc.md: TARGET_<code_model> renamed to TARGET_CM_....
TARGET_MEDANY renamed to TARGET_CM_EMBMEDANY.
(sethi_di_embmedany_{data,text}): Renamed from sethi_di_medany_....
(sethi_di_fullany): Delete.
From-SVN: r16108
This commit is contained in:
Doug Evans
parent
2d5b6dea25
commit
a0a301fc97
11 changed files with 378 additions and 354 deletions
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@ -70,10 +70,11 @@ Boston, MA 02111-1307, USA. */
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#define WCHAR_TYPE_SIZE BITS_PER_WORD
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES "-Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(sparc) -Amachine(sparc)"
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#define CPP_PREDEFINES "-Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)"
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#undef CPP_SPEC
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#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__} %{msupersparc:-D__supersparc__ -D__sparc_v8__} %{posix:-D_POSIX_SOURCE}"
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#undef CPP_SUBTARGET_SPEC
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#define CPP_SUBTARGET_SPEC \
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"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
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/* Don't default to pcc-struct-return, because gcc is the only compiler,
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and we want to retain compatibility with older gcc versions. */
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@ -42,6 +42,7 @@ Boston, MA 02111-1307, USA. */
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/* Use stabs instead of DWARF debug format. */
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#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
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#include <sparc/sysv4.h>
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#undef MD_EXEC_PREFIX
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@ -102,13 +103,15 @@ Boston, MA 02111-1307, USA. */
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#define WCHAR_TYPE_SIZE BITS_PER_WORD
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES "-D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(sparc) -Amachine(sparc)"
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#define CPP_PREDEFINES "-D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)"
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#undef CPP_SPEC
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#undef CPP_SUBTARGET_SPEC
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#ifdef USE_GNULIBC_1
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#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__} %{msupersparc:-D__supersparc__ -D__sparc_v8__} %{posix:-D_POSIX_SOURCE}"
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#define CPP_SUBTARGET_SPEC \
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"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
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#else
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#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__} %{msupersparc:-D__supersparc__ -D__sparc_v8__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
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#define CPP_SUBTARGET_SPEC \
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"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
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#endif
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#undef LIB_SPEC
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@ -19,14 +19,12 @@ along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* ??? bi-architecture support will require changes to the linker
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related specs, among perhaps other things (multilibs). */
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/* #define SPARC_BI_ARCH */
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#define LINUX_DEFAULT_ELF
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/* This is a v9 only compiler. -mv8 is not expected to work. If you want
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a v8/v9 compiler, this isn't the place to do it. */
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#define SPARC_V9 1 /* See sparc.h. */
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#define SPARC_ARCH64 1
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/* Don't assume anything about the header files. */
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#define NO_IMPLICIT_EXTERN_C
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@ -47,8 +45,8 @@ Boston, MA 02111-1307, USA. */
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fprintf (FILE, "\t.version\t\"01.01\"\n"); \
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} while (0)
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#undef ASM_DEFAULT_SPEC
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#define ASM_DEFAULT_SPEC "-Av9a"
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#undef ASM_CPU_DEFAULT_SPEC
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#define ASM_CPU_DEFAULT_SPEC "-Av9a"
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#undef LIBGCC_SPEC
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#define LIBGCC_SPEC \
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@ -78,13 +76,17 @@ Boston, MA 02111-1307, USA. */
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#undef TARGET_VERSION
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#define TARGET_VERSION fprintf (stderr, " (sparc64 Linux/ELF)");
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/* A v9 compiler with stack-bias, 32 bit integers, 64 bit longs and
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64 bit pointers, in a Medium/Anywhere code model environment. */
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/* A 64 bit v9 compiler with stack-bias,
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in a Medium/Anywhere code model environment. */
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT \
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(MASK_V9 + MASK_ARCH64 + MASK_LONG64 + MASK_PTR64 /* + MASK_HARD_QUAD */ \
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+ MASK_STACK_BIAS + MASK_MEDANY + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
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(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
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+ MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
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/* The default code model. */
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#undef SPARC_DEFAULT_CMODEL
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#define SPARC_DEFAULT_CMODEL CM_MEDANY
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#undef SIZE_TYPE
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#define SIZE_TYPE "long long unsigned int"
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@ -97,20 +99,17 @@ Boston, MA 02111-1307, USA. */
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#undef WCHAR_TYPE_SIZE
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#define WCHAR_TYPE_SIZE BITS_PER_WORD
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#undef LONG_DOUBLE_TYPE_SIZE
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#define LONG_DOUBLE_TYPE_SIZE 128
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES "-D__sparc__ -D__sparc__ -D__sparc_v9__ -D__arch64__ -D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(sparc) -Amachine(sparc)"
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#define CPP_PREDEFINES "-D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)"
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#undef CPP_SPEC
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#define CPP_SPEC "\
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#undef CPP_SUBTARGET_SPEC
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#define CPP_SUBTARGET_SPEC "\
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%{fPIC:-D__PIC__ -D__pic__} \
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%{fpic:-D__PIC__ -D__pic__} \
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%{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
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%{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
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%{mlittle-endian:-D__LITTLE_ENDIAN__} \
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%{msparclite:-D__sparclite__} \
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%{mv8:-D__sparc_v8__} \
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%{msupersparc:-D__supersparc__ -D__sparc_v8__} \
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%{posix:-D_POSIX_SOURCE} \
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"
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/* We no longer link with libc_p.a or libg.a by default. If you
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@ -162,7 +161,7 @@ Boston, MA 02111-1307, USA. */
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%{Wa,*:%*} \
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-s %{fpic:-K PIC} %{fPIC:-K PIC} \
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%{mlittle-endian:-EL} \
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%(asm_cpu) \
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%(asm_cpu) %(asm_arch) \
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"
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/* Same as sparc.h */
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@ -25,14 +25,12 @@ Boston, MA 02111-1307, USA. */
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES \
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"-Dsun -Dsparc -Dunix -D__svr4__ -D__SVR4 \
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-Asystem(unix) -Asystem(svr4) -Acpu(sparc) -Amachine(sparc)\
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-D__GCC_NEW_VARARGS__"
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"-Dsparc -Dsun -Dunix -D__svr4__ -D__SVR4 \
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-Asystem(unix) -Asystem(svr4)"
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#undef CPP_SPEC
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#define CPP_SPEC "\
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#undef CPP_SUBTARGET_SPEC
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#define CPP_SUBTARGET_SPEC "\
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%{compat-bsd:-iwithprefixbefore ucbinclude -I/usr/ucbinclude} \
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%(cpp_cpu) \
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"
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/* The sun bundled assembler doesn't accept -Yd, (and neither does gas).
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@ -46,15 +44,19 @@ Boston, MA 02111-1307, USA. */
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/* This is here rather than in sparc.h because it's not known what
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other assemblers will accept. */
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#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64
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#undef ASM_DEFAULT_SPEC
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#define ASM_DEFAULT_SPEC "-xarch=v8plus"
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#if TARGET_CPU_DEFAULT == TARGET_CPU_v9
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#undef ASM_CPU_DEFAULT_SPEC
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#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plus"
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#endif
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#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
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#undef ASM_CPU_DEFAULT_SPEC
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#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusa"
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#endif
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#undef ASM_CPU_SPEC
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#define ASM_CPU_SPEC "\
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%{mcpu=v8plus:-xarch=v8plus} \
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%{mcpu=ultrasparc:-xarch=v8plus} \
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%{!mcpu*:%(asm_default)} \
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%{mcpu=ultrasparc:-xarch=v8plusa} \
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%{!mcpu*:%(asm_cpu_default)} \
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"
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/* However it appears that Solaris 2.0 uses the same reg numbering as
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@ -1,5 +1,5 @@
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/* Definitions of target machine for GNU compiler, for SPARC64, a.out.
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Copyright (C) 1994, 1996 Free Software Foundation, Inc.
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Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc.
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Contributed by Doug Evans, dje@cygnus.com.
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This file is part of GNU CC.
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@ -19,14 +19,6 @@ along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* This is a v9 only compiler. -mv8 is not expected to work. If you want
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a v8/v9 compiler, this isn't the place to do it.
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The only code model supported is Medium/Low. */
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#define SPARC_V9 1 /* See sparc.h. */
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#define SPARC_ARCH64 1
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#include "sparc/sparc.h"
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#include "aoutos.h"
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@ -35,5 +27,9 @@ Boston, MA 02111-1307, USA. */
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT \
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(MASK_V9 + MASK_ARCH64 + MASK_PTR64 + MASK_HARD_QUAD \
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+ MASK_MEDLOW + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
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(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
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+ MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
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/* The only code model supported is Medium/Low. */
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#undef SPARC_DEFAULT_CMODEL
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#define SPARC_DEFAULT_CMODEL CM_MEDLOW
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@ -19,12 +19,6 @@ along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* This is a v9 only compiler. -mcpu=v8 is not expected to work. If you want
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a v8/v9 compiler, this isn't the place to do it. */
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#define SPARC_V9 1 /* See sparc.h. */
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#define SPARC_ARCH64 1
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/* ??? We're taking the scheme of including another file and then overriding
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the values we don't like a bit too far here. The alternative is to more or
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less duplicate all of svr4.h, sparc/sysv4.h, and sparc/sol2.h here
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@ -35,30 +29,22 @@ Boston, MA 02111-1307, USA. */
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#undef TARGET_VERSION
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#define TARGET_VERSION fprintf (stderr, " (sparc64-elf)")
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/* A v9 compiler without stack-bias, lp64 sizes,
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/* A 64 bit v9 compiler without stack-bias,
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in a Medium/Anywhere code model environment.
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There is no stack bias as this configuration is intended for
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embedded systems. */
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT \
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(MASK_V9 + MASK_ARCH64 + MASK_PTR64 + MASK_LONG64 + MASK_HARD_QUAD \
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MASK_MEDANY + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
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(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
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+ MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
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/* __svr4__ is used by the C library */
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/* ??? __arch64__ is subject to change. */
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES "\
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-D__sparc__ -D__sparc_v9__ -D__arch64__ -D__svr4__ \
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-Acpu(sparc64) -Amachine(sparc64) \
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"
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#undef SPARC_DEFAULT_CMODEL
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#define SPARC_DEFAULT_CMODEL CM_EMBMEDANY
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#undef CPP_SPEC
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#define CPP_SPEC "\
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%{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
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%{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
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%{mlittle-endian:-D__LITTLE_ENDIAN__} \
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"
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/* __svr4__ is used by the C library (FIXME) */
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#undef CPP_SUBTARGET_SPEC
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#define CPP_SUBTARGET_SPEC "-D__svr4__"
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#undef MD_EXEC_PREFIX
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#undef MD_STARTFILE_PREFIX
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@ -67,6 +53,7 @@ Boston, MA 02111-1307, USA. */
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#define ASM_SPEC "\
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%{v:-V} -s %{fpic:-K PIC} %{fPIC:-K PIC} \
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%{mlittle-endian:-EL} \
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%(asm_cpu) %(asm_arch) \
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"
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/* This is taken from sol2.h. */
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@ -102,16 +89,6 @@ crtbegin.o%s \
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#undef WORDS_BIG_ENDIAN
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#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
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/* Unfortunately, svr4.h redefines these so we have to restore them to
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their original values in sparc.h. */
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/* ??? It might be possible to eventually get svr4.h to do the right thing. */
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#undef PTRDIFF_TYPE
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#define PTRDIFF_TYPE "long long int"
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#undef SIZE_TYPE
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#define SIZE_TYPE "long long unsigned int"
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/* ??? This should be 32 bits for v9 but what can we do? */
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#undef WCHAR_TYPE
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#define WCHAR_TYPE "short unsigned int"
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@ -119,6 +96,14 @@ crtbegin.o%s \
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#undef WCHAR_TYPE_SIZE
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#define WCHAR_TYPE_SIZE 16
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#undef LONG_DOUBLE_TYPE_SIZE
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#define LONG_DOUBLE_TYPE_SIZE 128
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#undef PTRDIFF_TYPE
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#define PTRDIFF_TYPE "long long int"
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#undef SIZE_TYPE
|
||||
#define SIZE_TYPE "long long unsigned int"
|
||||
|
||||
/* The medium/anywhere code model practically requires us to put jump tables
|
||||
in the text section as gcc is unable to distinguish LABEL_REF's of jump
|
||||
tables from other label refs (when we need to). */
|
||||
|
|
@ -131,6 +116,7 @@ crtbegin.o%s \
|
|||
anyway so it is the default. */
|
||||
|
||||
#define DWARF_DEBUGGING_INFO
|
||||
#define DWARF2_DEBUGGING_INFO
|
||||
#define DBX_DEBUGGING_INFO
|
||||
|
||||
#undef PREFERRED_DEBUGGING_TYPE
|
||||
|
|
|
|||
|
|
@ -105,7 +105,12 @@ static void sparc_init_modes ();
|
|||
|
||||
/* Option handling. */
|
||||
|
||||
/* Record options as passed by user. */
|
||||
/* Code model option as passed by user. */
|
||||
char *sparc_cmodel_string;
|
||||
/* Parsed value. */
|
||||
enum cmodel sparc_cmodel;
|
||||
|
||||
/* Record alignment options as passed by user. */
|
||||
char *sparc_align_loops_string;
|
||||
char *sparc_align_jumps_string;
|
||||
char *sparc_align_funcs_string;
|
||||
|
|
@ -133,16 +138,30 @@ enum processor_type sparc_cpu;
|
|||
void
|
||||
sparc_override_options ()
|
||||
{
|
||||
static struct code_model {
|
||||
char *name;
|
||||
int value;
|
||||
} cmodels[] = {
|
||||
{ "32", CM_32 },
|
||||
{ "medlow", CM_MEDLOW },
|
||||
{ "medmid", CM_MEDMID },
|
||||
{ "medany", CM_MEDANY },
|
||||
{ "embmedany", CM_EMBMEDANY },
|
||||
{ 0, 0 }
|
||||
};
|
||||
struct code_model *cmodel;
|
||||
/* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
|
||||
static struct cpu_default {
|
||||
int cpu;
|
||||
char *name;
|
||||
} cpu_default[] = {
|
||||
/* There must be one entry here for each TARGET_CPU value. */
|
||||
{ TARGET_CPU_sparc, "cypress" },
|
||||
{ TARGET_CPU_v8, "v8" },
|
||||
{ TARGET_CPU_supersparc, "supersparc" },
|
||||
{ TARGET_CPU_sparclet, "tsc701" },
|
||||
{ TARGET_CPU_sparclite, "f930" },
|
||||
{ TARGET_CPU_v8, "v8" },
|
||||
{ TARGET_CPU_supersparc, "supersparc" },
|
||||
{ TARGET_CPU_v9, "v9" },
|
||||
{ TARGET_CPU_ultrasparc, "ultrasparc" },
|
||||
{ 0 }
|
||||
};
|
||||
|
|
@ -167,22 +186,47 @@ sparc_override_options ()
|
|||
{ "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
|
||||
/* TEMIC sparclet */
|
||||
{ "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
|
||||
/* "v9" is used to specify a true 64 bit architecture.
|
||||
"v8plus" is what Sun calls Solaris2 running on UltraSPARC's. */
|
||||
/* "v8plus" is what Sun calls Solaris2.5 running on UltraSPARC's. */
|
||||
{ "v8plus", PROCESSOR_V8PLUS, MASK_ISA, MASK_V9 },
|
||||
#if SPARC_ARCH64
|
||||
{ "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
|
||||
#endif
|
||||
/* TI ultrasparc */
|
||||
{ "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
|
||||
{ 0 }
|
||||
};
|
||||
struct cpu_table *cpu;
|
||||
struct sparc_cpu_select *sel;
|
||||
int fpu;
|
||||
|
||||
int fpu = TARGET_FPU; /* save current -mfpu status */
|
||||
#ifndef SPARC_BI_ARCH
|
||||
/* Check for unsupported architecture size. */
|
||||
if (! TARGET_64BIT != DEFAULT_ARCH32_P)
|
||||
{
|
||||
error ("%s is not supported by this configuration",
|
||||
DEFAULT_ARCH32_P ? "-m64" : "-m32");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set the default. */
|
||||
/* Code model selection. */
|
||||
sparc_cmodel = SPARC_DEFAULT_CMODEL;
|
||||
if (sparc_cmodel_string != NULL)
|
||||
{
|
||||
if (TARGET_ARCH64)
|
||||
{
|
||||
for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
|
||||
if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
|
||||
break;
|
||||
if (cmodel->name == NULL)
|
||||
error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
|
||||
else
|
||||
sparc_cmodel = cmodel->value;
|
||||
}
|
||||
else
|
||||
error ("-mcmodel= is not supported on 32 bit systems");
|
||||
}
|
||||
|
||||
fpu = TARGET_FPU; /* save current -mfpu status */
|
||||
|
||||
/* Set the default CPU. */
|
||||
for (def = &cpu_default[0]; def->name; ++def)
|
||||
if (def->cpu == TARGET_CPU_DEFAULT)
|
||||
break;
|
||||
|
|
@ -284,7 +328,7 @@ static rtx fpconv_stack_temp;
|
|||
/* Called once for each function. */
|
||||
|
||||
void
|
||||
sparc64_init_expanders ()
|
||||
sparc_init_expanders ()
|
||||
{
|
||||
fpconv_stack_temp = NULL_RTX;
|
||||
}
|
||||
|
|
@ -295,10 +339,10 @@ rtx
|
|||
sparc64_fpconv_stack_temp ()
|
||||
{
|
||||
if (fpconv_stack_temp == NULL_RTX)
|
||||
fpconv_stack_temp =
|
||||
assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0);
|
||||
fpconv_stack_temp =
|
||||
assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0);
|
||||
|
||||
return fpconv_stack_temp;
|
||||
return fpconv_stack_temp;
|
||||
}
|
||||
|
||||
/* Miscellaneous utilities. */
|
||||
|
|
@ -532,7 +576,7 @@ sp64_medium_pic_operand (op, mode)
|
|||
/* Return 1 if the operand is a data segment reference. This includes
|
||||
the readonly data segment, or in other words anything but the text segment.
|
||||
This is needed in the medium/anywhere code model on v9. These values
|
||||
are accessed with MEDANY_BASE_REG. */
|
||||
are accessed with EMBMEDANY_BASE_REG. */
|
||||
|
||||
int
|
||||
data_segment_operand (op, mode)
|
||||
|
|
@ -4679,8 +4723,8 @@ print_operand (file, x, code)
|
|||
fputs ("\n\tnop", file);
|
||||
return;
|
||||
case '_':
|
||||
/* Output the Medium/Anywhere code model base register. */
|
||||
fputs (MEDANY_BASE_REG, file);
|
||||
/* Output the Embedded Medium/Anywhere code model base register. */
|
||||
fputs (EMBMEDANY_BASE_REG, file);
|
||||
return;
|
||||
case '@':
|
||||
/* Print out what we are using as the frame pointer. This might
|
||||
|
|
@ -4944,7 +4988,7 @@ output_double_int (file, value)
|
|||
|| GET_CODE (value) == CODE_LABEL
|
||||
|| GET_CODE (value) == MINUS)))
|
||||
{
|
||||
if (!TARGET_V9 || TARGET_MEDLOW)
|
||||
if (!TARGET_V9 || TARGET_CM_MEDLOW)
|
||||
{
|
||||
ASM_OUTPUT_INT (file, const0_rtx);
|
||||
ASM_OUTPUT_INT (file, value);
|
||||
|
|
|
|||
|
|
@ -22,105 +22,133 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
|
|||
Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* Note that some other tm.h files include this one and then override
|
||||
many of the definitions that relate to assembler syntax. */
|
||||
whatever definitions are necessary. */
|
||||
|
||||
/* Sparc64 support has been added by trying to allow for a day when one
|
||||
compiler can handle both v8 and v9. There are a few cases where this
|
||||
isn't doable, but keep them to a minimum!
|
||||
/* Specify this in a cover file to provide bi-architecture (32/64) support. */
|
||||
/* #define SPARC_BI_ARCH */
|
||||
|
||||
TARGET_V9 is used to select at runtime the sparc64 chip.
|
||||
TARGET_ARCH64 is used to select at runtime a 64 bit environment.
|
||||
SPARC_V9 is defined as 0 or 1 (so it may be used inside and outside
|
||||
#define's), and says whether the cpu is a sparc64 chip (which may be
|
||||
running in a 32 or 64 bit environment).
|
||||
SPARC_ARCH64 is defined as 0 for a 32 bit environment and 1 for a 64 bit
|
||||
environment.
|
||||
/* Macro used later in this file to determine default architecture. */
|
||||
#define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
|
||||
|
||||
In places where it is possible to choose at runtime, use TARGET_V9 and
|
||||
TARGET_ARCH64. In places where it is currently not possible to select
|
||||
between the two at runtime use SPARC_{V9,ARCH64}. Again, keep uses of
|
||||
SPARC_{V9,ARCH64} to a minimum. No attempt is made to support both v8
|
||||
and v9 in the v9 compiler.
|
||||
/* TARGET_ARCH{32,64} are the main macros to decide which of the two
|
||||
architectures to compile for. We allow targets to choose compile time or
|
||||
runtime selection. */
|
||||
#ifdef SPARC_BI_ARCH
|
||||
#define TARGET_ARCH32 (! TARGET_64BIT)
|
||||
#else
|
||||
#define TARGET_ARCH32 (DEFAULT_ARCH32_P)
|
||||
#endif
|
||||
#define TARGET_ARCH64 (! TARGET_ARCH32)
|
||||
|
||||
??? All uses of SPARC_V9 have been removed. Try not to add new ones.
|
||||
/* Code model selection.
|
||||
-mcmodel is used to select the v9 code model.
|
||||
Different code models aren't supported for v8 code.
|
||||
|
||||
TARGET_CM_32: 32 bit address space, top 32 bits = 0,
|
||||
pointers are 32 bits. Note that this isn't intended
|
||||
to imply a v8 abi.
|
||||
|
||||
TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
|
||||
avoid generating %uhi and %ulo terms,
|
||||
pointers are 64 bits.
|
||||
|
||||
TARGET_CM_MEDMID: 64 bit address space.
|
||||
The executable must be in the low 16 TB of memory.
|
||||
This corresponds to the low 44 bits, and the %[hml]44
|
||||
relocs are used.
|
||||
|
||||
TARGET_CM_MEDANY: 64 bit address space.
|
||||
The text and data segments have a maximum size of 31
|
||||
bits and may be located anywhere. The maximum offset
|
||||
from any instruction to the label _GLOBAL_OFFSET_TABLE_
|
||||
is 31 bits.
|
||||
|
||||
TARGET_CM_EMBMEDANY: 64 bit address space.
|
||||
The text and data segments have a maximum size of 31 bits
|
||||
and may be located anywhere. Register %g4 contains
|
||||
the start address of the data segment.
|
||||
*/
|
||||
|
||||
#ifndef SPARC_V9
|
||||
#define SPARC_V9 0
|
||||
#endif
|
||||
#ifndef SPARC_ARCH64
|
||||
#define SPARC_ARCH64 0
|
||||
enum cmodel {
|
||||
CM_32,
|
||||
CM_MEDLOW,
|
||||
CM_MEDMID,
|
||||
CM_MEDANY,
|
||||
CM_EMBMEDANY
|
||||
};
|
||||
|
||||
/* Value of -mcmodel specified by user. */
|
||||
extern char *sparc_cmodel_string;
|
||||
/* One of CM_FOO. */
|
||||
extern enum cmodel sparc_cmodel;
|
||||
|
||||
/* V9 code model selection. */
|
||||
#define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
|
||||
#define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
|
||||
#define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
|
||||
#define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
|
||||
|
||||
#ifndef SPARC_DEFAULT_CMODEL
|
||||
#define SPARC_DEFAULT_CMODEL CM_MEDLOW
|
||||
#endif
|
||||
|
||||
/* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile. */
|
||||
/* This is call-clobbered in the normal ABI, but is reserved in the
|
||||
home grown (aka upward compatible) embedded ABI. */
|
||||
#define EMBMEDANY_BASE_REG "%g4"
|
||||
|
||||
/* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
|
||||
and specified by the user via --with-cpu=foo.
|
||||
This specifies the cpu implementation, not the architecture size. */
|
||||
#define TARGET_CPU_sparc 0
|
||||
#define TARGET_CPU_v7 0 /* alias for previous */
|
||||
#define TARGET_CPU_sparclet 1
|
||||
#define TARGET_CPU_sparclite 2
|
||||
#define TARGET_CPU_v8 3
|
||||
#define TARGET_CPU_v8 3 /* generic v8 implementation */
|
||||
#define TARGET_CPU_supersparc 4
|
||||
#define TARGET_CPU_ultrasparc 5
|
||||
#define TARGET_CPU_sparc64 5 /* alias for ultrasparc */
|
||||
#define TARGET_CPU_v9 5 /* generic v9 implementation */
|
||||
#define TARGET_CPU_sparc64 5 /* alias */
|
||||
#define TARGET_CPU_ultrasparc 6
|
||||
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc || TARGET_CPU_DEFAULT == TARGET_CPU_v8 || TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
|
||||
#define CPP_DEFAULT_SPEC ""
|
||||
#define ASM_DEFAULT_SPEC ""
|
||||
#else
|
||||
#define CPP_CPU_DEFAULT_SPEC ""
|
||||
#define ASM_CPU_DEFAULT_SPEC ""
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
|
||||
#define CPP_DEFAULT_SPEC "-D__sparclet__"
|
||||
#define ASM_DEFAULT_SPEC "-Asparclet"
|
||||
#else
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__sparclet__"
|
||||
#define ASM_CPU_DEFAULT_SPEC "-Asparclet"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
|
||||
#define CPP_DEFAULT_SPEC "-D__sparclite__"
|
||||
#define ASM_DEFAULT_SPEC "-Asparclite"
|
||||
#else
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__sparclite__"
|
||||
#define ASM_CPU_DEFAULT_SPEC "-Asparclite"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9
|
||||
/* ??? What does Sun's CC pass? */
|
||||
#define CPP_DEFAULT_SPEC "-D__sparc_v9__"
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__sparc_v9__"
|
||||
/* ??? It's not clear how other assemblers will handle this, so by default
|
||||
use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
|
||||
is handled in sol2.h. */
|
||||
#define ASM_DEFAULT_SPEC "-Av9"
|
||||
#else
|
||||
#define ASM_CPU_DEFAULT_SPEC "-Av9"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__sparc_v9__"
|
||||
#define ASM_CPU_DEFAULT_SPEC "-Av9a"
|
||||
#endif
|
||||
#ifndef CPP_CPU_DEFAULT_SPEC
|
||||
Unrecognized value in TARGET_CPU_DEFAULT.
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Names to predefine in the preprocessor for this target machine. */
|
||||
/* Names to predefine in the preprocessor for this target machine.
|
||||
??? It would be nice to not include any subtarget specific values here,
|
||||
however there's no way to portably provide subtarget values to
|
||||
CPP_PREFINES. Also, -D values in CPP_SUBTARGET_SPEC don't get turned into
|
||||
into foo, __foo and __foo__. */
|
||||
|
||||
/* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
|
||||
the right varags.h file when bootstrapping. */
|
||||
/* ??? It's not clear what value we want to use for -Acpu/machine for
|
||||
sparc64 in 32 bit environments, so for now we only use `sparc64' in
|
||||
64 bit environments. */
|
||||
/* ??? __arch64__ is subject to change. */
|
||||
|
||||
#if SPARC_ARCH64
|
||||
#define CPP_PREDEFINES \
|
||||
"-Dsparc -Dsun -Dunix -D__arch64__ \
|
||||
-Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)"
|
||||
#else
|
||||
#define CPP_PREDEFINES \
|
||||
"-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
|
||||
-Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
|
||||
#endif
|
||||
#define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem(unix) -Asystem(bsd)"
|
||||
|
||||
/* Define macros to distinguish architectures. */
|
||||
|
||||
#if SPARC_ARCH64
|
||||
#define CPP_SPEC "\
|
||||
%{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
|
||||
%{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
|
||||
"
|
||||
#else
|
||||
#define CPP_SPEC "%(cpp_cpu)"
|
||||
#endif
|
||||
|
||||
/* Common CPP definitions used by CPP_SPEC amongst the various targets
|
||||
for handling -mcpu=xxx switches. */
|
||||
/* ??? v8plus/v9/ultrasparc handling is tentative */
|
||||
#define CPP_CPU_SPEC "\
|
||||
%{mcypress:} \
|
||||
%{msparclite:-D__sparclite__} \
|
||||
|
|
@ -135,9 +163,34 @@ Unrecognized value in TARGET_CPU_DEFAULT.
|
|||
%{mcpu=v8plus:-D__sparc_v9__} \
|
||||
%{mcpu=v9:-D__sparc_v9__} \
|
||||
%{mcpu=ultrasparc:-D__sparc_v9__} \
|
||||
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_default)}}}}}}} \
|
||||
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
|
||||
"
|
||||
|
||||
/* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
|
||||
the right varags.h file when bootstrapping. */
|
||||
/* ??? It's not clear what value we want to use for -Acpu/machine for
|
||||
sparc64 in 32 bit environments, so for now we only use `sparc64' in
|
||||
64 bit environments. */
|
||||
|
||||
#define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)"
|
||||
#define CPP_ARCH64_SPEC "-D__arch64__ -Acpu(sparc64) -Amachine(sparc64)"
|
||||
#define CPP_ARCH_DEFAULT_SPEC \
|
||||
(DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
|
||||
|
||||
#define CPP_ARCH_SPEC "\
|
||||
%{m32:%(cpp_arch32)} \
|
||||
%{m64:%(cpp_arch64)} \
|
||||
%{!m32:%{!m64:%(cpp_arch_default)}} \
|
||||
"
|
||||
|
||||
/* Macros to distinguish endianness. */
|
||||
#define CPP_ENDIAN_SPEC "%{mlittle-endian:-D__LITTLE_ENDIAN__}"
|
||||
|
||||
/* Macros to distinguish the particular subtarget. */
|
||||
#define CPP_SUBTARGET_SPEC ""
|
||||
|
||||
#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
|
||||
|
||||
/* Prevent error on `-sun4' and `-target sun4' options. */
|
||||
/* This used to translate -dalign to -malign, but that is no good
|
||||
because it can't turn off the usual meaning of making debugging dumps. */
|
||||
|
|
@ -151,21 +204,6 @@ Unrecognized value in TARGET_CPU_DEFAULT.
|
|||
%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
|
||||
"
|
||||
|
||||
#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
|
||||
|
||||
/* Provide required defaults for linker -e and -d switches. */
|
||||
|
||||
#define LINK_SPEC \
|
||||
"%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
|
||||
%{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
|
||||
|
||||
/* Special flags to the Sun-4 assembler when using pipe for input. */
|
||||
|
||||
#define ASM_SPEC "\
|
||||
%| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
|
||||
%(asm_cpu) \
|
||||
"
|
||||
|
||||
/* Override in target specific files. */
|
||||
#define ASM_CPU_SPEC "\
|
||||
%{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
|
||||
|
|
@ -173,12 +211,39 @@ Unrecognized value in TARGET_CPU_DEFAULT.
|
|||
%{mf930:-Asparclite} %{mf934:-Asparclite} \
|
||||
%{mcpu=sparclite:-Asparclite} \
|
||||
%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
|
||||
%{mcpu=v8plus:-Av9a} \
|
||||
%{mcpu=v8plus:-Av8plus} \
|
||||
%{mcpu=v9:-Av9} \
|
||||
%{mcpu=ultrasparc:-Av9a} \
|
||||
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_default)}}}}}}} \
|
||||
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
|
||||
"
|
||||
|
||||
/* Word size selection, among other things. */
|
||||
#define ASM_ARCH32_SPEC "-32"
|
||||
#define ASM_ARCH64_SPEC "-64"
|
||||
#define ASM_ARCH_DEFAULT_SPEC \
|
||||
(DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
|
||||
|
||||
#define ASM_ARCH_SPEC "\
|
||||
%{m32:%(asm_arch32)} \
|
||||
%{m64:%(asm_arch64)} \
|
||||
%{!m32:%{!m64:%(asm_arch_default)}} \
|
||||
"
|
||||
|
||||
/* Special flags to the Sun-4 assembler when using pipe for input. */
|
||||
|
||||
#define ASM_SPEC "\
|
||||
%| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
|
||||
%(asm_cpu) %(asm_arch) \
|
||||
"
|
||||
|
||||
#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
|
||||
|
||||
/* Provide required defaults for linker -e and -d switches. */
|
||||
|
||||
#define LINK_SPEC \
|
||||
"%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
|
||||
%{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
|
||||
|
||||
/* This macro defines names of additional specifications to put in the specs
|
||||
that can be used in various specifications like CC1_SPEC. Its definition
|
||||
is an initializer with a subgrouping for each command option.
|
||||
|
|
@ -189,22 +254,31 @@ Unrecognized value in TARGET_CPU_DEFAULT.
|
|||
|
||||
Do not define this macro if it does not need to do anything. */
|
||||
|
||||
#define EXTRA_SPECS \
|
||||
#define EXTRA_SPECS \
|
||||
{ "cpp_cpu", CPP_CPU_SPEC }, \
|
||||
{ "cpp_default", CPP_DEFAULT_SPEC }, \
|
||||
{ "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
|
||||
{ "cpp_arch32", CPP_ARCH32_SPEC }, \
|
||||
{ "cpp_arch64", CPP_ARCH64_SPEC }, \
|
||||
{ "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
|
||||
{ "cpp_arch", CPP_ARCH_SPEC }, \
|
||||
{ "cpp_endian", CPP_ENDIAN_SPEC }, \
|
||||
{ "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
|
||||
{ "asm_cpu", ASM_CPU_SPEC }, \
|
||||
{ "asm_default", ASM_DEFAULT_SPEC }, \
|
||||
{ "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
|
||||
{ "asm_arch32", ASM_ARCH32_SPEC }, \
|
||||
{ "asm_arch64", ASM_ARCH64_SPEC }, \
|
||||
{ "asm_arch_default", ASM_ARCH_DEFAULT_SPEC }, \
|
||||
{ "asm_arch", ASM_ARCH_SPEC }, \
|
||||
SUBTARGET_EXTRA_SPECS
|
||||
|
||||
#define SUBTARGET_EXTRA_SPECS
|
||||
|
||||
#if SPARC_ARCH64
|
||||
#define PTRDIFF_TYPE "long long int"
|
||||
#define SIZE_TYPE "long long unsigned int"
|
||||
#else
|
||||
#define PTRDIFF_TYPE "int"
|
||||
/* The default value for SIZE_TYPE is "unsigned int" which is what we want. */
|
||||
#ifdef SPARC_BI_ARCH
|
||||
#define NO_BUILTIN_PTRDIFF_TYPE
|
||||
#define NO_BUILTIN_SIZE_TYPE
|
||||
#endif
|
||||
#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long long int" : "int")
|
||||
#define SIZE_TYPE (TARGET_ARCH64 ? "long long unsigned int" : "unsigned int")
|
||||
|
||||
/* ??? This should be 32 bits for v9 but what can we do? */
|
||||
#define WCHAR_TYPE "short unsigned int"
|
||||
|
|
@ -335,16 +409,7 @@ extern int target_flags;
|
|||
#define MASK_LITTLE_ENDIAN 0x1000
|
||||
#define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
|
||||
|
||||
/* Nonzero if ints are 64 bits.
|
||||
This automatically implies longs are 64 bits too.
|
||||
This option is for v9 only. */
|
||||
#define MASK_INT64 0x2000
|
||||
#define TARGET_INT64 (target_flags & MASK_INT64)
|
||||
|
||||
/* Nonzero if longs are 64 bits.
|
||||
This option is for v9 only. */
|
||||
#define MASK_LONG64 0x4000
|
||||
#define TARGET_LONG64 (target_flags & MASK_LONG64)
|
||||
/* 0x2000, 0x4000 are unused */
|
||||
|
||||
/* Nonzero if pointers are 64 bits.
|
||||
This is not a user selectable option, though it may be one day -
|
||||
|
|
@ -352,31 +417,13 @@ extern int target_flags;
|
|||
#define MASK_PTR64 0x8000
|
||||
#define TARGET_PTR64 (target_flags & MASK_PTR64)
|
||||
|
||||
/* Nonzero if generating code to run in a 64 bit environment. */
|
||||
#define MASK_ARCH64 0x10000
|
||||
#define TARGET_ARCH64 (target_flags & MASK_ARCH64)
|
||||
#define TARGET_ARCH32 (! TARGET_ARCH64)
|
||||
/* Nonzero if generating code to run in a 64 bit environment.
|
||||
This is intended to only be used by TARGET_ARCH{32,64} as they are the
|
||||
mechanism used to control compile time or run time selection. */
|
||||
#define MASK_64BIT 0x10000
|
||||
#define TARGET_64BIT (target_flags & MASK_64BIT)
|
||||
|
||||
/* SPARC64 memory models.
|
||||
TARGET_MEDLOW: 32 bit address space, top 32 bits = 0,
|
||||
avoid generating %uhi and %ulo terms.
|
||||
(pointers can be 32 or 64 bits)
|
||||
TARGET_MEDANY: 64 bit address space, data segment restricted to 4G, but
|
||||
can be loaded anywhere (use %g4 as offset).
|
||||
TARGET_FULLANY: 64 bit address space, no restrictions.
|
||||
This option is not fully supported yet.
|
||||
These options are for v9 only. All mask values are nonzero so the v8
|
||||
compiler can assume this stuff won't interfere. */
|
||||
#define MASK_MEDLOW 0x20000
|
||||
#define MASK_MEDANY 0x40000
|
||||
#define MASK_FULLANY 0x60000
|
||||
#define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY)
|
||||
#define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW)
|
||||
#define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY)
|
||||
#define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY)
|
||||
|
||||
/* ??? There are hardcoded references to this reg in the .md file. */
|
||||
#define MEDANY_BASE_REG "%g4"
|
||||
/* 0x20000,0x40000 unused */
|
||||
|
||||
/* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
|
||||
adding 2047 to %sp. This option is for v9 only and is the default. */
|
||||
|
|
@ -427,15 +474,22 @@ extern int target_flags;
|
|||
{"no-app-regs", -MASK_APP_REGS}, \
|
||||
{"hard-quad-float", MASK_HARD_QUAD}, \
|
||||
{"soft-quad-float", -MASK_HARD_QUAD}, \
|
||||
/* ??? These are coerced to -mcpu=. Delete in 2.9. */ \
|
||||
/* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
|
||||
{"cypress", 0}, \
|
||||
{"sparclite", 0}, \
|
||||
{"f930", 0}, \
|
||||
{"f934", 0}, \
|
||||
{"v8", 0}, \
|
||||
{"supersparc", 0}, \
|
||||
/* End of deprecated options. */ \
|
||||
/* -mptrNN exists for *experimental* purposes. */ \
|
||||
/* {"ptr64", MASK_PTR64}, */ \
|
||||
/* {"ptr32", -MASK_PTR64}, */ \
|
||||
{"32", -MASK_64BIT}, \
|
||||
{"64", MASK_64BIT}, \
|
||||
{"stack-bias", MASK_STACK_BIAS}, \
|
||||
{"no-stack-bias", -MASK_STACK_BIAS}, \
|
||||
SUBTARGET_SWITCHES \
|
||||
ARCH64_SWITCHES \
|
||||
{ "", TARGET_DEFAULT}}
|
||||
|
||||
/* MASK_APP_REGS must always be the default because that's what
|
||||
|
|
@ -446,32 +500,6 @@ extern int target_flags;
|
|||
/* This is meant to be redefined in target specific files. */
|
||||
#define SUBTARGET_SWITCHES
|
||||
|
||||
/* ??? Until we support a combination 32/64 bit compiler, these options
|
||||
are only defined for the v9 compiler in a true 64 bit environment. */
|
||||
#if SPARC_ARCH64
|
||||
#define ARCH64_SWITCHES \
|
||||
/* {"arch32", -MASK_ARCH64}, */ \
|
||||
/* {"arch64", MASK_ARCH64}, */ \
|
||||
{"int64", MASK_INT64+MASK_LONG64}, \
|
||||
{"int32", -MASK_INT64}, \
|
||||
{"int32", MASK_LONG64}, \
|
||||
{"long64", -MASK_INT64}, \
|
||||
{"long64", MASK_LONG64}, \
|
||||
{"long32", -(MASK_INT64+MASK_LONG64)}, \
|
||||
/* {"ptr64", MASK_PTR64}, */ \
|
||||
/* {"ptr32", -MASK_PTR64}, */ \
|
||||
{"stack-bias", MASK_STACK_BIAS}, \
|
||||
{"no-stack-bias", -MASK_STACK_BIAS}, \
|
||||
{"medlow", -MASK_CODE_MODEL}, \
|
||||
{"medlow", MASK_MEDLOW}, \
|
||||
{"medany", -MASK_CODE_MODEL}, \
|
||||
{"medany", MASK_MEDANY}, \
|
||||
{"fullany", -MASK_CODE_MODEL}, \
|
||||
{"fullany", MASK_FULLANY},
|
||||
#else
|
||||
#define ARCH64_SWITCHES
|
||||
#endif
|
||||
|
||||
/* Processor type.
|
||||
These must match the values for the cpu attribute in sparc.md. */
|
||||
enum processor_type {
|
||||
|
|
@ -515,11 +543,12 @@ extern enum processor_type sparc_cpu;
|
|||
|
||||
#define TARGET_OPTIONS \
|
||||
{ \
|
||||
{"cpu=", &sparc_select[1].string}, \
|
||||
{"tune=", &sparc_select[2].string}, \
|
||||
{"align-loops=", &sparc_align_loops_string }, \
|
||||
{"align-jumps=", &sparc_align_jumps_string }, \
|
||||
{"align-functions=", &sparc_align_funcs_string }, \
|
||||
{ "cpu=", &sparc_select[1].string }, \
|
||||
{ "tune=", &sparc_select[2].string }, \
|
||||
{ "cmodel=", &sparc_cmodel_string }, \
|
||||
{ "align-loops=", &sparc_align_loops_string }, \
|
||||
{ "align-jumps=", &sparc_align_jumps_string }, \
|
||||
{ "align-functions=", &sparc_align_funcs_string }, \
|
||||
SUBTARGET_OPTIONS \
|
||||
}
|
||||
|
||||
|
|
@ -591,16 +620,17 @@ extern int sparc_align_funcs;
|
|||
/* Now define the sizes of the C data types. */
|
||||
|
||||
#define SHORT_TYPE_SIZE 16
|
||||
#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
|
||||
#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
|
||||
#define INT_TYPE_SIZE 32
|
||||
#define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
|
||||
#define LONG_LONG_TYPE_SIZE 64
|
||||
#define FLOAT_TYPE_SIZE 32
|
||||
#define DOUBLE_TYPE_SIZE 64
|
||||
|
||||
#define MAX_INT_TYPE_SIZE 64
|
||||
#if defined (SPARC_BI_ARCH)
|
||||
#define MAX_LONG_TYPE_SIZE 64
|
||||
#endif
|
||||
|
||||
#if SPARC_ARCH64
|
||||
#if 0
|
||||
/* ??? This does not work in SunOS 4.x, so it is not enabled here.
|
||||
Instead, it is enabled in sol2.h, because it does work under Solaris. */
|
||||
/* Define for support of TFmode long double and REAL_ARITHMETIC.
|
||||
|
|
@ -655,7 +685,6 @@ if (TARGET_ARCH64 \
|
|||
#define FUNCTION_BOUNDARY (1 << (sparc_align_funcs + 3))
|
||||
|
||||
/* Alignment of field after `int : 0' in a structure. */
|
||||
/* ??? Should this be based on TARGET_INT64? */
|
||||
#define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
|
||||
|
||||
/* Every structure's size must be a multiple of this. */
|
||||
|
|
@ -791,11 +820,14 @@ if (TARGET_ARCH64 \
|
|||
g5 through g7 are reserved for the operating system.
|
||||
|
||||
On v9 systems:
|
||||
g1,g4,g5 are free to use as temporaries.
|
||||
g1,g5 are free to use between calls if call is to external function via PLT.
|
||||
g1,g5 are free to use as temporaries, and are free to use between calls
|
||||
if the call is to an external function via the PLT.
|
||||
g4 is free to use as a temporary in the non-embedded case.
|
||||
g4 is reserved in the embedded case.
|
||||
g2-g3 are reserved for applications. Gcc normally uses them as
|
||||
temporaries, but this can be disabled via the -mno-app-regs option.
|
||||
g6-g7 are reserved for the operating system.
|
||||
g6-g7 are reserved for the operating system (or application in
|
||||
embedded case).
|
||||
??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
|
||||
currently be a fixed register until this pattern is rewritten.
|
||||
Register 1 is also used when restoring call-preserved registers in large
|
||||
|
|
@ -854,11 +886,11 @@ if (TARGET_ARCH64 \
|
|||
#define CONDITIONAL_REGISTER_USAGE \
|
||||
do \
|
||||
{ \
|
||||
if (! SPARC_ARCH64) \
|
||||
if (TARGET_ARCH32) \
|
||||
{ \
|
||||
fixed_regs[5] = 1; \
|
||||
} \
|
||||
if (SPARC_ARCH64) \
|
||||
else \
|
||||
{ \
|
||||
fixed_regs[1] = 1; \
|
||||
} \
|
||||
|
|
@ -884,7 +916,7 @@ do \
|
|||
/* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \
|
||||
fixed_regs[2] |= ! TARGET_APP_REGS; \
|
||||
fixed_regs[3] |= ! TARGET_APP_REGS; \
|
||||
fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_MEDANY; \
|
||||
fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_CM_EMBMEDANY; \
|
||||
if (TARGET_FLAT) \
|
||||
{ \
|
||||
/* Let the compiler believe the frame pointer is still \
|
||||
|
|
@ -962,7 +994,7 @@ extern int sparc_mode_class[];
|
|||
#define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
|
||||
|
||||
/* The stack bias (amount by which the hardware register is offset by). */
|
||||
#define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0)
|
||||
#define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
|
||||
|
||||
/* Is stack biased? */
|
||||
#define STACK_BIAS SPARC_STACK_BIAS
|
||||
|
|
@ -1579,11 +1611,9 @@ function_arg_padding ((MODE), (TYPE))
|
|||
space at some point.
|
||||
??? Use assign_stack_temp? */
|
||||
|
||||
extern void sparc64_init_expanders ();
|
||||
extern void sparc_init_expanders ();
|
||||
extern struct rtx_def *sparc64_fpconv_stack_temp ();
|
||||
#if SPARC_ARCH64
|
||||
#define INIT_EXPANDERS sparc64_init_expanders ()
|
||||
#endif
|
||||
#define INIT_EXPANDERS sparc_init_expanders ()
|
||||
|
||||
/* Define the information needed to generate branch and scc insns. This is
|
||||
stored from the compare operation. Note that we can't use "rtx" here
|
||||
|
|
@ -1655,8 +1685,6 @@ extern int leaf_function;
|
|||
fputs ("\tsethi %hi(", FILE); \
|
||||
assemble_name (FILE, buf); \
|
||||
fputs ("),%o0\n", FILE); \
|
||||
if (TARGET_MEDANY) \
|
||||
fprintf (FILE, "\tadd %%o0,%s,%%o0\n", MEDANY_BASE_REG); \
|
||||
fputs ("\tcall mcount\n\tadd %o0,%lo(", FILE); \
|
||||
assemble_name (FILE, buf); \
|
||||
fputs ("),%o0\n", FILE); \
|
||||
|
|
@ -1756,20 +1784,12 @@ do \
|
|||
switch (profile_block_flag) \
|
||||
{ \
|
||||
case 2: \
|
||||
if (TARGET_MEDANY) \
|
||||
fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tadd %%o0,%s,%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tadd %g0,%%lo(%d),%%o1\n",\
|
||||
MEDANY_BASE_REG, bol, bol); \
|
||||
else \
|
||||
fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\
|
||||
bol, bol); \
|
||||
fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\
|
||||
bol, bol); \
|
||||
break; \
|
||||
default: \
|
||||
if (TARGET_MEDANY) \
|
||||
fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
|
||||
MEDANY_BASE_REG, bol, MEDANY_BASE_REG, bol);\
|
||||
else \
|
||||
fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
|
||||
bol, bol); \
|
||||
fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
|
||||
bol, bol); \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -1847,21 +1867,13 @@ do \
|
|||
switch (profile_block_flag) \
|
||||
{ \
|
||||
case 2: \
|
||||
if (TARGET_MEDANY) \
|
||||
fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tor %%0,%%lo(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%s+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%0,%%lo(LPBX0),%%g2\n\tadd %%g2,%s,%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%g1+%%lo(___bb)]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
|
||||
blockn, blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
|
||||
else \
|
||||
fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
|
||||
blockn, blockn); \
|
||||
fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
|
||||
blockn, blockn); \
|
||||
break; \
|
||||
default: \
|
||||
if (TARGET_MEDANY) \
|
||||
fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \
|
||||
4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
|
||||
else \
|
||||
fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
|
||||
fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
|
||||
\tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
|
||||
4 * blockn, 4 * blockn, 4 * blockn); \
|
||||
4 * blockn, 4 * blockn, 4 * blockn); \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -2436,12 +2448,12 @@ extern struct rtx_def *legitimize_pic_address ();
|
|||
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
|
||||
|
||||
/* If we are referencing a function make the SYMBOL_REF special.
|
||||
In the Medium/Anywhere code model, %g4 points to the data segment so we
|
||||
must not add it to function addresses. */
|
||||
In the Embedded Medium/Anywhere code model, %g4 points to the data segment
|
||||
so we must not add it to function addresses. */
|
||||
|
||||
#define ENCODE_SECTION_INFO(DECL) \
|
||||
do { \
|
||||
if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
|
||||
if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
|
||||
SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
|
||||
} while (0)
|
||||
|
||||
|
|
@ -2910,7 +2922,7 @@ do { \
|
|||
ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
|
||||
if (Pmode == SImode) \
|
||||
fprintf (FILE, "\t.word\t"); \
|
||||
else if (TARGET_MEDLOW) \
|
||||
else if (TARGET_CM_MEDLOW) \
|
||||
fprintf (FILE, "\t.word\t0\n\t.word\t"); \
|
||||
else \
|
||||
fprintf (FILE, "\t.xword\t"); \
|
||||
|
|
@ -2927,7 +2939,7 @@ do { \
|
|||
ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
|
||||
if (Pmode == SImode) \
|
||||
fprintf (FILE, "\t.word\t"); \
|
||||
else if (TARGET_MEDLOW) \
|
||||
else if (TARGET_CM_MEDLOW) \
|
||||
fprintf (FILE, "\t.word\t0\n\t.word\t"); \
|
||||
else \
|
||||
fprintf (FILE, "\t.xword\t"); \
|
||||
|
|
@ -3014,7 +3026,7 @@ do { \
|
|||
(FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
|
||||
fprintf (FILE, ",0\n"); \
|
||||
} \
|
||||
else if (TARGET_MEDANY || TARGET_FULLANY) \
|
||||
else if (TARGET_CM_EMBMEDANY) \
|
||||
{ \
|
||||
fprintf (FILE, "\tsetx "); \
|
||||
assemble_name \
|
||||
|
|
@ -3055,7 +3067,7 @@ do { \
|
|||
#define TARGET_CR 015
|
||||
|
||||
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
|
||||
((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
|
||||
((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
|
||||
|
||||
/* Print operand X (an rtx) in assembler syntax to file FILE.
|
||||
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
|
||||
|
|
|
|||
|
|
@ -1777,21 +1777,27 @@
|
|||
;; Most of the required support for the various code models is here.
|
||||
;; We can do this because sparcs need the high insn to load the address. We
|
||||
;; just need to get high to do the right thing for each code model. Then each
|
||||
;; uses the same "%X+%lo(...)" in the load/store insn.
|
||||
;; uses the same "%X+%lo(...)" in the load/store insn, though in the case of
|
||||
;; the medium/middle code model "%lo" is written "%l44".
|
||||
|
||||
;; When TARGET_MEDLOW, assume that the upper 32 bits of symbol addresses are
|
||||
;; When TARGET_CM_MEDLOW, assume that the upper 32 bits of symbol addresses are
|
||||
;; always 0.
|
||||
;; When TARGET_MEDANY, the text and data segments have a maximum size of 32
|
||||
;; bits and may be located anywhere. MEDANY_BASE_REG contains the start
|
||||
;; When TARGET_CM_MEDMID, the executable must be in the low 16 TB of memory.
|
||||
;; This corresponds to the low 44 bits, and the %[hml]44 relocs are used.
|
||||
;; ??? Not implemented yet.
|
||||
;; When TARGET_CM_EMBMEDANY, the text and data segments have a maximum size of
|
||||
;; 31 bits and may be located anywhere. EMBMEDANY_BASE_REG contains the start
|
||||
;; address of the data segment, currently %g4.
|
||||
;; When TARGET_FULLANY, symbolic addresses are 64 bits.
|
||||
;; When TARGET_CM_MEDANY, the text and data segments have a maximum size of 31
|
||||
;; bits and may be located anywhere. The maximum offset from any instruction
|
||||
;; to the label _GLOBAL_OFFSET_TABLE_ is 31 bits.
|
||||
|
||||
(define_insn "*sethi_di_medlow"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (match_operand 1 "" "")))
|
||||
;; The clobber is here because emit_move_sequence assumes the worst case.
|
||||
(clobber (reg:DI 1))]
|
||||
"TARGET_MEDLOW && check_pic (1)"
|
||||
"TARGET_CM_MEDLOW && check_pic (1)"
|
||||
"sethi %%hi(%a1),%0"
|
||||
[(set_attr "type" "move")
|
||||
(set_attr "length" "1")])
|
||||
|
|
@ -1799,7 +1805,7 @@
|
|||
(define_insn "*sethi_di_medium_pic"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (match_operand 1 "sp64_medium_pic_operand" "")))]
|
||||
"(TARGET_MEDLOW || TARGET_MEDANY) && check_pic (1)"
|
||||
"(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
|
||||
"sethi %%hi(%a1),%0"
|
||||
[(set_attr "type" "move")
|
||||
(set_attr "length" "1")])
|
||||
|
|
@ -1807,31 +1813,22 @@
|
|||
;; WARNING: %0 gets %hi(%1)+%g4.
|
||||
;; You cannot OR in %lo(%1), it must be added in.
|
||||
|
||||
(define_insn "*sethi_di_medany_data"
|
||||
(define_insn "*sethi_di_embmedany_data"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (match_operand 1 "data_segment_operand" "")))
|
||||
;; The clobber is here because emit_move_sequence assumes the worst case.
|
||||
(clobber (reg:DI 1))]
|
||||
"TARGET_MEDANY && check_pic (1)"
|
||||
"sethi %%hi(%a1),%0; add %0,%%g4,%0"
|
||||
"TARGET_CM_EMBMEDANY && check_pic (1)"
|
||||
"sethi %%hi(%a1),%0; add %0,%_,%0"
|
||||
[(set_attr "type" "move")
|
||||
(set_attr "length" "2")])
|
||||
|
||||
(define_insn "*sethi_di_medany_text"
|
||||
(define_insn "*sethi_di_embmedany_text"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (match_operand 1 "text_segment_operand" "")))
|
||||
;; The clobber is here because emit_move_sequence assumes the worst case.
|
||||
(clobber (reg:DI 1))]
|
||||
"TARGET_MEDANY && check_pic (1)"
|
||||
"sethi %%uhi(%a1),%%g1; or %%g1,%%ulo(%a1),%%g1; sllx %%g1,32,%%g1; sethi %%hi(%a1),%0; or %0,%%g1,%0"
|
||||
[(set_attr "type" "move")
|
||||
(set_attr "length" "5")])
|
||||
|
||||
(define_insn "*sethi_di_fullany"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (match_operand 1 "" "")))
|
||||
(clobber (reg:DI 1))]
|
||||
"TARGET_FULLANY && check_pic (1)"
|
||||
"TARGET_CM_EMBMEDANY && check_pic (1)"
|
||||
"sethi %%uhi(%a1),%%g1; or %%g1,%%ulo(%a1),%%g1; sllx %%g1,32,%%g1; sethi %%hi(%a1),%0; or %0,%%g1,%0"
|
||||
[(set_attr "type" "move")
|
||||
(set_attr "length" "5")])
|
||||
|
|
|
|||
|
|
@ -36,12 +36,6 @@ Boston, MA 02111-1307, USA. */
|
|||
{"broken-saverestore", MASK_BROKEN_SAVERESTORE}, \
|
||||
{"no-broken-saverestore", -MASK_BROKEN_SAVERESTORE},
|
||||
|
||||
#undef CPP_SPEC
|
||||
#define CPP_SPEC "\
|
||||
%(cpp_cpu) \
|
||||
%{mlittle-endian:-D__LITTLE_ENDIAN__} \
|
||||
"
|
||||
|
||||
#undef ASM_SPEC
|
||||
#define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)"
|
||||
|
||||
|
|
|
|||
|
|
@ -52,9 +52,7 @@ Boston, MA 02111-1307, USA. */
|
|||
the Sparc running svr4. __svr4__ is our extension. */
|
||||
|
||||
#define CPP_PREDEFINES \
|
||||
"-Dsparc -Dunix -D__svr4__ \
|
||||
-Asystem(unix) -Asystem(svr4) -Acpu(sparc) -Amachine(sparc) \
|
||||
-D__GCC_NEW_VARARGS__"
|
||||
"-Dsparc -Dunix -D__svr4__ -Asystem(unix) -Asystem(svr4)"
|
||||
|
||||
/* The native assembler can't compute differences between symbols in different
|
||||
sections when generating pic code, so we must put jump tables in the
|
||||
|
|
@ -201,12 +199,8 @@ do { \
|
|||
#undef FUNCTION_BLOCK_PROFILER
|
||||
#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
|
||||
do { \
|
||||
if (TARGET_MEDANY) \
|
||||
fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tor %%0,%%lo(.LLPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne .LLPY%d\n\tadd %%o0,%s,%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \
|
||||
MEDANY_BASE_REG, (LABELNO), MEDANY_BASE_REG, (LABELNO)); \
|
||||
else \
|
||||
fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tld [%%lo(.LLPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(.LLPBX0),%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \
|
||||
(LABELNO), (LABELNO)); \
|
||||
fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tld [%%lo(.LLPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(.LLPBX0),%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \
|
||||
(LABELNO), (LABELNO)); \
|
||||
} while (0)
|
||||
|
||||
/* Output assembler code to FILE to increment the entry-count for
|
||||
|
|
@ -216,13 +210,9 @@ do { \
|
|||
#define BLOCK_PROFILER(FILE, BLOCKNO) \
|
||||
{ \
|
||||
int blockn = (BLOCKNO); \
|
||||
if (TARGET_MEDANY) \
|
||||
fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tor %%g1,%%lo(.LLPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \
|
||||
4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
|
||||
else \
|
||||
fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tld [%%lo(.LLPBX2+%d)+%%g1],%%g2\n\
|
||||
fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tld [%%lo(.LLPBX2+%d)+%%g1],%%g2\n\
|
||||
\tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(.LLPBX2+%d)+%%g1]\n", \
|
||||
4 * blockn, 4 * blockn, 4 * blockn); \
|
||||
4 * blockn, 4 * blockn, 4 * blockn); \
|
||||
}
|
||||
|
||||
/* A C statement (sans semicolon) to output to the stdio stream
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue