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install.texi: Add documentation for --enable-altivec.

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2001-12-19  Aldy Hernandez  <aldyh@redhat.com>

        * doc/install.texi: Add documentation for --enable-altivec.

        * config.gcc: Add support for --enable-altivec.

        * config/rs6000/altivec.h: New.

        * config/rs6000/linuxaltivec.h (SUBSUBTARGET_OVERRIDE_OPTIONS):
        Define.  Fix typo.

        * config/rs6000/rs6000.c (vrsave_operation): Change unspec to
	unspec_volatile.
        (generate_set_vrsave): Generate the unspec here instead of calling
        an .md pattern.
        (generate_set_vrsave): Use gen_rtvec.
        (rs6000_emit_prologue): Replace call to gen_get_vrsave with
        gen_rtx_SET.

        * config/rs6000/rs6000.md ("*movsi_internal1"): Add constraints
	for setting special registers.
        ("*set_vrsave_internal"): Use unspec_volatile.
        ("set_vrsave"): Remove.
        ("get_vrsave"): Remove.

        * config/rs6000/rs6000.h (REG_CLASS_CONTENTS): Add vrsave to
	SPECIAL_REGS.

From-SVN: r48194
This commit is contained in:
Aldy Hernandez 2001-12-20 04:42:23 +00:00 • committed by Aldy Hernandez
parent b5639a499e
commit a004eb826e
7 changed files with 86 additions and 32 deletions
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28
gcc/ChangeLog
View file

@ -1,3 +1,31 @@
2001-12-19 Aldy Hernandez <aldyh@redhat.com>
* doc/install.texi: Add documentation for --enable-altivec.
* config.gcc: Add support for --enable-altivec.
* config/rs6000/altivec.h: New.
* config/rs6000/linuxaltivec.h (SUBSUBTARGET_OVERRIDE_OPTIONS):
Define. Fix typo.
* config/rs6000/rs6000.c (vrsave_operation): Change unspec to
unspec_volatile.
(generate_set_vrsave): Generate the unspec here instead of calling
an .md pattern.
(generate_set_vrsave): Use gen_rtvec.
(rs6000_emit_prologue): Replace call to gen_get_vrsave with
gen_rtx_SET.
* config/rs6000/rs6000.md ("*movsi_internal1"): Add constraints
for setting special registers.
("*set_vrsave_internal"): Use unspec_volatile.
("set_vrsave"): Remove.
("get_vrsave"): Remove.
* config/rs6000/rs6000.h (REG_CLASS_CONTENTS): Add vrsave to
SPECIAL_REGS.
2001-12-19 Bruce Korb <bkorb@gnu.org>
* gcc/fixinc/inclhack.def: Remove all the fix suppression "fixes".

27
gcc/config/rs6000/altivec.h Normal file
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@ -0,0 +1,27 @@
/* Target definitions for GNU compiler for PowerPC with AltiVec.
Copyright (C) 2001 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldyh@redhat.com).
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
do { \
rs6000_altivec_abi = 1; \
target_flags |= MASK_ALTIVEC; \
} while (0)

3
gcc/config/rs6000/linuxaltivec.h
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@ -27,4 +27,5 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_ALTIVEC)
#undef SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1

23
gcc/config/rs6000/rs6000.c
View file

@ -4555,7 +4555,7 @@ vrsave_operation (op, mode)
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
return 0;
dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
@ -7831,8 +7831,14 @@ generate_set_vrsave (reg, info, epiloguep)
{
int nclobs, i;
rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
clobs[0] = gen_set_vrsave (reg);
clobs[0]
= gen_rtx_SET (VOIDmode,
vrsave,
gen_rtx_UNSPEC_VOLATILE (SImode,
gen_rtvec (2, reg, vrsave),
30));
nclobs = 1;
@ -7859,12 +7865,12 @@ generate_set_vrsave (reg, info, epiloguep)
else
{
rtx reg = gen_rtx_REG (V4SImode, i);
rtvec r = rtvec_alloc (1);
RTVEC_ELT (r, 0) = reg;
clobs[nclobs++]
= gen_rtx_SET (VOIDmode, reg, gen_rtx_UNSPEC (V4SImode, r, 27));
= gen_rtx_SET (VOIDmode,
reg,
gen_rtx_UNSPEC (V4SImode,
gen_rtvec (1, reg), 27));
}
}
@ -7958,12 +7964,13 @@ rs6000_emit_prologue ()
if (TARGET_ALTIVEC && info->vrsave_mask != 0)
{
rtx reg, mem;
rtx reg, mem, vrsave;
int offset;
/* Get VRSAVE onto a GPR. */
reg = gen_rtx_REG (SImode, 12);
emit_insn (gen_get_vrsave (reg));
vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
/* Save VRSAVE. */
offset = info->vrsave_save_offset + sp_offset;

2
gcc/config/rs6000/rs6000.h
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@ -1120,7 +1120,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
{ 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
{ 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
{ 0x00000000, 0x00000000, 0x00000007, 0x00000000 }, /* SPECIAL_REGS */ \
{ 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
{ 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
{ 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \

29
gcc/config/rs6000/rs6000.md
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@ -7630,8 +7630,8 @@
(set_attr "length" "4")])
(define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
(match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
(match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
"gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)"
"@
@ -7646,9 +7646,10 @@
mf%1 %0
mt%0 %1
mt%0 %1
mt%0 %1
cror 0,0,0"
[(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*")
(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
[(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*")
(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
;; Split a load of a large constant into the appropriate two-insn
;; sequence.
@ -13944,31 +13945,15 @@
vor %0,%1,%1"
[(set_attr "type" "altivec")])
;; Copy VRSAVE into a GPR.
(define_insn "get_vrsave"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(reg:SI 109)] 28))]
"TARGET_ALTIVEC"
"mfvrsave %0"
[(set_attr "type" "altivec")])
(define_insn "*set_vrsave_internal"
[(match_parallel 0 "vrsave_operation"
[(set (reg:SI 109)
(unspec:SI [(match_operand:SI 1 "register_operand" "r")
(reg:SI 109)] 30))])]
(unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
(reg:SI 109)] 30))])]
"TARGET_ALTIVEC"
"mtvrsave %1"
[(set_attr "type" "altivec")])
(define_insn "set_vrsave"
[(set (reg:SI 109)
(unspec:SI [(match_operand:SI 0 "register_operand" "r")
(reg:SI 109)] 30))]
"TARGET_ALTIVEC"
"mtvrsave %0"
[(set_attr "type" "altivec")])
;; Simple binary operations.
(define_insn "addv16qi3"

6
gcc/doc/install.texi
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@ -678,6 +678,12 @@ SPARC@. If configure does not recognize the model name (e.g.@: arm700,
603e, or ultrasparc) you provide, please check the configure script
for a complete list of supported models.
@item --enable-altivec
Specify that the target supports AltiVec vector enhancements. This
option will adjust the ABI for AltiVec enhancements, as well as generate
AltiVec code when appropriate. This option is only available for
PowerPC systems.
@item --enable-target-optspace
Specify that target
libraries should be optimized for code space instead of code speed.