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RISC-V: Remove redundant vcond patterns

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Previously, Richi has suggested that vcond patterns are only needed when target
support comparison + select consuming 1 instruction.

Now, I do the experiments on removing those "vcond" patterns, it works perfectly.

All testcases PASS.

Really appreicate Richi helps us recognize such issue.

Now remove all "vcond" patterns as Richi suggested.

gcc/ChangeLog:

	* config/riscv/autovec.md (vcond<V:mode><VI:mode>): Remove redundant
	vcond patterns.
	(vcondu<V:mode><VI:mode>): Ditto.
	* config/riscv/riscv-protos.h (expand_vcond): Ditto.
	* config/riscv/riscv-v.cc (expand_vcond): Ditto.
This commit is contained in:
Juzhe-Zhong 2023-06-26 11:38:30 +08:00 • committed by Pan Li
parent ab6eac20f0
commit 9f76f04be4
3 changed files with 0 additions and 61 deletions
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38
gcc/config/riscv/autovec.md
View file

@ -311,44 +311,6 @@
}
)
;; -------------------------------------------------------------------------
;; ---- [INT,FP] Compare and select
;; -------------------------------------------------------------------------
;; The patterns in this section are synthetic.
;; -------------------------------------------------------------------------
(define_expand "vcond<V:mode><VI:mode>"
[(set (match_operand:V 0 "register_operand")
(if_then_else:V
(match_operator 3 "comparison_operator"
[(match_operand:VI 4 "register_operand")
(match_operand:VI 5 "register_operand")])
(match_operand:V 1 "register_operand")
(match_operand:V 2 "register_operand")))]
"TARGET_VECTOR && known_eq (GET_MODE_NUNITS (<V:MODE>mode),
GET_MODE_NUNITS (<VI:MODE>mode))"
{
riscv_vector::expand_vcond (operands);
DONE;
}
)
(define_expand "vcondu<V:mode><VI:mode>"
[(set (match_operand:V 0 "register_operand")
(if_then_else:V
(match_operator 3 "comparison_operator"
[(match_operand:VI 4 "register_operand")
(match_operand:VI 5 "register_operand")])
(match_operand:V 1 "register_operand")
(match_operand:V 2 "register_operand")))]
"TARGET_VECTOR && known_eq (GET_MODE_NUNITS (<V:MODE>mode),
GET_MODE_NUNITS (<VI:MODE>mode))"
{
riscv_vector::expand_vcond (operands);
DONE;
}
)
;; -------------------------------------------------------------------------
;; ---- [INT] Sign and zero extension
;; -------------------------------------------------------------------------

1
gcc/config/riscv/riscv-protos.h
View file

@ -252,7 +252,6 @@ machine_mode preferred_simd_mode (scalar_mode);
opt_machine_mode get_mask_mode (machine_mode);
void expand_vec_series (rtx, rtx, rtx);
void expand_vec_init (rtx, rtx);
void expand_vcond (rtx *);
void expand_vec_perm (rtx, rtx, rtx, rtx);
void expand_select_vl (rtx *);
void expand_load_store (rtx *, bool);

22
gcc/config/riscv/riscv-v.cc
View file

@ -2421,28 +2421,6 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1,
return false;
}
/* Expand an RVV vcond pattern with operands OPS. DATA_MODE is the mode
of the data being merged and CMP_MODE is the mode of the values being
compared. */
void
expand_vcond (rtx *ops)
{
machine_mode cmp_mode = GET_MODE (ops[4]);
machine_mode data_mode = GET_MODE (ops[1]);
machine_mode mask_mode = get_mask_mode (cmp_mode).require ();
rtx mask = gen_reg_rtx (mask_mode);
if (FLOAT_MODE_P (cmp_mode))
{
if (expand_vec_cmp_float (mask, GET_CODE (ops[3]), ops[4], ops[5], true))
std::swap (ops[1], ops[2]);
}
else
expand_vec_cmp (mask, GET_CODE (ops[3]), ops[4], ops[5]);
emit_insn (
gen_vcond_mask (data_mode, data_mode, ops[0], ops[1], ops[2], mask));
}
/* Implement vec_perm<mode>. */
void