procyberian/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

2017-07-28 Tamar Christina <tamar.christina@arm.com>

Browse source 
* config/aarch64/aarch64.c
	(aarch64_internal_mov_immediate): Add new special pattern.
	* config/aarch64/aarch64.md (*movdi_aarch64):
	Add reg/32bit const mov case.

gcc/testsuite/
2017-07-28  Tamar Christina  <tamar.christina@arm.com>

	* gcc.target/aarch64/int_mov_immediate_1.c: New.

From-SVN: r250680
This commit is contained in:
Tamar Christina 2017-07-28 16:47:08 +00:00 • committed by Tamar Christina
parent 8de33df278
commit 9de009354e
5 changed files with 102 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
gcc/ChangeLog
View file

@ -1,3 +1,10 @@
2017-07-28 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.c
(aarch64_internal_mov_immediate): Add new special pattern.
* config/aarch64/aarch64.md (*movdi_aarch64):
Add reg/32bit const mov case.
2017-07-28 Tamar Christina <tamar.christina@arm.com>
Richard Sandiford <richard.sandiford@linaro.org>

25
gcc/config/aarch64/aarch64.c
View file

@ -1832,6 +1832,31 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
return 1;
}
/* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
(with XXXX non-zero). In that case check to see if the move can be done in
a smaller mode. */
val2 = val & 0xffffffff;
if (mode == DImode
&& aarch64_move_imm (val2, SImode)
&& (((val >> 32) & 0xffff) == 0 || (val >> 48) == 0))
{
if (generate)
emit_insn (gen_rtx_SET (dest, GEN_INT (val2)));
/* Check if we have to emit a second instruction by checking to see
if any of the upper 32 bits of the original DI mode value is set. */
if (val == val2)
return 1;
i = (val >> 48) ? 48 : 32;
if (generate)
emit_insn (gen_insv_immdi (dest, GEN_INT (i),
GEN_INT ((val >> i) & 0xffff)));
return 2;
}
if ((val >> 32) == 0 || mode == SImode)
{
if (generate)

13
gcc/config/aarch64/aarch64.md
View file

@ -962,8 +962,8 @@
)
(define_insn_and_split "*movdi_aarch64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m, m,r,r, *w,r,*w,w")
(match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,n,m, m,rZ,*w,Usa,Ush,rZ,w,*w,Dd"))]
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,r,r,*w,m, m,r,r, *w,r,*w,w")
(match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,M,n,m, m,rZ,*w,Usa,Ush,rZ,w,*w,Dd"))]
"(register_operand (operands[0], DImode)
|| aarch64_reg_or_zero (operands[1], DImode))"
"@
@ -971,6 +971,7 @@
mov\\t%0, %x1
mov\\t%x0, %1
mov\\t%x0, %1
mov\\t%w0, %1
#
ldr\\t%x0, %1
ldr\\t%d0, %1
@ -989,10 +990,10 @@
aarch64_expand_mov_immediate (operands[0], operands[1]);
DONE;
}"
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
adr,adr,f_mcr,f_mrc,fmov,neon_move")
(set_attr "fp" "*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
(set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load1,\
load1,store1,store1,adr,adr,f_mcr,f_mrc,fmov,neon_move")
(set_attr "fp" "*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
(set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
)
(define_insn "insv_imm<mode>"

4
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,7 @@
2017-07-28 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/int_mov_immediate_1.c: New.
2017-07-28 Bin Cheng <bin.cheng@arm.com>
* gcc.dg/vect/pr80815-3.c: Require vect_perm.

59
gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c Normal file
View file

@ -0,0 +1,59 @@
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
/* { dg-options "-O3" } */
long long f1(void)
{
return 0xffff6666;
}
int f3(void)
{
return 0xffff6666;
}
long f2(void)
{
return 0x11110000ffff6666;
}
long f4(void)
{
return 0x11110001ffff6666;
}
long f5(void)
{
return 0x111100001ff6666;
}
long f6(void)
{
return 0x00001111ffff6666;
}
long f7(void)
{
return 0x000011116666ffff;
}
long f8(void)
{
return 0x0f0011116666ffff;
}
/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, -39322" 1 } } */
/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 4294927974" 3 } } */
/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 1718026239" 1 } } */
/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -2576941057" 1 } } */
/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -39322" 1 } } */
/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 26214" 1 } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0xf00, lsl 48" 1 } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1111, lsl 48" 2 } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1000, lsl 32" 1 } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1111, lsl 32" 3 } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x111, lsl 48" 1 } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1ff, lsl 16" 1 } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1, lsl 32" 1 } } */