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i386.md (simple_return_indirect_internal): New expander.

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* config/i386/i386.md (simple_return_indirect_internal): New expander.
	(*simple_return_indirect_internal<mode>): Rename from
	simple_return_indirect_internal.  Use W mode iterator.
	(rstorssp): New expander.
	(*rstorssp<mode>): Rename from rstorssp.  Use P mode iterator.
	(clrssbsy): New expander.
	(*clrssbsy<mode>): Rename from clrssbsy.  Use P mode iterator.

From-SVN: r261208
This commit is contained in:
Uros Bizjak 2018-06-05 20:04:07 +02:00 • committed by Uros Bizjak
parent 9063f9ed9c
commit 9c5913b3c2
2 changed files with 39 additions and 13 deletions
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10
gcc/ChangeLog
View file

@ -1,3 +1,13 @@
2018-06-05 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (simple_return_indirect_internal): New expander.
(*simple_return_indirect_internal<mode>): Rename from
simple_return_indirect_internal. Use W mode iterator.
(rstorssp): New expander.
(*rstorssp<mode>): Rename from rstorssp. Use P mode iterator.
(clrssbsy): New expander.
(*clrssbsy<mode>): Rename from clrssbsy. Use P mode iterator.
2018-06-05 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm_cmse.h (cmse_nsfptr_create): Change typeof to

42
gcc/config/i386/i386.md
View file

@ -13483,9 +13483,14 @@
(set_attr "modrm" "0")
(set_attr "maybe_prefix_bnd" "1")])
(define_insn "simple_return_indirect_internal"
(define_expand "simple_return_indirect_internal"
[(parallel
[(simple_return)
(use (match_operand 0 "register_operand"))])])
(define_insn "*simple_return_indirect_internal<mode>"
[(simple_return)
(use (match_operand 0 "register_operand" "r"))]
(use (match_operand:W 0 "register_operand" "r"))]
"reload_completed"
"* return ix86_output_indirect_function_return (operands[0]);"
[(set (attr "type")
@ -20641,7 +20646,7 @@
(define_insn "incssp<mode>"
[(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r")]
UNSPECV_INCSSP)]
UNSPECV_INCSSP)]
"TARGET_SHSTK || (flag_cf_protection & CF_RETURN)"
"incssp<mskmodesuffix>\t%0"
[(set_attr "length" "4")
@ -20654,9 +20659,14 @@
[(set_attr "length" "5")
(set_attr "type" "other")])
(define_insn "rstorssp"
[(unspec_volatile [(match_operand 0 "memory_operand" "m")]
UNSPECV_RSTORSSP)]
(define_expand "rstorssp"
[(unspec_volatile [(match_operand 0 "memory_operand")]
UNSPECV_RSTORSSP)]
"TARGET_SHSTK")
(define_insn "*rstorssp<mode>"
[(unspec_volatile [(match_operand:P 0 "memory_operand" "m")]
UNSPECV_RSTORSSP)]
"TARGET_SHSTK"
"rstorssp\t%0"
[(set_attr "length" "5")
@ -20665,7 +20675,7 @@
(define_insn "wrss<mode>"
[(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r")
(match_operand:SWI48x 1 "memory_operand" "m")]
UNSPECV_WRSS)]
UNSPECV_WRSS)]
"TARGET_SHSTK"
"wrss<mskmodesuffix>\t%0, %1"
[(set_attr "length" "3")
@ -20674,7 +20684,7 @@
(define_insn "wruss<mode>"
[(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r")
(match_operand:SWI48x 1 "memory_operand" "m")]
UNSPECV_WRUSS)]
UNSPECV_WRUSS)]
"TARGET_SHSTK"
"wruss<mskmodesuffix>\t%0, %1"
[(set_attr "length" "4")
@ -20687,9 +20697,14 @@
[(set_attr "length" "4")
(set_attr "type" "other")])
(define_insn "clrssbsy"
[(unspec_volatile [(match_operand 0 "memory_operand" "m")]
UNSPECV_CLRSSBSY)]
(define_expand "clrssbsy"
[(unspec_volatile [(match_operand 0 "memory_operand")]
UNSPECV_CLRSSBSY)]
"TARGET_SHSTK")
(define_insn "*clrssbsy<mode>"
[(unspec_volatile [(match_operand:P 0 "memory_operand" "m")]
UNSPECV_CLRSSBSY)]
"TARGET_SHSTK"
"clrssbsy\t%0"
[(set_attr "length" "4")
@ -20698,8 +20713,9 @@
(define_insn "nop_endbr"
[(unspec_volatile [(const_int 0)] UNSPECV_NOP_ENDBR)]
"(flag_cf_protection & CF_BRANCH)"
"*
{ return (TARGET_64BIT)? \"endbr64\" : \"endbr32\"; }"
{
return TARGET_64BIT ? "endbr64" : "endbr32";
}
[(set_attr "length" "4")
(set_attr "length_immediate" "0")
(set_attr "modrm" "0")])