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GCN: Generally enable the 'gcc.target/gcn/avgpr-[...]' test cases

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... added in commit ae0d2c2402
"amdgcn: Add Accelerator VGPR registers".  This way, they're correctly tested
no matter what '-march=[...]' is used with 'make check'.

	gcc/testsuite/
	* gcc.target/gcn/avgpr-mem-double.c: Remove
	'dg-skip-if "incompatible ISA" [...]'.
	* gcc.target/gcn/avgpr-mem-int.c: Likewise.
	* gcc.target/gcn/avgpr-mem-long.c: Likewise.
	* gcc.target/gcn/avgpr-mem-short.c: Likewise.
	* gcc.target/gcn/avgpr-spill-double.c: Likewise.
	* gcc.target/gcn/avgpr-spill-int.c: Likewise.
	* gcc.target/gcn/avgpr-spill-long.c: Likewise.
	* gcc.target/gcn/avgpr-spill-short.c: Likewise.
This commit is contained in:
Thomas Schwinge 2023-11-16 23:17:36 +01:00
parent 318f5232cf
commit 9bd6ee8a82
8 changed files with 0 additions and 8 deletions
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1
gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c
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@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=gfx90a -O1" } */
/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
/* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
/* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */

1
gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c
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@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=gfx90a -O1" } */
/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
/* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
/* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */

1
gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c
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@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=gfx90a -O1" } */
/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
/* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
/* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */

1
gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c
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@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=gfx90a -O1" } */
/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
/* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
/* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */

1
gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
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@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=gfx908 -O1" } */
/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
/* { dg-final { scan-assembler "accvgpr" } } */
#define TYPE double

1
gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
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@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=gfx908 -O1" } */
/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
/* { dg-final { scan-assembler "accvgpr" } } */
#ifndef TYPE

1
gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
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@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=gfx908 -O1" } */
/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
/* { dg-final { scan-assembler "accvgpr" } } */
#define TYPE long

1
gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
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@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=gfx908 -O1" } */
/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
/* { dg-final { scan-assembler "accvgpr" } } */
#define TYPE short