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RISC-V: Bugfix for merging undef tmp register for trunc

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For trunc function autovec, there will be one step like below take MU
for the merge operand.

rtx tmp = gen_reg_rtx (vec_int_mode);
emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode);

The MU will leave the tmp (aka dest register) register unmasked elements
unchanged and it is undefined here. This patch would like to adjust the
MU to MA.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): Add insn type
	arg.
	(expand_vec_trunc): Take MA instead of MU for cvt_x_f_rtz.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li 2023-10-23 15:45:12 +08:00
parent e1b1cba141
commit 996785db50
1 changed files with 12 additions and 4 deletions
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16
gcc/config/riscv/riscv-v.cc
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@ -4144,12 +4144,20 @@ emit_vec_cvt_f_x (rtx op_dest, rtx op_src, rtx mask,
static void
emit_vec_cvt_x_f_rtz (rtx op_dest, rtx op_src, rtx mask,
machine_mode vec_mode)
insn_type type, machine_mode vec_mode)
{
rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src};
insn_code icode = code_for_pred (FIX, vec_mode);
emit_vlmax_insn (icode, UNARY_OP_TAMU, cvt_x_ops);
if (type & USE_VUNDEF_MERGE_P)
{
rtx cvt_x_ops[] = {op_dest, mask, op_src};
emit_vlmax_insn (icode, type, cvt_x_ops);
}
else
{
rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src};
emit_vlmax_insn (icode, type, cvt_x_ops);
}
}
void
@ -4285,7 +4293,7 @@ expand_vec_trunc (rtx op_0, rtx op_1, machine_mode vec_fp_mode,
/* Step-3: Convert to integer on mask, rounding to zero (aka truncate). */
rtx tmp = gen_reg_rtx (vec_int_mode);
emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode);
emit_vec_cvt_x_f_rtz (tmp, op_1, mask, UNARY_OP_TAMA, vec_fp_mode);
/* Step-4: Convert to floating-point on mask for the rint result. */
emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode);