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Add x86 tune to enable v2df vector reduction by paddpd.

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The tune is disabled by default.

gcc/ChangeLog:

	PR target/97147
	* config/i386/i386.h (TARGET_V2DF_REDUCTION_PREFER_HADDPD):
	New macro.
	* config/i386/sse.md (*sse3_haddv2df3_low): Add
	TARGET_V2DF_REDUCTION_PREFER_HADDPD.
	(*sse3_hsubv2df3_low): Ditto.
	* config/i386/x86-tune.def
	(X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD): New tune.

gcc/testsuite/ChangeLog:

	PR target/97147
	* gcc.target/i386/pr54400.c: Adjust testcase.
	* gcc.target/i386/pr94147.c: New test.
This commit is contained in:
liuhongt 2021-08-17 13:11:26 +08:00
parent 2d14d64bf2
commit 97d51c1764
5 changed files with 32 additions and 3 deletions
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2
gcc/config/i386/i386.h
View file

@ -418,6 +418,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
#define TARGET_EXPAND_ABS \
ix86_tune_features[X86_TUNE_EXPAND_ABS]
#define TARGET_V2DF_REDUCTION_PREFER_HADDPD \
ix86_tune_features[X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD]
/* Feature tests against the various architecture variations. */
enum ix86_arch_indices {

4
gcc/config/i386/sse.md
View file

@ -2771,7 +2771,7 @@
(vec_select:DF
(match_dup 1)
(parallel [(match_operand:SI 3 "const_0_to_1_operand")]))))]
"TARGET_SSE3
"TARGET_SSE3 && TARGET_V2DF_REDUCTION_PREFER_HADDPD
&& INTVAL (operands[2]) != INTVAL (operands[3])"
"@
haddpd\t{%0, %0|%0, %0}
@ -2790,7 +2790,7 @@
(vec_select:DF
(match_dup 1)
(parallel [(const_int 1)]))))]
"TARGET_SSE3"
"TARGET_SSE3 && TARGET_V2DF_REDUCTION_PREFER_HADDPD"
"@
hsubpd\t{%0, %0|%0, %0}
vhsubpd\t{%1, %1, %0|%0, %1, %1}"

5
gcc/config/i386/x86-tune.def
View file

@ -452,6 +452,11 @@ DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER)
smaller FMA chain. */
DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains", m_ZNVER2 | m_ZNVER3)
/* X86_TUNE_V2DF_REDUCTION_PREFER_PHADDPD: Prefer haddpd
for v2df vector reduction. */
DEF_TUNE (X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD,
"v2df_reduction_prefer_haddpd", m_NONE)
/*****************************************************************************/
/* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
/*****************************************************************************/

2
gcc/testsuite/gcc.target/i386/pr54400.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
/* { dg-options "-O2 -msse3 -mfpmath=sse -mtune-ctrl=v2df_reduction_prefer_haddpd" } */
#include <x86intrin.h>

22
gcc/testsuite/gcc.target/i386/pr94147.c Normal file
View file

@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
#include <x86intrin.h>
double f (__m128d p)
{
return p[0] - p[1];
}
double g1 (__m128d p)
{
return p[0] + p[1];
}
double g2 (__m128d p)
{
return p[1] + p[0];
}
/* { dg-final { scan-assembler-not "hsubpd" } } */
/* { dg-final { scan-assembler-not "haddpd" } } */