re PR target/83604 (ICE in copy_to_mode_reg, at explow.c:630)
PR target/83604 * config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineinvqb_v64qi, __builtin_ia32_vgf2p8affineqb_v64qi, __builtin_ia32_vgf2p8mulb_v64qi): Require also OPTION_MASK_ISA_AVX512F in addition to OPTION_MASK_ISA_GFNI. (__builtin_ia32_vgf2p8affineinvqb_v16qi_mask, __builtin_ia32_vgf2p8affineqb_v16qi_mask): Require OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_SSE in addition to OPTION_MASK_ISA_GFNI. (__builtin_ia32_vgf2p8mulb_v32qi_mask): Require OPTION_MASK_ISA_AVX512VL in addition to OPTION_MASK_ISA_GFNI and OPTION_MASK_ISA_AVX512BW. (__builtin_ia32_vgf2p8mulb_v16qi_mask): Require OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_AVX512BW in addition to OPTION_MASK_ISA_GFNI. (__builtin_ia32_vgf2p8affineinvqb_v16qi, __builtin_ia32_vgf2p8affineqb_v16qi, __builtin_ia32_vgf2p8mulb_v16qi): Require OPTION_MASK_ISA_SSE2 instead of OPTION_MASK_ISA_SSE in addition to OPTION_MASK_ISA_GFNI. * config/i386/i386.c (def_builtin): Change to builtin isa/isa2 being a requirement for all ISAs rather than any of them with a few exceptions. (ix86_add_new_builtins): Clear OPTION_MASK_ISA_64BIT from isa before processing. (ix86_expand_builtin): Require all ISAs from builtin's isa and isa2 bitmasks to be enabled with 3 exceptions, instead of requiring any enabled ISA with lots of exceptions. * config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>, vgf2p8affineqb_<mode><mask_name>, vgf2p8mulb_<mode><mask_name>): Change avx512bw in isa attribute to avx512f. * config/i386/sgxintrin.h: Add license boilerplate. * config/i386/vaesintrin.h: Likewise. Fix macro spelling __AVX512F to __AVX512F__ and __AVX512VL to __AVX512VL__. (_mm256_aesdec_epi128, _mm256_aesdeclast_epi128, _mm256_aesenc_epi128, _mm256_aesenclast_epi128): Enable temporarily avx if __AVX__ is not defined. * config/i386/gfniintrin.h (_mm_gf2p8mul_epi8, _mm_gf2p8affineinv_epi64_epi8, _mm_gf2p8affine_epi64_epi8): Enable temporarily sse2 rather than sse if not enabled already. * gcc.target/i386/sse-26.c: New test. From-SVN: r256281
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
d33e32a723
commit
958d63e911
9 changed files with 148 additions and 66 deletions
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@ -1,5 +1,46 @@
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2018-01-05 Jakub Jelinek <jakub@redhat.com>
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PR target/83604
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* config/i386/i386-builtin.def
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(__builtin_ia32_vgf2p8affineinvqb_v64qi,
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__builtin_ia32_vgf2p8affineqb_v64qi, __builtin_ia32_vgf2p8mulb_v64qi):
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Require also OPTION_MASK_ISA_AVX512F in addition to
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OPTION_MASK_ISA_GFNI.
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(__builtin_ia32_vgf2p8affineinvqb_v16qi_mask,
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__builtin_ia32_vgf2p8affineqb_v16qi_mask): Require
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OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_SSE in addition
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to OPTION_MASK_ISA_GFNI.
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(__builtin_ia32_vgf2p8mulb_v32qi_mask): Require
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OPTION_MASK_ISA_AVX512VL in addition to OPTION_MASK_ISA_GFNI and
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OPTION_MASK_ISA_AVX512BW.
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(__builtin_ia32_vgf2p8mulb_v16qi_mask): Require
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OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_AVX512BW in
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addition to OPTION_MASK_ISA_GFNI.
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(__builtin_ia32_vgf2p8affineinvqb_v16qi,
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__builtin_ia32_vgf2p8affineqb_v16qi, __builtin_ia32_vgf2p8mulb_v16qi):
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Require OPTION_MASK_ISA_SSE2 instead of OPTION_MASK_ISA_SSE in addition
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to OPTION_MASK_ISA_GFNI.
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* config/i386/i386.c (def_builtin): Change to builtin isa/isa2 being
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a requirement for all ISAs rather than any of them with a few
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exceptions.
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(ix86_add_new_builtins): Clear OPTION_MASK_ISA_64BIT from isa before
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processing.
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(ix86_expand_builtin): Require all ISAs from builtin's isa and isa2
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bitmasks to be enabled with 3 exceptions, instead of requiring any
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enabled ISA with lots of exceptions.
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* config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
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vgf2p8affineqb_<mode><mask_name>, vgf2p8mulb_<mode><mask_name>):
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Change avx512bw in isa attribute to avx512f.
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* config/i386/sgxintrin.h: Add license boilerplate.
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* config/i386/vaesintrin.h: Likewise. Fix macro spelling __AVX512F
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to __AVX512F__ and __AVX512VL to __AVX512VL__.
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(_mm256_aesdec_epi128, _mm256_aesdeclast_epi128, _mm256_aesenc_epi128,
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_mm256_aesenclast_epi128): Enable temporarily avx if __AVX__ is not
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defined.
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* config/i386/gfniintrin.h (_mm_gf2p8mul_epi8,
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_mm_gf2p8affineinv_epi64_epi8, _mm_gf2p8affine_epi64_epi8): Enable
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temporarily sse2 rather than sse if not enabled already.
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PR target/83604
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* config/i386/sse.md (VI248_VLBW): Rename to ...
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(VI248_AVX512VL): ... this. Don't guard V32HI with TARGET_AVX512BW.
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@ -28,9 +28,9 @@
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#ifndef _GFNIINTRIN_H_INCLUDED
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#define _GFNIINTRIN_H_INCLUDED
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#if !defined(__GFNI__) || !defined(__SSE__)
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#if !defined(__GFNI__) || !defined(__SSE2__)
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#pragma GCC push_options
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#pragma GCC target("gfni,sse")
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#pragma GCC target("gfni,sse2")
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#define __DISABLE_GFNI__
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#endif /* __GFNI__ */
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@ -2530,24 +2530,24 @@ BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpshldv_
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BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpshldv_v2di_maskz, "__builtin_ia32_vpshldv_v2di_maskz", IX86_BUILTIN_VPSHLDVV2DI_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT)
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/* GFNI */
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BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v64qi, "__builtin_ia32_vgf2p8affineinvqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512F, CODE_FOR_vgf2p8affineinvqb_v64qi, "__builtin_ia32_vgf2p8affineinvqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v64qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v64qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX, CODE_FOR_vgf2p8affineinvqb_v32qi, "__builtin_ia32_vgf2p8affineinvqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEINVQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
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BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineqb_v64qi, "__builtin_ia32_vgf2p8affineqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE2, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512F, CODE_FOR_vgf2p8affineqb_v64qi, "__builtin_ia32_vgf2p8affineqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v64qi_mask, "__builtin_ia32_vgf2p8affineqb_v64qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX, CODE_FOR_vgf2p8affineqb_v32qi, "__builtin_ia32_vgf2p8affineqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineqb_v32qi_mask, "__builtin_ia32_vgf2p8affineqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineqb_v16qi, "__builtin_ia32_vgf2p8affineqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineqb_v16qi_mask, "__builtin_ia32_vgf2p8affineqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
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BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8mulb_v64qi, "__builtin_ia32_vgf2p8mulb_v64qi", IX86_BUILTIN_VGF2P8MULB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v32qi_mask, "__builtin_ia32_vgf2p8affineqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE2, CODE_FOR_vgf2p8affineqb_v16qi, "__builtin_ia32_vgf2p8affineqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineqb_v16qi_mask, "__builtin_ia32_vgf2p8affineqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512F, CODE_FOR_vgf2p8mulb_v64qi, "__builtin_ia32_vgf2p8mulb_v64qi", IX86_BUILTIN_VGF2P8MULB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v64qi_mask, "__builtin_ia32_vgf2p8mulb_v64qi_mask", IX86_BUILTIN_VGF2P8MULB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX, CODE_FOR_vgf2p8mulb_v32qi, "__builtin_ia32_vgf2p8mulb_v32qi", IX86_BUILTIN_VGF2P8MULB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v32qi_mask, "__builtin_ia32_vgf2p8mulb_v32qi_mask", IX86_BUILTIN_VGF2P8MULB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8mulb_v16qi, "__builtin_ia32_vgf2p8mulb_v16qi", IX86_BUILTIN_VGF2P8MULB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v16qi_mask, "__builtin_ia32_vgf2p8mulb_v16qi_mask", IX86_BUILTIN_VGF2P8MULB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v32qi_mask, "__builtin_ia32_vgf2p8mulb_v32qi_mask", IX86_BUILTIN_VGF2P8MULB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE2, CODE_FOR_vgf2p8mulb_v16qi, "__builtin_ia32_vgf2p8mulb_v16qi", IX86_BUILTIN_VGF2P8MULB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
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BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8mulb_v16qi_mask, "__builtin_ia32_vgf2p8mulb_v16qi_mask", IX86_BUILTIN_VGF2P8MULB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI)
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/* VNNI */
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@ -29816,28 +29816,20 @@ def_builtin (HOST_WIDE_INT mask, const char *name,
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{
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ix86_builtins_isa[(int) code].isa = mask;
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/* OPTION_MASK_ISA_AVX512{F,VL,BW} have special meaning. Despite of
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generic case, where any bit set means that built-in is enable, this
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bit must be *and-ed* with another one. E.g.:
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OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL
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means that *both* cpuid bits must be set for the built-in to
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be available. Handle this here. */
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mask &= ~OPTION_MASK_ISA_64BIT;
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/* Filter out the masks most often ored together with others. */
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if ((mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
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&& mask != OPTION_MASK_ISA_AVX512VL)
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mask &= ~OPTION_MASK_ISA_AVX512VL;
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if ((mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW)
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&& mask != OPTION_MASK_ISA_AVX512BW)
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mask &= ~OPTION_MASK_ISA_AVX512BW;
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if ((mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512F)
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&& mask != OPTION_MASK_ISA_AVX512F)
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mask &= ~OPTION_MASK_ISA_AVX512F;
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mask &= ~OPTION_MASK_ISA_64BIT;
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if (mask == 0
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|| (mask & ix86_isa_flags) != 0
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|| (lang_hooks.builtin_function
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== lang_hooks.builtin_function_ext_scope))
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{
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tree type = ix86_get_builtin_func_type (tcode);
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decl = add_builtin_function (name, type, code, BUILT_IN_MD,
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@ -29972,6 +29964,8 @@ def_builtin_pure2 (HOST_WIDE_INT mask, const char *name,
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static void
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ix86_add_new_builtins (HOST_WIDE_INT isa, HOST_WIDE_INT isa2)
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{
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isa &= ~OPTION_MASK_ISA_64BIT;
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if ((isa & deferred_isa_values) == 0
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&& (isa2 & deferred_isa_values2) == 0)
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return;
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@ -35389,41 +35383,34 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
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}
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}
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/* Determine whether the builtin function is available under the current ISA.
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Originally the builtin was not created if it wasn't applicable to the
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current ISA based on the command line switches. With function specific
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options, we need to check in the context of the function making the call
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whether it is supported. Treat AVX512{VL,BW,F} and MMX specially. For
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other flags, if isa includes more than one ISA bit, treat those are
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requiring any of them. For AVX512VL, require both AVX512VL and the
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non-AVX512VL ISAs. Likewise for MMX, require both MMX and the non-MMX
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ISAs. Similarly for AVX512F and AVX512BW.
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Similarly for 64BIT, but we shouldn't be building such builtins
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at all, -m64 is a whole TU option. */
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if (((ix86_builtins_isa[fcode].isa
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& ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX
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| OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_AVX512BW
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| OPTION_MASK_ISA_AVX512F))
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&& !(ix86_builtins_isa[fcode].isa
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& ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX
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| OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_AVX512BW
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| OPTION_MASK_ISA_AVX512F)
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& ix86_isa_flags))
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|| ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512VL)
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&& !(ix86_isa_flags & OPTION_MASK_ISA_AVX512VL))
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|| ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512BW)
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&& !(ix86_isa_flags & OPTION_MASK_ISA_AVX512BW))
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|| ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512F)
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&& !(ix86_isa_flags & OPTION_MASK_ISA_AVX512F))
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|| ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_MMX)
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&& !(ix86_isa_flags & OPTION_MASK_ISA_MMX))
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|| (ix86_builtins_isa[fcode].isa2
|
||||
&& !(ix86_builtins_isa[fcode].isa2 & ix86_isa_flags2)))
|
||||
HOST_WIDE_INT isa = ix86_isa_flags;
|
||||
HOST_WIDE_INT isa2 = ix86_isa_flags2;
|
||||
HOST_WIDE_INT bisa = ix86_builtins_isa[fcode].isa;
|
||||
HOST_WIDE_INT bisa2 = ix86_builtins_isa[fcode].isa2;
|
||||
/* The general case is we require all the ISAs specified in bisa{,2}
|
||||
to be enabled.
|
||||
The exceptions are:
|
||||
OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A
|
||||
OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32
|
||||
OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4
|
||||
where for each this pair it is sufficient if either of the ISAs is
|
||||
enabled, plus if it is ored with other options also those others. */
|
||||
if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A))
|
||||
== (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A))
|
||||
&& (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A)) != 0)
|
||||
isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A);
|
||||
if (((bisa & (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32))
|
||||
== (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32))
|
||||
&& (isa & (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32)) != 0)
|
||||
isa |= (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32);
|
||||
if (((bisa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
|
||||
== (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
|
||||
&& (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
|
||||
isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
|
||||
if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)
|
||||
{
|
||||
char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa,
|
||||
ix86_builtins_isa[fcode].isa2, 0, 0,
|
||||
NULL, NULL, (enum fpmath_unit) 0,
|
||||
false);
|
||||
char *opts = ix86_target_string (bisa, bisa2, 0, 0, NULL, NULL,
|
||||
(enum fpmath_unit) 0, false);
|
||||
if (!opts)
|
||||
error ("%qE needs unknown isa option", fndecl);
|
||||
else
|
||||
|
|
|
|||
|
|
@ -1,3 +1,26 @@
|
|||
/* Copyright (C) 2017-2018 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef _SGXINTRIN_H_INCLUDED
|
||||
#define _SGXINTRIN_H_INCLUDED
|
||||
|
||||
|
|
|
|||
|
|
@ -20074,7 +20074,7 @@
|
|||
gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
|
||||
vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}
|
||||
vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
|
||||
[(set_attr "isa" "noavx,avx,avx512bw")
|
||||
[(set_attr "isa" "noavx,avx,avx512f")
|
||||
(set_attr "prefix_data16" "1,*,*")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "orig,maybe_evex,evex")
|
||||
|
|
@ -20092,7 +20092,7 @@
|
|||
gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
|
||||
vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}
|
||||
vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
|
||||
[(set_attr "isa" "noavx,avx,avx512bw")
|
||||
[(set_attr "isa" "noavx,avx,avx512f")
|
||||
(set_attr "prefix_data16" "1,*,*")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "orig,maybe_evex,evex")
|
||||
|
|
@ -20109,7 +20109,7 @@
|
|||
gf2p8mulb\t{%2, %0| %0, %2}
|
||||
vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}
|
||||
vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}"
|
||||
[(set_attr "isa" "noavx,avx,avx512bw")
|
||||
[(set_attr "isa" "noavx,avx,avx512f")
|
||||
(set_attr "prefix_data16" "1,*,*")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "orig,maybe_evex,evex")
|
||||
|
|
|
|||
|
|
@ -1,9 +1,32 @@
|
|||
/* Copyright (C) 2017-2018 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef __VAESINTRIN_H_INCLUDED
|
||||
#define __VAESINTRIN_H_INCLUDED
|
||||
|
||||
#ifndef __VAES__
|
||||
#if !defined(__VAES__) || !defined(__AVX__)
|
||||
#pragma GCC push_options
|
||||
#pragma GCC target("vaes")
|
||||
#pragma GCC target("vaes,avx")
|
||||
#define __DISABLE_VAES__
|
||||
#endif /* __VAES__ */
|
||||
|
||||
|
|
@ -43,7 +66,7 @@ _mm256_aesenclast_epi128 (__m256i __A, __m256i __B)
|
|||
#endif /* __DISABLE_VAES__ */
|
||||
|
||||
|
||||
#if !defined(__VAES__) || !defined(__AVX512F)
|
||||
#if !defined(__VAES__) || !defined(__AVX512F__)
|
||||
#pragma GCC push_options
|
||||
#pragma GCC target("vaes,avx512f")
|
||||
#define __DISABLE_VAESF__
|
||||
|
|
@ -85,7 +108,7 @@ _mm512_aesenclast_epi128 (__m512i __A, __m512i __B)
|
|||
#pragma GCC pop_options
|
||||
#endif /* __DISABLE_VAES__ */
|
||||
|
||||
#if !defined(__VAES__) || !defined(__AVX512VL)
|
||||
#if !defined(__VAES__) || !defined(__AVX512VL__)
|
||||
#pragma GCC push_options
|
||||
#pragma GCC target("vaes,avx512vl")
|
||||
#define __DISABLE_VAESVL__
|
||||
|
|
|
|||
|
|
@ -1,5 +1,8 @@
|
|||
2018-01-05 Jakub Jelinek <jakub@redhat.com>
|
||||
|
||||
PR target/83604
|
||||
* gcc.target/i386/sse-26.c: New test.
|
||||
|
||||
PR target/83604
|
||||
* gcc.target/i386/pr83604.c: New test.
|
||||
|
||||
|
|
|
|||
5
gcc/testsuite/gcc.target/i386/sse-26.c
Normal file
5
gcc/testsuite/gcc.target/i386/sse-26.c
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse2 -mmmx -mno-sse3 -mno-3dnow -mno-fma -mno-fxsr -mno-xsave -mno-rtm -mno-prfchw -mno-rdseed -mno-adx -mno-prefetchwt1 -mno-clflushopt -mno-xsavec -mno-xsaves -mno-clwb -mno-mwaitx -mno-clzero -mno-pku -mno-rdpid -mno-gfni -mno-ibt -mno-shstk -mno-vaes -mno-vpclmulqdq" } */
|
||||
/* { dg-add-options bind_pic_locally } */
|
||||
|
||||
#include "sse-13.c"
|
||||
Loading…
Add table
Reference in a new issue