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[ARM/AArch64 Testsuite]Add test of vcvt{,_high}_i{f32_f16,f16_f32}

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* gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c: New.
	* lib/target-supports.exp
	(check_effective_target_arm_neon_fp16_hw): New.

From-SVN: r227555
This commit is contained in:
Alan Lawrence 2015-09-08 19:36:41 +00:00 • committed by Alan Lawrence
parent 1fa754dc7b
commit 946e211e90
3 changed files with 119 additions and 0 deletions
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6
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2015-09-08 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c: New.
* lib/target-supports.exp
(check_effective_target_arm_neon_fp16_hw): New.
2015-09-08 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp:

98
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c Normal file
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@ -0,0 +1,98 @@
/* { dg-require-effective-target arm_neon_fp16_hw { target { arm*-*-* } } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#include <math.h>
/* Expected results for vcvt. */
VECT_VAR_DECL (expected,hfloat,32,4) [] = { 0x41800000, 0x41700000,
0x41600000, 0x41500000 };
VECT_VAR_DECL (expected,hfloat,16,4) [] = { 0x3e00, 0x4100, 0x4300, 0x4480 };
/* Expected results for vcvt_high_f32_f16. */
VECT_VAR_DECL (expected_high,hfloat,32,4) [] = { 0xc1400000, 0xc1300000,
0xc1200000, 0xc1100000 };
/* Expected results for vcvt_high_f16_f32. */
VECT_VAR_DECL (expected_high,hfloat,16,8) [] = { 0x4000, 0x4000, 0x4000, 0x4000,
0xcc00, 0xcb80, 0xcb00, 0xca80 };
void
exec_vcvt (void)
{
clean_results ();
#define TEST_MSG vcvt_f32_f16
{
VECT_VAR_DECL (buffer_src, float, 16, 4) [] = { 16.0, 15.0, 14.0, 13.0 };
DECL_VARIABLE (vector_src, float, 16, 4);
VLOAD (vector_src, buffer_src, , float, f, 16, 4);
DECL_VARIABLE (vector_res, float, 32, 4) =
vcvt_f32_f16 (VECT_VAR (vector_src, float, 16, 4));
vst1q_f32 (VECT_VAR (result, float, 32, 4),
VECT_VAR (vector_res, float, 32, 4));
CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
}
#undef TEST_MSG
clean_results ();
#define TEST_MSG vcvt_f16_f32
{
VECT_VAR_DECL (buffer_src, float, 32, 4) [] = { 1.5, 2.5, 3.5, 4.5 };
DECL_VARIABLE (vector_src, float, 32, 4);
VLOAD (vector_src, buffer_src, q, float, f, 32, 4);
DECL_VARIABLE (vector_res, float, 16, 4) =
vcvt_f16_f32 (VECT_VAR (vector_src, float, 32, 4));
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16 ,4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected, "");
}
#undef TEST_MSG
#if defined (__aarch64__)
clean_results ();
#define TEST_MSG "vcvt_high_f32_f16"
{
DECL_VARIABLE (vector_src, float, 16, 8);
VLOAD (vector_src, buffer, q, float, f, 16, 8);
DECL_VARIABLE (vector_res, float, 32, 4);
VECT_VAR (vector_res, float, 32, 4) =
vcvt_high_f32_f16 (VECT_VAR (vector_src, float, 16, 8));
vst1q_f32 (VECT_VAR (result, float, 32, 4),
VECT_VAR (vector_res, float, 32, 4));
CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected_high, "");
}
#undef TEST_MSG
clean_results ();
#define TEST_MSG "vcvt_high_f16_f32"
{
DECL_VARIABLE (vector_low, float, 16, 4);
VDUP (vector_low, , float, f, 16, 4, 2.0);
DECL_VARIABLE (vector_src, float, 32, 4);
VLOAD (vector_src, buffer, q, float, f, 32, 4);
DECL_VARIABLE (vector_res, float, 16, 8) =
vcvt_high_f16_f32 (VECT_VAR (vector_low, float, 16, 4),
VECT_VAR (vector_src, float, 32, 4));
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_high, "");
}
#endif
}
int
main (void)
{
exec_vcvt ();
return 0;
}

15
gcc/testsuite/lib/target-supports.exp
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@ -2807,6 +2807,21 @@ proc check_effective_target_arm_neon_fp16_ok { } {
check_effective_target_arm_neon_fp16_ok_nocache]
}
proc check_effective_target_arm_neon_fp16_hw { } {
if {! [check_effective_target_arm_neon_fp16_ok] } {
return 0
}
global et_arm_neon_fp16_flags
check_runtime_nocache arm_neon_fp16_hw {
int
main (int argc, char **argv)
{
asm ("vcvt.f32.f16 q1, d0");
return 0;
}
} $et_arm_neon_fp16_flags
}
proc add_options_for_arm_neon_fp16 { flags } {
if { ! [check_effective_target_arm_neon_fp16_ok] } {
return "$flags"