RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC]
Allow those funciton apply from a local gcc_options rather than the global options. Preparatory for target attribute, sperate this change for eaiser reivew since it's a NFC. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_convert_vector_bits): Get setting from argument rather than get setting from global setting. (riscv_override_options_internal): New, splited from riscv_override_options, also take a gcc_options argument. (riscv_option_override): Splited most part to riscv_override_options_internal.
This commit is contained in:
Kito Cheng
parent
0363bba87f
commit
9452d13b1a
1 changed files with 52 additions and 41 deletions
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@ -8136,10 +8136,11 @@ riscv_init_machine_status (void)
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/* Return the VLEN value associated with -march.
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TODO: So far we only support length-agnostic value. */
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static poly_uint16
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riscv_convert_vector_bits (void)
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riscv_convert_vector_bits (struct gcc_options *opts)
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{
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int chunk_num;
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if (TARGET_MIN_VLEN > 32)
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int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
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if (min_vlen > 32)
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{
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/* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
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Otherwise we can not include SEW = 64bits.
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@ -8157,7 +8158,7 @@ riscv_convert_vector_bits (void)
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- TARGET_MIN_VLEN = 2048bit: [256,256]
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- TARGET_MIN_VLEN = 4096bit: [512,512]
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FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */
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chunk_num = TARGET_MIN_VLEN / 64;
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chunk_num = min_vlen / 64;
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}
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else
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{
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@ -8176,10 +8177,10 @@ riscv_convert_vector_bits (void)
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to set RVV mode size. The RVV machine modes size are run-time constant if
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TARGET_VECTOR is enabled. The RVV machine modes size remains default
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compile-time constant if TARGET_VECTOR is disabled. */
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if (TARGET_VECTOR)
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if (TARGET_VECTOR_OPTS_P (opts))
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{
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if (riscv_autovec_preference == RVV_FIXED_VLMAX)
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return (int) TARGET_MIN_VLEN / (riscv_bytes_per_vector_chunk * 8);
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if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
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return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
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else
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return poly_uint16 (chunk_num, chunk_num);
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}
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@ -8187,40 +8188,33 @@ riscv_convert_vector_bits (void)
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return 1;
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}
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/* Implement TARGET_OPTION_OVERRIDE. */
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static void
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riscv_option_override (void)
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/* 'Unpack' up the internal tuning structs and update the options
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in OPTS. The caller must have set up selected_tune and selected_arch
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as all the other target-specific codegen decisions are
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derived from them. */
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void
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riscv_override_options_internal (struct gcc_options *opts)
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{
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const struct riscv_tune_info *cpu;
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#ifdef SUBTARGET_OVERRIDE_OPTIONS
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SUBTARGET_OVERRIDE_OPTIONS;
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#endif
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flag_pcc_struct_return = 0;
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if (flag_pic)
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g_switch_value = 0;
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/* The presence of the M extension implies that division instructions
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are present, so include them unless explicitly disabled. */
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if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
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target_flags |= MASK_DIV;
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else if (!TARGET_MUL && TARGET_DIV)
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if (TARGET_MUL_OPTS_P (opts) && (target_flags_explicit & MASK_DIV) == 0)
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opts->x_target_flags |= MASK_DIV;
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else if (!TARGET_MUL_OPTS_P (opts) && TARGET_DIV_OPTS_P (opts))
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error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
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/* Likewise floating-point division and square root. */
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if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
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target_flags |= MASK_FDIV;
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opts->x_target_flags |= MASK_FDIV;
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/* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
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if both -mtune and -mcpu are not given. */
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cpu = riscv_parse_tune (riscv_tune_string ? riscv_tune_string :
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(riscv_cpu_string ? riscv_cpu_string :
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cpu = riscv_parse_tune (opts->x_riscv_tune_string ? opts->x_riscv_tune_string :
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(opts->x_riscv_cpu_string ? opts->x_riscv_cpu_string :
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RISCV_TUNE_STRING_DEFAULT));
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riscv_microarchitecture = cpu->microarchitecture;
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tune_param = optimize_size ? &optimize_size_tune_info : cpu->tune_param;
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tune_param = opts->x_optimize_size ? &optimize_size_tune_info : cpu->tune_param;
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/* Use -mtune's setting for slow_unaligned_access, even when optimizing
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for size. For architectures that trap and emulate unaligned accesses,
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@ -8236,15 +8230,38 @@ riscv_option_override (void)
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if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
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&& cpu->tune_param->slow_unaligned_access)
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target_flags |= MASK_STRICT_ALIGN;
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opts->x_target_flags |= MASK_STRICT_ALIGN;
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/* If the user hasn't specified a branch cost, use the processor's
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default. */
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if (riscv_branch_cost == 0)
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riscv_branch_cost = tune_param->branch_cost;
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if (opts->x_riscv_branch_cost == 0)
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opts->x_riscv_branch_cost = tune_param->branch_cost;
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/* Function to allocate machine-dependent function status. */
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init_machine_status = &riscv_init_machine_status;
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/* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of
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both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16.
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We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */
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if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
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sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
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"'V' Extension");
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/* Convert -march to a chunks count. */
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riscv_vector_chunks = riscv_convert_vector_bits (opts);
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}
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/* Implement TARGET_OPTION_OVERRIDE. */
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static void
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riscv_option_override (void)
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{
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#ifdef SUBTARGET_OVERRIDE_OPTIONS
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SUBTARGET_OVERRIDE_OPTIONS;
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#endif
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flag_pcc_struct_return = 0;
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if (flag_pic)
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g_switch_value = 0;
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if (flag_pic)
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riscv_cmodel = CM_PIC;
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@ -8359,20 +8376,14 @@ riscv_option_override (void)
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riscv_stack_protector_guard_offset = offs;
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}
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/* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of
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both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16.
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We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */
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if (TARGET_MIN_VLEN > 4096)
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sorry (
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"Current RISC-V GCC cannot support VLEN greater than 4096bit for 'V' Extension");
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SET_OPTION_IF_UNSET (&global_options, &global_options_set,
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param_sched_pressure_algorithm,
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SCHED_PRESSURE_MODEL);
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/* Convert -march to a chunks count. */
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riscv_vector_chunks = riscv_convert_vector_bits ();
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/* Function to allocate machine-dependent function status. */
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init_machine_status = &riscv_init_machine_status;
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riscv_override_options_internal (&global_options);
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}
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/* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
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