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rs6000: Enable REE pass by default

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Add ree pass as a default pass for rs6000 target for
O2 and above.

2023-05-16  Ajit Kumar Agarwal  <aagarwa1@linux.ibm.com>

gcc/ChangeLog:

	* common/config/rs6000/rs6000-common.cc: Add REE pass as a
	default rs6000 target pass for O2 and above.
	* doc/invoke.texi: Document -free
This commit is contained in:
“Ajit Kumar Agarwal” 2023-05-16 10:47:15 -05:00
parent 008cbecf62
commit 9417b30499
2 changed files with 4 additions and 2 deletions
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2
gcc/common/config/rs6000/rs6000-common.cc
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@ -34,6 +34,8 @@ static const struct default_options rs6000_option_optimization_table[] =
{ OPT_LEVELS_ALL, OPT_fsplit_wide_types_early, NULL, 1 },
/* Enable -fsched-pressure for first pass instruction scheduling. */
{ OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
/* Enable -free for zero extension and sign extension elimination.*/
{ OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
/* Enable -munroll-only-small-loops with -funroll-loops to unroll small
loops at -O2 and above by default. */
{ OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },

4
gcc/doc/invoke.texi
View file

@ -12455,8 +12455,8 @@ Attempt to remove redundant extension instructions. This is especially
helpful for the x86-64 architecture, which implicitly zero-extends in 64-bit
registers after writing to their lower 32-bit half.
Enabled for Alpha, AArch64 and x86 at levels @option{-O2},
@option{-O3}, @option{-Os}.
Enabled for Alpha, AArch64, PowerPC, RISC-V, SPARC, h83000 and x86 at levels
@option{-O2}, @option{-O3}, @option{-Os}.
@opindex fno-lifetime-dse
@opindex flifetime-dse