Remove amdgcn expcnt waits.
2019-07-31 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (scatter<mode>_insn_1offset<exec_scatter>): Remove s_waitcnt. (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise. (scatter<mode>_insn_2offsets<exec_scatter>): Likewise. * config/gcn/gcn.c (gcn_md_reorg): Add delayeduse and reads to struct ilist. Add nops for delayeduse insns. * config/gcn/gcn.md (delayeduse): New attribute. (*movbi): Remove s_waitcnt from stores. (*mov<mode>_insn): Likewise. (*movti_insn): Likewise. Add delayeduse attribute. (sync_compare_and_swap<mode>_insn): Add delayeduse attribute. (atomic_store<mode>): Remove or adjust s_waitcnt. From-SVN: r273931
This commit is contained in:
Andrew Stubbs
Andrew Stubbs
parent
f86c2e7196
commit
930c55993f
4 changed files with 67 additions and 38 deletions
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@ -1,3 +1,18 @@
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2019-07-31 Andrew Stubbs <ams@codesourcery.com>
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* config/gcn/gcn-valu.md
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(scatter<mode>_insn_1offset<exec_scatter>): Remove s_waitcnt.
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(scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
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(scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
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* config/gcn/gcn.c (gcn_md_reorg): Add delayeduse and reads to
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struct ilist. Add nops for delayeduse insns.
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* config/gcn/gcn.md (delayeduse): New attribute.
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(*movbi): Remove s_waitcnt from stores.
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(*mov<mode>_insn): Likewise.
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(*movti_insn): Likewise. Add delayeduse attribute.
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(sync_compare_and_swap<mode>_insn): Add delayeduse attribute.
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(atomic_store<mode>): Remove or adjust s_waitcnt.
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2019-07-31 Richard Biener <rguenther@suse.de>
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* vr-values.h (vr_values::swap_vr_value): New.
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@ -863,15 +863,12 @@
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if (AS_FLAT_P (as))
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{
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if (TARGET_GCN5_PLUS)
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sprintf (buf, "flat_store%%s2\t%%0, %%2 offset:%%1%s\;"
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"s_waitcnt\texpcnt(0)", glc);
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sprintf (buf, "flat_store%%s2\t%%0, %%2 offset:%%1%s", glc);
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else
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sprintf (buf, "flat_store%%s2\t%%0, %%2%s\;s_waitcnt\texpcnt(0)",
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glc);
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sprintf (buf, "flat_store%%s2\t%%0, %%2%s", glc);
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}
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else if (AS_GLOBAL_P (as))
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sprintf (buf, "global_store%%s2\t%%0, %%2, off offset:%%1%s\;"
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"s_waitcnt\texpcnt(0)", glc);
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sprintf (buf, "global_store%%s2\t%%0, %%2, off offset:%%1%s", glc);
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else
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gcc_unreachable ();
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@ -895,7 +892,7 @@
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{
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addr_space_t as = INTVAL (operands[3]);
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static char buf[200];
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sprintf (buf, "ds_write%%b2\t%%0, %%2 offset:%%1%s\;s_waitcnt\texpcnt(0)",
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sprintf (buf, "ds_write%%b2\t%%0, %%2 offset:%%1%s",
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(AS_GDS_P (as) ? " gds" : ""));
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return buf;
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}
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@ -929,8 +926,8 @@
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/* Work around assembler bug in which a 64-bit register is expected,
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but a 32-bit value would be correct. */
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int reg = REGNO (operands[1]) - FIRST_VGPR_REG;
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sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s\;"
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"s_waitcnt\texpcnt(0)", reg, reg + 1, glc);
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sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s",
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reg, reg + 1, glc);
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}
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else
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gcc_unreachable ();
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@ -4516,7 +4516,9 @@ gcn_md_reorg (void)
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{
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rtx_insn *insn;
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attr_unit unit;
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attr_delayeduse delayeduse;
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HARD_REG_SET writes;
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HARD_REG_SET reads;
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int age;
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} back[max_waits];
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int oldest = 0;
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@ -4535,6 +4537,7 @@ gcn_md_reorg (void)
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attr_type itype = get_attr_type (insn);
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attr_unit iunit = get_attr_unit (insn);
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attr_delayeduse idelayeduse = get_attr_delayeduse (insn);
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HARD_REG_SET ireads, iwrites;
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CLEAR_HARD_REG_SET (ireads);
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CLEAR_HARD_REG_SET (iwrites);
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@ -4610,6 +4613,14 @@ gcn_md_reorg (void)
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(regs, reg_class_contents[(int) VGPR_REGS]))
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nops_rqd = 2 - prev_insn->age;
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}
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/* Store that requires input registers are not overwritten by
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following instruction. */
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if ((prev_insn->age + nops_rqd) < 1
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&& prev_insn->delayeduse == DELAYEDUSE_YES
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&& ((hard_reg_set_intersect_p
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(prev_insn->reads, iwrites))))
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nops_rqd = 1 - prev_insn->age;
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}
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/* Insert the required number of NOPs. */
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@ -4637,7 +4648,9 @@ gcn_md_reorg (void)
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/* Track the current instruction as a previous instruction. */
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back[oldest].insn = insn;
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back[oldest].unit = iunit;
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back[oldest].delayeduse = idelayeduse;
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COPY_HARD_REG_SET (back[oldest].writes, iwrites);
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COPY_HARD_REG_SET (back[oldest].reads, ireads);
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back[oldest].age = 0;
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oldest = (oldest + 1) % max_waits;
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@ -285,6 +285,11 @@
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(define_attr "laneselect" "yes,no" (const_string "no"))
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; Identify instructions that require a "Manually Inserted Wait State" if
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; their inputs are overwritten by subsequent instructions.
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(define_attr "delayeduse" "yes,no" (const_string "no"))
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;; }}}
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;; {{{ Iterators useful across the wole machine description
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@ -475,15 +480,15 @@
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case 6:
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return "s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)";
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case 7:
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return "s_store_dword\t%1, %A0\;s_waitcnt\texpcnt(0)";
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return "s_store_dword\t%1, %A0";
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case 8:
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return "flat_load_dword\t%0, %A1%O1%g1\;s_waitcnt\t0";
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case 9:
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return "flat_store_dword\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)";
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return "flat_store_dword\t%A0, %1%O0%g0";
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case 10:
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return "global_load_dword\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)";
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case 11:
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return "global_store_dword\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)";
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return "global_store_dword\t%A0, %1%O0%g0";
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default:
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gcc_unreachable ();
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}
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@ -506,20 +511,20 @@
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s_movk_i32\t%0, %1
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s_mov_b32\t%0, %1
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s_buffer_load%s0\t%0, s[0:3], %1\;s_waitcnt\tlgkmcnt(0)
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s_buffer_store%s1\t%1, s[0:3], %0\;s_waitcnt\texpcnt(0)
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s_buffer_store%s1\t%1, s[0:3], %0
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s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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s_store_dword\t%1, %A0\;s_waitcnt\texpcnt(0)
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s_store_dword\t%1, %A0
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v_mov_b32\t%0, %1
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v_readlane_b32\t%0, %1, 0
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v_writelane_b32\t%0, %1, 0
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flat_load_dword\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_store_dword\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)
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flat_store_dword\t%A0, %1%O0%g0
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v_mov_b32\t%0, %1
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ds_write_b32\t%A0, %1%O0\;s_waitcnt\texpcnt(0)
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ds_write_b32\t%A0, %1%O0
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ds_read_b32\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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s_mov_b32\t%0, %1
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global_load_dword\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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global_store_dword\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)"
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global_store_dword\t%A0, %1%O0%g0"
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[(set_attr "type" "sop1,sopk,sop1,smem,smem,smem,smem,vop1,vop3a,vop3a,flat,
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flat,vop1,ds,ds,sop1,flat,flat")
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(set_attr "exec" "*,*,*,*,*,*,*,*,none,none,*,*,*,*,*,*,*,*")
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@ -541,12 +546,12 @@
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v_readlane_b32\t%0, %1, 0
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v_writelane_b32\t%0, %1, 0
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flat_load%o1\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_store%s0\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)
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flat_store%s0\t%A0, %1%O0%g0
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v_mov_b32\t%0, %1
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ds_write%b0\t%A0, %1%O0\;s_waitcnt\texpcnt(0)
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ds_write%b0\t%A0, %1%O0
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ds_read%u1\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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global_load%o1\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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global_store%s0\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)"
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global_store%s0\t%A0, %1%O0%g0"
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[(set_attr "type"
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"sop1,sopk,sop1,vop1,vop3a,vop3a,flat,flat,vop1,ds,ds,flat,flat")
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(set_attr "exec" "*,*,*,*,none,none,*,*,*,*,*,*,*")
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@ -564,18 +569,18 @@
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s_mov_b64\t%0, %1
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s_mov_b64\t%0, %1
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#
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s_store_dwordx2\t%1, %A0\;s_waitcnt\texpcnt(0)
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s_store_dwordx2\t%1, %A0
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s_load_dwordx2\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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#
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#
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#
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#
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flat_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_store_dwordx2\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)
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ds_write_b64\t%A0, %1%O0\;s_waitcnt\texpcnt(0)
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flat_store_dwordx2\t%A0, %1%O0%g0
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ds_write_b64\t%A0, %1%O0
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ds_read_b64\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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global_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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global_store_dwordx2\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)"
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global_store_dwordx2\t%A0, %1%O0%g0"
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"(reload_completed && !MEM_P (operands[0]) && !MEM_P (operands[1])
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&& !gcn_sgpr_move_p (operands[0], operands[1]))
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|| (GET_CODE (operands[1]) == CONST_INT && !gcn_constant64_p (operands[1]))"
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@ -617,16 +622,16 @@
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""
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"@
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#
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s_store_dwordx4\t%1, %A0\;s_waitcnt\texpcnt(0)
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s_store_dwordx4\t%1, %A0
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s_load_dwordx4\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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flat_store_dwordx4\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)
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flat_store_dwordx4\t%A0, %1%O0%g0
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flat_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\t0
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#
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#
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#
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global_store_dwordx4\t%A0, %1%O0%g0\;s_waitcnt\texpcnt(0)
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global_store_dwordx4\t%A0, %1%O0%g0
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global_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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ds_write_b128\t%A0, %1%O0\;s_waitcnt\texpcnt(0)
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ds_write_b128\t%A0, %1%O0
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ds_read_b128\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)"
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"reload_completed
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&& REG_P (operands[0])
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@ -647,6 +652,7 @@
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}
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[(set_attr "type" "mult,smem,smem,flat,flat,vmult,vmult,vmult,flat,flat,\
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ds,ds")
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(set_attr "delayeduse" "*,*,yes,*,*,*,*,*,*,*,*,*")
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(set_attr "length" "*,12,12,12,12,*,*,*,12,12,12,12")])
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;; }}}
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@ -1612,7 +1618,8 @@
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global_atomic_cmpswap<X>\t%0, %A1, %2%O1 glc\;s_waitcnt\tvmcnt(0)"
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[(set_attr "type" "smem,flat,flat")
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(set_attr "length" "12")
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(set_attr "gcn_version" "gcn5,*,gcn5")])
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(set_attr "gcn_version" "gcn5,*,gcn5")
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(set_attr "delayeduse" "*,yes,*")])
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(define_insn "sync_compare_and_swap<mode>_lds_insn"
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[(set (match_operand:SIDI 0 "register_operand" "= v")
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@ -1715,14 +1722,11 @@
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switch (which_alternative)
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{
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case 0:
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return "s_dcache_wb_vol\;s_store%o1\t%1, %A0 glc\;"
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"s_waitcnt\texpcnt(0)";
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return "s_dcache_wb_vol\;s_store%o1\t%1, %A0 glc";
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case 1:
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return "buffer_wbinvl1_vol\;flat_store%o1\t%A0, %1%O0 glc\;"
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"s_waitcnt\texpcnt(0)";
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return "buffer_wbinvl1_vol\;flat_store%o1\t%A0, %1%O0 glc";
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case 2:
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return "buffer_wbinvl1_vol\;global_store%o1\t%A0, %1%O0 glc\;"
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"s_waitcnt\texpcnt(0)";
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return "buffer_wbinvl1_vol\;global_store%o1\t%A0, %1%O0 glc";
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}
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break;
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case MEMMODEL_ACQ_REL:
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@ -1732,13 +1736,13 @@
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{
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case 0:
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return "s_dcache_wb_vol\;s_store%o1\t%1, %A0 glc\;"
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"s_waitcnt\texpcnt(0)\;s_dcache_inv_vol";
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"s_waitcnt\tlgkmcnt(0)\;s_dcache_inv_vol";
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case 1:
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return "buffer_wbinvl1_vol\;flat_store%o1\t%A0, %1%O0 glc\;"
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"s_waitcnt\texpcnt(0)\;buffer_wbinvl1_vol";
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"s_waitcnt\t0\;buffer_wbinvl1_vol";
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case 2:
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return "buffer_wbinvl1_vol\;global_store%o1\t%A0, %1%O0 glc\;"
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"s_waitcnt\texpcnt(0)\;buffer_wbinvl1_vol";
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"s_waitcnt\tvmcnt(0)\;buffer_wbinvl1_vol";
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}
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break;
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}
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