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[i386] APX: Fix EGPR usage in several patterns.

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For vextract/insert{if}128 they cannot adopt EGPR in their memory operand, all
related pattern should be adjusted to disable EGPR usage on them.
Also fix a wrong gpr16 attr for insertps.

gcc/ChangeLog:

	* config/i386/sse.md (vec_extract_hi_<mode>): Add noavx512vl
	alternative with attr addr gpr16 and "jm" constraint.
	(vec_extract_hi_<mode>): Likewise for SF vector modes.
	(@vec_extract_hi_<mode>): Likewise.
	(*vec_extractv2ti): Likewise.
	(vec_set_hi_<mode><mask_name>): Likewise.
	* config/i386/mmx.md (@sse4_1_insertps_<mode>): Correct gpr16 attr for
	each alternative.
This commit is contained in:
Hongyu Wang 2023-11-09 13:11:41 +08:00
parent 17cc2e57f4
commit 9251db0dab
2 changed files with 21 additions and 13 deletions
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2
gcc/config/i386/mmx.md
View file

@ -1215,7 +1215,7 @@
}
}
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "addr" "*,*,gpr16")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "type" "sselog")
(set_attr "prefix_data16" "1,1,*")
(set_attr "prefix_extra" "1")

32
gcc/config/i386/sse.md
View file

@ -12049,9 +12049,9 @@
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vec_extract_hi_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=vm")
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=xjm,vm")
(vec_select:<ssehalfvecmode>
(match_operand:VI8F_256 1 "register_operand" "v")
(match_operand:VI8F_256 1 "register_operand" "x,v")
(parallel [(const_int 2) (const_int 3)])))]
"TARGET_AVX"
{
@ -12065,7 +12065,9 @@
else
return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}";
}
[(set_attr "type" "sselog1")
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
@ -12132,7 +12134,7 @@
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vec_extract_hi_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=xm, vm")
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=xjm, vm")
(vec_select:<ssehalfvecmode>
(match_operand:VI4F_256 1 "register_operand" "x, v")
(parallel [(const_int 4) (const_int 5)
@ -12141,7 +12143,8 @@
"@
vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}
vextract<shuffletype>32x4\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "isa" "*, avx512vl")
[(set_attr "isa" "noavx512vl, avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "prefix" "vex, evex")
(set_attr "type" "sselog1")
(set_attr "length_immediate" "1")
@ -12222,7 +12225,7 @@
"operands[1] = gen_lowpart (<ssehalfvecmode>mode, operands[1]);")
(define_insn "@vec_extract_hi_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=xm,vm")
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=xjm,vm")
(vec_select:<ssehalfvecmode>
(match_operand:V16_256 1 "register_operand" "x,v")
(parallel [(const_int 8) (const_int 9)
@ -12236,7 +12239,8 @@
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "isa" "*,avx512vl")
(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "prefix" "vex,evex")
(set_attr "mode" "OI")])
@ -20465,7 +20469,7 @@
})
(define_insn "*vec_extractv2ti"
[(set (match_operand:TI 0 "nonimmediate_operand" "=xm,vm")
[(set (match_operand:TI 0 "nonimmediate_operand" "=xjm,vm")
(vec_select:TI
(match_operand:V2TI 1 "register_operand" "x,v")
(parallel
@ -20477,6 +20481,8 @@
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "prefix" "vex,evex")
(set_attr "mode" "OI")])
@ -27556,12 +27562,12 @@
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vec_set_hi_<mode><mask_name>"
[(set (match_operand:VI8F_256 0 "register_operand" "=v")
[(set (match_operand:VI8F_256 0 "register_operand" "=x,v")
(vec_concat:VI8F_256
(vec_select:<ssehalfvecmode>
(match_operand:VI8F_256 1 "register_operand" "v")
(match_operand:VI8F_256 1 "register_operand" "x,v")
(parallel [(const_int 0) (const_int 1)]))
(match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "vm")))]
(match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "xjm,vm")))]
"TARGET_AVX && <mask_avx512dq_condition>"
{
if (TARGET_AVX512DQ)
@ -27571,7 +27577,9 @@
else
return "vinsert<i128>\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}";
}
[(set_attr "type" "sselog")
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")