sparc.c (const64_operand, [...]): Get it right when HOST_BITS_PER_WIDE_INT is not 64.
* config/sparc/sparc.c (const64_operand, const64_high_operand): Get it right when HOST_BITS_PER_WIDE_INT is not 64. (input_operand): Fixup test for what we accept for constant integers. (sparc_emit_set_const32, sparc_emit_set_symbolic_const64): Give set VOIDmode. (safe_constDI): Remove. (sparc_emit_set_safe_HIGH64, gen_safe_SET64, gen_safe_OR64, gen_safe_XOR64): New functions. (sparc_emit_set_const64_quick1, sparc_emit_set_const64_quick2, sparc_emit_set_const64_longway, sparc_emit_set_const64): Use them. * config/sparc/sparc.md (define_insn xordi3_sp64_dbl): Only make available when HOST_BITS_PER_WIDE_INT is not 64. (define_insn movdi_sp64_dbl, movdi_const64_special): Likewise and move before movdi_insn_sp64 pattern. (define_insn movdi_lo_sum_sp64_dbl, movdi_high_sp64_dbl): Remove. (define_insn sethi_di_medlow, seth44, setm44, sethh): Use symbolic_operand as predicate for second operand. (DImode minus split on arch32, negsi2 expander, one_cmplsi2 expander): Give set VOIDmode. From-SVN: r21724
This commit is contained in:
David S. Miller
David S. Miller
parent
a2cd38a9f8
commit
9208e4b25c
3 changed files with 228 additions and 148 deletions
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@ -1,3 +1,27 @@
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Fri Aug 14 00:34:34 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
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* config/sparc/sparc.c (const64_operand, const64_high_operand):
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Get it right when HOST_BITS_PER_WIDE_INT is not 64.
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(input_operand): Fixup test for what we accept for constant
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integers.
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(sparc_emit_set_const32, sparc_emit_set_symbolic_const64): Give
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set VOIDmode.
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(safe_constDI): Remove.
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(sparc_emit_set_safe_HIGH64, gen_safe_SET64, gen_safe_OR64,
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gen_safe_XOR64): New functions.
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(sparc_emit_set_const64_quick1, sparc_emit_set_const64_quick2,
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sparc_emit_set_const64_longway, sparc_emit_set_const64): Use
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them.
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* config/sparc/sparc.md (define_insn xordi3_sp64_dbl): Only make
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available when HOST_BITS_PER_WIDE_INT is not 64.
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(define_insn movdi_sp64_dbl, movdi_const64_special): Likewise and
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move before movdi_insn_sp64 pattern.
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(define_insn movdi_lo_sum_sp64_dbl, movdi_high_sp64_dbl): Remove.
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(define_insn sethi_di_medlow, seth44, setm44, sethh): Use
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symbolic_operand as predicate for second operand.
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(DImode minus split on arch32, negsi2 expander, one_cmplsi2
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expander): Give set VOIDmode.
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Fri Aug 14 01:45:06 1998 Mumit Khan <khan@xraylith.wisc.edu>
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* i386/cygwin32 (DEFAULT_PCC_STRUCT_RETURN): Define.
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@ -791,22 +791,35 @@ const64_operand (op, mode)
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{
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return ((GET_CODE (op) == CONST_INT
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&& SPARC_SIMM13_P (INTVAL (op)))
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#if HOST_BITS_PER_WIDE_INT != 64
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|| (GET_CODE (op) == CONST_DOUBLE
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&& CONST_DOUBLE_HIGH (op) == 0
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&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
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&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
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&& (CONST_DOUBLE_HIGH (op) ==
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((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
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0xffffffff : 0)))
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#endif
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|| GET_CODE (op) == CONSTANT_P_RTX);
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}
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/* The same, but considering what can fit for a sethi instruction. */
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/* The same, but only for sethi instructions. */
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int
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const64_high_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return ((GET_CODE (op) == CONST_INT
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&& SPARC_SETHI_P (INTVAL (op)))
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&& (INTVAL (op) & 0xfffffc00) != 0
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&& SPARC_SETHI_P (INTVAL (op))
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#if HOST_BITS_PER_WIDE_INT != 64
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/* Must be positive on non-64bit host else the
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optimizer is fooled into thinking that sethi
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sign extends, even though it does not. */
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&& INTVAL (op) >= 0
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#endif
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)
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|| (GET_CODE (op) == CONST_DOUBLE
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&& CONST_DOUBLE_HIGH (op) == 0
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&& (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
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&& SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
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|| GET_CODE (op) == CONSTANT_P_RTX);
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}
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@ -1006,14 +1019,29 @@ input_operand (op, mode)
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/* Allow any one instruction integer constant, and all CONST_INT
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variants when we are working in DImode and !arch64. */
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if (GET_MODE_CLASS (mode) == MODE_INT
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&& GET_CODE (op) == CONST_INT
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&& ((SPARC_SETHI_P (INTVAL (op))
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&& (! TARGET_ARCH64
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|| (INTVAL (op) >= 0)
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|| mode == SImode))
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|| SPARC_SIMM13_P (INTVAL (op))
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|| (mode == DImode
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&& ! TARGET_ARCH64)))
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&& ((GET_CODE (op) == CONST_INT
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&& ((SPARC_SETHI_P (INTVAL (op))
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&& (! TARGET_ARCH64
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|| (INTVAL (op) >= 0)
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|| mode == SImode))
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|| SPARC_SIMM13_P (INTVAL (op))
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|| (mode == DImode
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&& ! TARGET_ARCH64)))
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|| (TARGET_ARCH64
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&& GET_CODE (op) == CONST_DOUBLE
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&& ((CONST_DOUBLE_HIGH (op) == 0
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&& SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
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||
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#if HOST_BITS_PER_WIDE_INT == 64
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(CONST_DOUBLE_HIGH (op) == 0
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&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
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#else
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(SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
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&& (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
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&& CONST_DOUBLE_HIGH (op) == 0)
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|| (CONST_DOUBLE_HIGH (op) == -1)))
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#endif
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))))
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return 1;
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/* Always match this. */
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@ -1084,11 +1112,11 @@ sparc_emit_set_const32 (op0, op1)
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else
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temp = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (mode,
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emit_insn (gen_rtx_SET (VOIDmode,
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temp,
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gen_rtx_HIGH (mode,
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op1)));
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emit_insn (gen_rtx_SET (mode,
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emit_insn (gen_rtx_SET (VOIDmode,
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op0,
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gen_rtx_LO_SUM (mode,
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temp,
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@ -1116,8 +1144,8 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
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sethi %hi(symbol), %temp
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or %temp, %lo(symbol), %reg */
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emit_insn (gen_rtx_SET (DImode, temp1, gen_rtx_HIGH (DImode, op1)));
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emit_insn (gen_rtx_SET (DImode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
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emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
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emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
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break;
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case CM_MEDMID:
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@ -1135,7 +1163,7 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
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or %temp3, %l44(symbol), %reg */
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emit_insn (gen_seth44 (op0, op1));
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emit_insn (gen_setm44 (op0, op0, op1));
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emit_insn (gen_rtx_SET (DImode, temp1,
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emit_insn (gen_rtx_SET (VOIDmode, temp1,
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gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
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emit_insn (gen_setl44 (op0, temp1, op1));
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break;
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@ -1166,9 +1194,9 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
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emit_insn (gen_sethh (op0, op1));
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emit_insn (gen_setlm (temp1, op1));
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emit_insn (gen_sethm (op0, op0, op1));
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emit_insn (gen_rtx_SET (DImode, op0,
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
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emit_insn (gen_rtx_SET (DImode, op0,
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_rtx_PLUS (DImode, op0, temp1)));
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emit_insn (gen_setlo (op0, op0, op1));
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break;
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@ -1209,9 +1237,9 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
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emit_insn (gen_embmedany_textuhi (op0, op1));
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emit_insn (gen_embmedany_texthi (temp1, op1));
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emit_insn (gen_embmedany_textulo (op0, op0, op1));
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emit_insn (gen_rtx_SET (DImode, op0,
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
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emit_insn (gen_rtx_SET (DImode, op0,
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_rtx_PLUS (DImode, op0, temp1)));
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emit_insn (gen_embmedany_textlo (op0, op0, op1));
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}
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@ -1222,19 +1250,63 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
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}
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}
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/* This avoids problems when cross compiling. */
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static rtx safe_constDI PROTO((HOST_WIDE_INT));
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/* These avoid problems when cross compiling. If we do not
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go through all this hair then the optimizer will see
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invalid REG_EQUAL notes or in some cases none at all. */
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static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT));
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static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT));
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static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT));
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static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT));
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static rtx
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safe_constDI(val)
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#if HOST_BITS_PER_WIDE_INT == 64
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#define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
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#define GEN_INT64(__x) GEN_INT (__x)
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#else
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#define GEN_HIGHINT64(__x) \
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gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
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(__x) & 0xfffffc00, 0)
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#define GEN_INT64(__x) \
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gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
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(__x) & 0xffffffff, \
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((__x) & 0x80000000 \
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? 0xffffffff : 0))
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#endif
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/* The optimizer is not to assume anything about exactly
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which bits are set for a HIGH, they are unspecified.
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Unfortunately this leads to many missed optimizations
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during CSE. We mask out the non-HIGH bits, and matches
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a plain movdi, to alleviate this problem. */
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static void
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sparc_emit_set_safe_HIGH64 (dest, val)
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rtx dest;
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HOST_WIDE_INT val;
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{
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#if HOST_BITS_PER_WIDE_INT != 64
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if (val & 0x80000000)
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return immed_double_const (val, 0, DImode);
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else
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#endif
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return GEN_INT (val);
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emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
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}
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static rtx
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gen_safe_SET64 (dest, val)
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rtx dest;
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HOST_WIDE_INT val;
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{
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return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
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}
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static rtx
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gen_safe_OR64 (src, val)
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rtx src;
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HOST_WIDE_INT val;
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{
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return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
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}
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static rtx
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gen_safe_XOR64 (src, val)
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rtx src;
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HOST_WIDE_INT val;
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{
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return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
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}
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/* Worker routines for 64-bit constant formation on arch64.
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@ -1262,21 +1334,14 @@ sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
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else
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high_bits = low_bits;
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emit_insn (gen_rtx_SET (DImode, temp,
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gen_rtx_HIGH (DImode,
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safe_constDI (high_bits))));
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sparc_emit_set_safe_HIGH64 (temp, high_bits);
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if (!is_neg)
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{
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emit_insn (gen_rtx_SET (DImode, op0,
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gen_rtx_LO_SUM (DImode, temp,
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safe_constDI (high_bits))));
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}
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_safe_OR64 (temp, (high_bits & 0x3ff))));
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else
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{ /* as opposed to, say, tricky dick... */
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rtx tricky_bits = safe_constDI (-0x400 | (low_bits & 0x3ff));
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emit_insn (gen_rtx_SET (DImode, op0,
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gen_rtx_XOR (DImode, temp, tricky_bits)));
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}
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_safe_XOR64 (temp,
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(-0x400 | (low_bits & 0x3ff)))));
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}
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static void sparc_emit_set_const64_quick2
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@ -1295,33 +1360,29 @@ sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
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if ((high_bits & 0xfffffc00) != 0)
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{
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emit_insn (gen_rtx_SET (DImode, temp,
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gen_rtx_HIGH (DImode,
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safe_constDI (high_bits))));
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sparc_emit_set_safe_HIGH64 (temp, high_bits);
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if ((high_bits & ~0xfffffc00) != 0)
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emit_insn (gen_rtx_SET (DImode, op0,
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gen_rtx_LO_SUM (DImode, temp,
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safe_constDI (high_bits))));
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_safe_OR64 (temp, (high_bits & 0x3ff))));
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else
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temp2 = temp;
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}
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else
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{
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emit_insn (gen_rtx_SET (DImode, temp, safe_constDI (high_bits)));
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emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high_bits)));
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temp2 = temp;
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}
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/* Now shift it up into place. */
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emit_insn (gen_rtx_SET (DImode, op0,
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_rtx_ASHIFT (DImode, temp2,
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GEN_INT (shift_count))));
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/* If there is a low immediate part piece, finish up by
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putting that in as well. */
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if (low_immediate != 0)
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emit_insn (gen_rtx_SET (DImode, op0,
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gen_rtx_IOR (DImode, op0,
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safe_constDI (low_immediate & 0x3ff))));
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_safe_OR64 (op0, low_immediate)));
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}
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static void sparc_emit_set_const64_longway
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@ -1345,21 +1406,17 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
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if ((high_bits & 0xfffffc00) != 0)
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{
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emit_insn (gen_rtx_SET (DImode,
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temp,
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gen_rtx_HIGH (DImode,
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safe_constDI (high_bits))));
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sparc_emit_set_safe_HIGH64 (temp, high_bits);
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if ((high_bits & ~0xfffffc00) != 0)
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emit_insn (gen_rtx_SET (DImode,
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emit_insn (gen_rtx_SET (VOIDmode,
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sub_temp,
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gen_rtx_LO_SUM (DImode, temp,
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safe_constDI (high_bits))));
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gen_safe_OR64 (temp, (high_bits & 0x3ff))));
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else
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sub_temp = temp;
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}
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else
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{
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emit_insn (gen_rtx_SET (DImode, temp, safe_constDI (high_bits)));
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emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high_bits)));
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sub_temp = temp;
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}
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@ -1369,28 +1426,22 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
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rtx temp3 = gen_reg_rtx (DImode);
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rtx temp4 = gen_reg_rtx (DImode);
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emit_insn (gen_rtx_SET (DImode, temp4,
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emit_insn (gen_rtx_SET (VOIDmode, temp4,
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gen_rtx_ASHIFT (DImode, sub_temp,
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GEN_INT (32))));
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/* Be careful, we must mask the bits here because otherwise
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on a 32-bit host the optimizer will think we're putting
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something like "-1" here and optimize it away. */
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emit_insn (gen_rtx_SET (DImode, temp2,
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gen_rtx_HIGH (DImode,
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safe_constDI (low_bits))));
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sparc_emit_set_safe_HIGH64 (temp2, low_bits);
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if ((low_bits & ~0xfffffc00) != 0)
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emit_insn (gen_rtx_SET (DImode, temp3,
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gen_rtx_LO_SUM (DImode, temp2,
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safe_constDI (low_bits))));
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emit_insn (gen_rtx_SET (DImode, op0,
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emit_insn (gen_rtx_SET (VOIDmode, temp3,
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gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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||||
gen_rtx_PLUS (DImode, temp4, temp3)));
|
||||
}
|
||||
else
|
||||
{
|
||||
rtx low1 = safe_constDI ((low_bits >> (32 - 12)) & 0xfff);
|
||||
rtx low2 = safe_constDI ((low_bits >> (32 - 12 - 12)) & 0xfff);
|
||||
rtx low3 = safe_constDI ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
|
||||
rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
|
||||
rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
|
||||
rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
|
||||
int to_shift = 12;
|
||||
|
||||
/* We are in the middle of reload, so this is really
|
||||
|
|
@ -1398,10 +1449,10 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
|
|||
avoid emmitting truly stupid code. */
|
||||
if (low1 != const0_rtx)
|
||||
{
|
||||
emit_insn (gen_rtx_SET (DImode, op0,
|
||||
emit_insn (gen_rtx_SET (VOIDmode, op0,
|
||||
gen_rtx_ASHIFT (DImode, sub_temp,
|
||||
GEN_INT (to_shift))));
|
||||
emit_insn (gen_rtx_SET (DImode, op0,
|
||||
emit_insn (gen_rtx_SET (VOIDmode, op0,
|
||||
gen_rtx_IOR (DImode, op0, low1)));
|
||||
sub_temp = op0;
|
||||
to_shift = 12;
|
||||
|
|
@ -1412,10 +1463,10 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
|
|||
}
|
||||
if (low2 != const0_rtx)
|
||||
{
|
||||
emit_insn (gen_rtx_SET (DImode, op0,
|
||||
emit_insn (gen_rtx_SET (VOIDmode, op0,
|
||||
gen_rtx_ASHIFT (DImode, sub_temp,
|
||||
GEN_INT (to_shift))));
|
||||
emit_insn (gen_rtx_SET (DImode, op0,
|
||||
emit_insn (gen_rtx_SET (VOIDmode, op0,
|
||||
gen_rtx_IOR (DImode, op0, low2)));
|
||||
sub_temp = op0;
|
||||
to_shift = 8;
|
||||
|
|
@ -1424,11 +1475,11 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
|
|||
{
|
||||
to_shift += 8;
|
||||
}
|
||||
emit_insn (gen_rtx_SET (DImode, op0,
|
||||
emit_insn (gen_rtx_SET (VOIDmode, op0,
|
||||
gen_rtx_ASHIFT (DImode, sub_temp,
|
||||
GEN_INT (to_shift))));
|
||||
if (low3 != const0_rtx)
|
||||
emit_insn (gen_rtx_SET (DImode, op0,
|
||||
emit_insn (gen_rtx_SET (VOIDmode, op0,
|
||||
gen_rtx_IOR (DImode, op0, low3)));
|
||||
/* phew... */
|
||||
}
|
||||
|
|
@ -1482,7 +1533,7 @@ analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
|
|||
as one instruction! */
|
||||
if (lowest_bit_set == -1
|
||||
|| highest_bit_set == -1)
|
||||
abort();
|
||||
abort ();
|
||||
all_bits_between_are_set = 1;
|
||||
for (i = lowest_bit_set; i <= highest_bit_set; i++)
|
||||
{
|
||||
|
|
@ -1525,7 +1576,11 @@ const64_is_2insns (high_bits, low_bits)
|
|||
&& all_bits_between_are_set != 0)
|
||||
return 1;
|
||||
|
||||
if ((highest_bit_set - lowest_bit_set) < 22)
|
||||
if ((highest_bit_set - lowest_bit_set) < 21)
|
||||
return 1;
|
||||
|
||||
if (high_bits == 0
|
||||
|| high_bits == 0xffffffff)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
|
|
@ -1553,7 +1608,7 @@ create_simple_focus_bits (high_bits, low_bits, highest_bit_set, lowest_bit_set,
|
|||
hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
|
||||
}
|
||||
if (hi & lo)
|
||||
abort();
|
||||
abort ();
|
||||
return (hi | lo);
|
||||
}
|
||||
|
||||
|
|
@ -1577,7 +1632,7 @@ sparc_emit_set_const64 (op0, op1)
|
|||
|| GET_CODE (op0) != REG
|
||||
|| (REGNO (op0) >= SPARC_FIRST_FP_REG
|
||||
&& REGNO (op0) <= SPARC_LAST_V9_FP_REG))
|
||||
abort();
|
||||
abort ();
|
||||
|
||||
if (GET_CODE (op1) != CONST_DOUBLE
|
||||
&& GET_CODE (op1) != CONST_INT)
|
||||
|
|
@ -1641,7 +1696,7 @@ sparc_emit_set_const64 (op0, op1)
|
|||
&& all_bits_between_are_set != 0)
|
||||
|| ((highest_bit_set - lowest_bit_set) < 12))
|
||||
{
|
||||
rtx the_const = constm1_rtx;
|
||||
HOST_WIDE_INT the_const = -1;
|
||||
int shift = lowest_bit_set;
|
||||
|
||||
if (highest_bit_set == lowest_bit_set)
|
||||
|
|
@ -1650,29 +1705,29 @@ sparc_emit_set_const64 (op0, op1)
|
|||
can be done in one instruction. */
|
||||
if (lowest_bit_set < 32)
|
||||
abort ();
|
||||
the_const = const1_rtx;
|
||||
the_const = 1;
|
||||
}
|
||||
else if (all_bits_between_are_set == 0)
|
||||
{
|
||||
the_const =
|
||||
safe_constDI (create_simple_focus_bits (high_bits, low_bits,
|
||||
highest_bit_set,
|
||||
lowest_bit_set, 0));
|
||||
create_simple_focus_bits (high_bits, low_bits,
|
||||
highest_bit_set,
|
||||
lowest_bit_set, 0);
|
||||
}
|
||||
else if (lowest_bit_set == 0)
|
||||
shift = -(64 - highest_bit_set);
|
||||
emit_insn (gen_rtx_SET (DImode, temp, the_const));
|
||||
shift = -(63 - highest_bit_set);
|
||||
|
||||
emit_insn (gen_safe_SET64 (temp, the_const));
|
||||
if (shift > 0)
|
||||
emit_insn (gen_rtx_SET (DImode,
|
||||
emit_insn (gen_rtx_SET (VOIDmode,
|
||||
op0,
|
||||
gen_rtx_ASHIFT (DImode,
|
||||
temp,
|
||||
GEN_INT (shift))));
|
||||
else if (shift < 0)
|
||||
emit_insn (gen_rtx_SET (DImode,
|
||||
emit_insn (gen_rtx_SET (VOIDmode,
|
||||
op0,
|
||||
gen_rtx_ASHIFTRT (DImode,
|
||||
gen_rtx_LSHIFTRT (DImode,
|
||||
temp,
|
||||
GEN_INT (-shift))));
|
||||
else
|
||||
|
|
@ -1691,22 +1746,21 @@ sparc_emit_set_const64 (op0, op1)
|
|||
unsigned HOST_WIDE_INT focus_bits =
|
||||
create_simple_focus_bits (high_bits, low_bits,
|
||||
highest_bit_set, lowest_bit_set, 10);
|
||||
emit_insn (gen_rtx_SET (DImode,
|
||||
temp,
|
||||
gen_rtx_HIGH (DImode, safe_constDI (focus_bits))));
|
||||
sparc_emit_set_safe_HIGH64 (temp, focus_bits);
|
||||
|
||||
/* If lowest_bit_set == 10 then a sethi alone could have done it. */
|
||||
if (lowest_bit_set < 10)
|
||||
emit_insn (gen_rtx_SET (DImode,
|
||||
emit_insn (gen_rtx_SET (VOIDmode,
|
||||
op0,
|
||||
gen_rtx_ASHIFTRT (DImode, temp,
|
||||
gen_rtx_LSHIFTRT (DImode, temp,
|
||||
GEN_INT (10 - lowest_bit_set))));
|
||||
else if (lowest_bit_set >= 10)
|
||||
emit_insn (gen_rtx_SET (DImode,
|
||||
else if (lowest_bit_set > 10)
|
||||
emit_insn (gen_rtx_SET (VOIDmode,
|
||||
op0,
|
||||
gen_rtx_ASHIFT (DImode, temp,
|
||||
GEN_INT (lowest_bit_set - 10))));
|
||||
else
|
||||
abort();
|
||||
abort ();
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1747,13 +1801,13 @@ sparc_emit_set_const64 (op0, op1)
|
|||
|| (((~high_bits) & 0xffffffff) == 0xffffffff
|
||||
&& ((~low_bits) & 0x80000000) != 0))
|
||||
{
|
||||
rtx fast_int = GEN_INT (~low_bits & 0xffffffff);
|
||||
HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
|
||||
|
||||
if (input_operand (fast_int, DImode))
|
||||
emit_insn (gen_rtx_SET (DImode, temp,
|
||||
safe_constDI (~low_bits & 0xffffffff)));
|
||||
if (SPARC_SETHI_P (fast_int)
|
||||
|| SPARC_SIMM13_P (((int)fast_int)))
|
||||
emit_insn (gen_safe_SET64 (temp, fast_int));
|
||||
else
|
||||
sparc_emit_set_const64 (temp, fast_int);
|
||||
sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1762,16 +1816,16 @@ sparc_emit_set_const64 (op0, op1)
|
|||
negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
|
||||
(((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
|
||||
#else
|
||||
negated_const = gen_rtx_CONST_DOUBLE (DImode, NULL_RTX,
|
||||
negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
|
||||
(~low_bits) & 0xfffffc00,
|
||||
(~high_bits) & 0xffffffff);
|
||||
#endif
|
||||
sparc_emit_set_const64 (temp, negated_const);
|
||||
}
|
||||
emit_insn (gen_rtx_SET (DImode,
|
||||
emit_insn (gen_rtx_SET (VOIDmode,
|
||||
op0,
|
||||
gen_rtx_XOR (DImode, temp,
|
||||
safe_constDI (-0x400 | trailing_bits))));
|
||||
gen_safe_XOR64 (temp,
|
||||
(-0x400 | trailing_bits))));
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1786,14 +1840,14 @@ sparc_emit_set_const64 (op0, op1)
|
|||
/* We can't get here in this state. */
|
||||
if (highest_bit_set < 32
|
||||
|| lowest_bit_set >= 32)
|
||||
abort();
|
||||
abort ();
|
||||
|
||||
/* So what we know is that the set bits straddle the
|
||||
middle of the 64-bit word. */
|
||||
hi = (low_bits >> lowest_bit_set);
|
||||
lo = (high_bits << (32 - lowest_bit_set));
|
||||
if (hi & lo)
|
||||
abort();
|
||||
abort ();
|
||||
focus_bits = (hi | lo);
|
||||
sparc_emit_set_const64_quick2 (op0, temp,
|
||||
focus_bits, 0,
|
||||
|
|
@ -3685,7 +3739,7 @@ function_arg_record_value (type, mode, slotno, named, regbase)
|
|||
nregs = SPARC_INT_ARG_MAX - slotno;
|
||||
}
|
||||
if (nregs == 0)
|
||||
abort();
|
||||
abort ();
|
||||
|
||||
parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
|
||||
|
||||
|
|
@ -4489,7 +4543,7 @@ epilogue_renumber (where)
|
|||
|
||||
default:
|
||||
debug_rtx (*where);
|
||||
abort();
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4611,7 +4665,7 @@ sparc_splitdi_legitimate(reg, mem)
|
|||
|
||||
/* Punt if we are here by mistake. */
|
||||
if (! reload_completed)
|
||||
abort();
|
||||
abort ();
|
||||
|
||||
/* We must have an offsettable memory reference. */
|
||||
if (! offsettable_memref_p (mem))
|
||||
|
|
|
|||
|
|
@ -2328,6 +2328,24 @@
|
|||
[(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
|
||||
(set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")])
|
||||
|
||||
(define_insn "*movdi_sp64_dbl"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(match_operand:DI 1 "const64_operand" ""))]
|
||||
"(TARGET_ARCH64
|
||||
&& HOST_BITS_PER_WIDE_INT != 64)"
|
||||
"mov\\t%1, %0"
|
||||
[(set_attr "type" "move")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
(define_insn "*movdi_const64_special"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(match_operand:DI 1 "const64_high_operand" ""))]
|
||||
"(TARGET_ARCH64
|
||||
&& HOST_BITS_PER_WIDE_INT != 64)"
|
||||
"sethi\\t%%hi(%a1), %0"
|
||||
[(set_attr "type" "move")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
(define_insn "*movdi_insn_sp64"
|
||||
[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,m,?e,?e,?m")
|
||||
(match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e"))]
|
||||
|
|
@ -2346,7 +2364,7 @@
|
|||
[(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
;; The following two are generated by sparc_emit_set_const64
|
||||
;; The following are generated by sparc_emit_set_const64
|
||||
(define_insn "*movdi_lo_sum_sp64_cint"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
||||
|
|
@ -2356,15 +2374,6 @@
|
|||
[(set_attr "type" "ialu")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
(define_insn "*movdi_lo_sum_sp64_dbl"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
||||
(match_operand:DI 2 "const64_operand" "")))]
|
||||
"TARGET_ARCH64"
|
||||
"or\\t%1, %%lo(%a2), %0"
|
||||
[(set_attr "type" "ialu")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
(define_insn "*movdi_high_sp64_cint"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (match_operand:DI 1 "const_int_operand" "in")))]
|
||||
|
|
@ -2373,14 +2382,6 @@
|
|||
[(set_attr "type" "move")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
(define_insn "*movdi_high_sp64_dbl"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (match_operand:DI 1 "const64_high_operand" "")))]
|
||||
"TARGET_ARCH64"
|
||||
"sethi\\t%%hi(%a1), %0"
|
||||
[(set_attr "type" "move")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
;; ??? revisit this...
|
||||
(define_insn "move_label_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
|
|
@ -2425,7 +2426,7 @@
|
|||
|
||||
(define_insn "*sethi_di_medlow"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (match_operand:DI 1 "" "")))]
|
||||
(high:DI (match_operand:DI 1 "symbolic_operand" "")))]
|
||||
"TARGET_CM_MEDLOW && check_pic (1)"
|
||||
"sethi\\t%%hi(%a1), %0"
|
||||
[(set_attr "type" "move")
|
||||
|
|
@ -2441,7 +2442,7 @@
|
|||
|
||||
(define_insn "seth44"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (unspec:DI [(match_operand:DI 1 "" "")] 6)))]
|
||||
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))]
|
||||
"TARGET_CM_MEDMID"
|
||||
"sethi\\t%%h44(%a1), %0"
|
||||
[(set_attr "type" "move")
|
||||
|
|
@ -2450,7 +2451,7 @@
|
|||
(define_insn "setm44"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 2 "" "")] 7)))]
|
||||
(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))]
|
||||
"TARGET_CM_MEDMID"
|
||||
"or\\t%1, %%m44(%a2), %0"
|
||||
[(set_attr "type" "move")
|
||||
|
|
@ -2466,7 +2467,7 @@
|
|||
|
||||
(define_insn "sethh"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (unspec:DI [(match_operand:DI 1 "" "")] 9)))]
|
||||
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))]
|
||||
"TARGET_CM_MEDANY"
|
||||
"sethi\\t%%hh(%a1), %0"
|
||||
[(set_attr "type" "move")
|
||||
|
|
@ -2474,7 +2475,7 @@
|
|||
|
||||
(define_insn "setlm"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (unspec:DI [(match_operand:DI 1 "" "")] 10)))]
|
||||
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))]
|
||||
"TARGET_CM_MEDANY"
|
||||
"sethi\\t%%lm(%a1), %0"
|
||||
[(set_attr "type" "move")
|
||||
|
|
@ -4673,7 +4674,7 @@
|
|||
if ((lowp == const0_rtx)
|
||||
&& (operands[0] == operands[1]))
|
||||
{
|
||||
emit_insn (gen_rtx_SET (SImode,
|
||||
emit_insn (gen_rtx_SET (VOIDmode,
|
||||
gen_highpart (SImode, operands[0]),
|
||||
gen_rtx_MINUS (SImode,
|
||||
gen_highpart (SImode, operands[1]),
|
||||
|
|
@ -5652,7 +5653,8 @@
|
|||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(xor:DI (match_operand:DI 1 "register_operand" "%r")
|
||||
(match_operand:DI 2 "const64_operand" "")))]
|
||||
"TARGET_ARCH64"
|
||||
"(TARGET_ARCH64
|
||||
&& HOST_BITS_PER_WIDE_INT != 64)"
|
||||
"xor\\t%1, %2, %0"
|
||||
[(set_attr "type" "ialu")
|
||||
(set_attr "length" "1")])
|
||||
|
|
@ -5971,8 +5973,8 @@
|
|||
{
|
||||
rtx zero_reg = gen_reg_rtx (SImode);
|
||||
|
||||
emit_insn (gen_rtx_SET (SImode, zero_reg, const0_rtx));
|
||||
emit_insn (gen_rtx_SET (SImode, operands[0],
|
||||
emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx));
|
||||
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
|
||||
gen_rtx_MINUS (SImode, zero_reg,
|
||||
operands[1])));
|
||||
DONE;
|
||||
|
|
@ -6078,8 +6080,8 @@
|
|||
{
|
||||
rtx zero_reg = gen_reg_rtx (SImode);
|
||||
|
||||
emit_insn (gen_rtx_SET (SImode, zero_reg, const0_rtx));
|
||||
emit_insn (gen_rtx_SET (SImode,
|
||||
emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx));
|
||||
emit_insn (gen_rtx_SET (VOIDmode,
|
||||
operands[0],
|
||||
gen_rtx_NOT (SImode,
|
||||
gen_rtx_XOR (SImode,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue