From 90e0c734fa7ee61bacefcbdccfa0c22dad59c579 Mon Sep 17 00:00:00 2001 From: James E Wilson Date: Wed, 17 Aug 2005 14:43:49 -0700 Subject: [PATCH] Fix misoptimization of mask and shift. PR target/21684 * config/mcore/mcore.h (SHIFT_COUNT_TRUNCATED): Define to 0. Co-Authored-By: Kevin Winchester From-SVN: r103228 --- gcc/ChangeLog | 6 ++++++ gcc/config/mcore/mcore.h | 10 ++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6fa630143db..06898fded44 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2005-08-17 James E Wilson + Kevin Winchester + + PR target/21684 + * config/mcore/mcore.h (SHIFT_COUNT_TRUNCATED): Define to 0. + 2005-08-17 Uros Bizjak PR target/23268 diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index f0afa88191b..d9960dc0edb 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -820,12 +820,10 @@ extern const enum reg_class reg_class_from_letter[]; /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES -/* Immediate shift counts are truncated by the output routines (or was it - the assembler?). Shift counts in a register are truncated by ARM. Note - that the native compiler puts too large (> 32) immediate shift counts - into a register and shifts by the register, letting the ARM decide what - to do instead of doing that itself. */ -#define SHIFT_COUNT_TRUNCATED 1 +/* Shift counts are truncated to 6-bits (0 to 63) instead of the expected + 5-bits, so we can not define SHIFT_COUNT_TRUNCATED to true for this + target. */ +#define SHIFT_COUNT_TRUNCATED 0 /* All integers have the same format so truncation is easy. */ #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1