i386: Optimize pmovmskb on inverted vector to inversion of pmovmskb result [PR98461]
The following patch adds combine splitters to optimize:
- vpcmpeqd %ymm1, %ymm1, %ymm1
- vpandn %ymm1, %ymm0, %ymm0
vpmovmskb %ymm0, %eax
+ notl %eax
etc. (for vectors with less than 32 elements with xorl instead of notl).
2020-12-30 Jakub Jelinek <jakub@redhat.com>
PR target/98461
* config/i386/sse.md (<sse2_avx2>_pmovmskb): Add splitters
for pmovmskb of NOT vector.
* gcc.target/i386/sse2-pr98461.c: New test.
* gcc.target/i386/avx2-pr98461.c: New test.
This commit is contained in:
Jakub Jelinek
parent
86b3edf1ff
commit
8f7941ca37
3 changed files with 151 additions and 0 deletions
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@ -16099,6 +16099,53 @@
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "SI")])
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(define_split
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[(set (match_operand:SI 0 "register_operand")
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(unspec:SI
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[(not:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand"))]
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UNSPEC_MOVMSK))]
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"TARGET_SSE2"
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[(set (match_dup 2)
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(unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
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(set (match_dup 0) (match_dup 3))]
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{
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operands[2] = gen_reg_rtx (SImode);
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if (GET_MODE_NUNITS (<MODE>mode) == 32)
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operands[3] = gen_rtx_NOT (SImode, operands[2]);
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else
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{
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operands[3]
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= gen_int_mode ((HOST_WIDE_INT_1 << GET_MODE_NUNITS (<MODE>mode)) - 1,
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SImode);
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operands[3] = gen_rtx_XOR (SImode, operands[2], operands[3]);
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}
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})
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(define_split
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[(set (match_operand:SI 0 "register_operand")
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(unspec:SI
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[(subreg:VI1_AVX2 (not (match_operand 1 "register_operand")) 0)]
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UNSPEC_MOVMSK))]
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"TARGET_SSE2
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&& GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_VECTOR_INT
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&& GET_MODE_SIZE (GET_MODE (operands[1])) == <MODE_SIZE>"
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[(set (match_dup 2)
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(unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
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(set (match_dup 0) (match_dup 3))]
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{
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operands[2] = gen_reg_rtx (SImode);
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operands[1] = gen_lowpart (<MODE>mode, operands[1]);
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if (GET_MODE_NUNITS (<MODE>mode) == 32)
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operands[3] = gen_rtx_NOT (SImode, operands[2]);
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else
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{
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operands[3]
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= gen_int_mode ((HOST_WIDE_INT_1 << GET_MODE_NUNITS (<MODE>mode)) - 1,
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SImode);
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operands[3] = gen_rtx_XOR (SImode, operands[2], operands[3]);
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}
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})
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(define_insn_and_split "*<sse2_avx2>_pmovmskb_lt"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI
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54
gcc/testsuite/gcc.target/i386/avx2-pr98461.c
Normal file
54
gcc/testsuite/gcc.target/i386/avx2-pr98461.c
Normal file
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@ -0,0 +1,54 @@
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/* PR target/98461 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx2 -masm=att" } */
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/* { dg-final { scan-assembler-times "\tvpmovmskb\t" 6 } } */
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/* { dg-final { scan-assembler-times "\tnotl\t" 6 } } */
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/* { dg-final { scan-assembler-not "\tvpcmpeq" } } */
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/* { dg-final { scan-assembler-not "\tvpxor" } } */
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/* { dg-final { scan-assembler-not "\tvpandn" } } */
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#include <x86intrin.h>
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int
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f1 (__m256i x)
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{
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return ~_mm256_movemask_epi8 (x);
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}
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int
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f2 (__m256i x)
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{
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return _mm256_movemask_epi8 (_mm256_andnot_si256 (x, _mm256_set1_epi8 (255)));
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}
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int
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f3 (__v32qi x)
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{
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x ^= (__v32qi) { -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1 };
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return _mm256_movemask_epi8 ((__m256i) x);
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}
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long
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f4 (__m256i x)
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{
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return (unsigned) ~_mm256_movemask_epi8 (x);
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}
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long
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f5 (__m256i x)
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{
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return (unsigned) _mm256_movemask_epi8 (_mm256_andnot_si256 (x, _mm256_set1_epi8 (255)));
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}
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long
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f6 (__v32qi x)
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{
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x ^= (__v32qi) { -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1 };
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return (unsigned) _mm256_movemask_epi8 ((__m256i) x);
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}
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50
gcc/testsuite/gcc.target/i386/sse2-pr98461.c
Normal file
50
gcc/testsuite/gcc.target/i386/sse2-pr98461.c
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@ -0,0 +1,50 @@
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/* PR target/98461 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -msse2 -mno-sse3 -masm=att" } */
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/* { dg-final { scan-assembler-times "\tpmovmskb\t" 6 } } */
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/* { dg-final { scan-assembler-times "\txorl\t" 6 } } */
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/* { dg-final { scan-assembler-not "\tpcmpeq" } } */
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/* { dg-final { scan-assembler-not "\tpxor" } } */
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/* { dg-final { scan-assembler-not "\tpandn" } } */
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#include <x86intrin.h>
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int
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f1 (__m128i x)
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{
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return _mm_movemask_epi8 (x) ^ 65535;
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}
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int
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f2 (__m128i x)
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{
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return _mm_movemask_epi8 (_mm_andnot_si128 (x, _mm_set1_epi8 (255)));
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}
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int
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f3 (__v16qi x)
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{
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x ^= (__v16qi) { -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1 };
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return _mm_movemask_epi8 ((__m128i) x);
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}
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long
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f4 (__m128i x)
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{
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return (unsigned) (_mm_movemask_epi8 (x) ^ 65535);
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}
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long
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f5 (__m128i x)
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{
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return (unsigned) _mm_movemask_epi8 (_mm_andnot_si128 (x, _mm_set1_epi8 (255)));
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}
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long
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f6 (__v16qi x)
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{
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x ^= (__v16qi) { -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1 };
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return (unsigned) _mm_movemask_epi8 ((__m128i) x);
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}
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