[2/4] ARMv8.2-A testsuite for new data movement intrinsics
gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (FP16_SUPPORTED): Enable AArch64. * gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Add support for vdup*_laneq. * gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c: New. * gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: New. * gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: New. * gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: New. From-SVN: r240922
This commit is contained in:
Jiong Wang
Jiong Wang
parent
6e49f922a6
commit
8f3edb0732
7 changed files with 1053 additions and 15 deletions
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@ -1,3 +1,14 @@
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2016-10-10 Jiong Wang <jiong.wang@arm.com>
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* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (FP16_SUPPORTED):
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Enable AArch64.
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* gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Add support for
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vdup*_laneq.
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* gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c: New.
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* gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: New.
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* gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: New.
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* gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: New.
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2016-10-10 Matthew Wahab <matthew.wahab@arm.com>
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Jiong Wang <jiong.wang@arm.com>
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@ -17,9 +17,8 @@ extern void *memcpy(void *, const void *, size_t);
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extern size_t strlen(const char *);
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/* Helper macro to select FP16 tests. */
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#if (!defined (__aarch64__) \
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&& (defined (__ARM_FP16_FORMAT_IEEE) \
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|| defined (__ARM_FP16_FORMAT_ALTERNATIVE)))
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#if (defined (__ARM_FP16_FORMAT_IEEE) \
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|| defined (__ARM_FP16_FORMAT_ALTERNATIVE))
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#define FP16_SUPPORTED (1)
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#else
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#undef FP16_SUPPORTED
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@ -520,17 +519,6 @@ static void clean_results (void)
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/* Helpers to initialize vectors. */
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#define VDUP(VAR, Q, T1, T2, W, N, V) \
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VECT_VAR(VAR, T1, W, N) = vdup##Q##_n_##T2##W(V)
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#if (defined (__aarch64__) \
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&& (defined (__ARM_FP16_FORMAT_IEEE) \
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|| defined (__ARM_FP16_FORMAT_ALTERNATIVE)))
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/* Work around that there is no vdup_n_f16 intrinsic. */
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#define vdup_n_f16(VAL) \
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__extension__ \
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({ \
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float16_t f = VAL; \
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vld1_dup_f16(&f); \
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})
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#endif
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#define VSET_LANE(VAR, Q, T1, T2, W, N, L, V) \
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VECT_VAR(VAR, T1, W, N) = vset##Q##_lane_##T2##W(V, \
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@ -56,7 +56,7 @@ VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xca80, 0xca80,
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1700000, 0xc1700000,
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0xc1700000, 0xc1700000 };
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#define TEST_MSG "VDUP_LANE/VDUP_LANEQ"
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#define TEST_MSG "VDUP_LANE/VDUPQ_LANE"
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void exec_vdup_lane (void)
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{
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/* Basic test: vec1=vdup_lane(vec2, lane), then store the result. */
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@ -114,6 +114,123 @@ void exec_vdup_lane (void)
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#else
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CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
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#endif
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#if defined (__aarch64__)
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#undef TEST_MSG
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#define TEST_MSG "VDUP_LANEQ/VDUPQ_LANEQ"
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/* Expected results for vdup*_laneq tests. */
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VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd,
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0xfd, 0xfd, 0xfd, 0xfd };
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VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
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VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
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VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 };
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VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff };
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VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
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VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
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VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 };
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VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7,
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0xf7, 0xf7, 0xf7, 0xf7 };
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VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
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VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
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#if defined (FP16_SUPPORTED)
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VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80,
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0xca80, 0xca80 };
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#endif
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VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb,
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0xfb, 0xfb, 0xfb, 0xfb,
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0xfb, 0xfb, 0xfb, 0xfb,
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0xfb, 0xfb, 0xfb, 0xfb };
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VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff7, 0xfff7, 0xfff7, 0xfff7,
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0xfff7, 0xfff7, 0xfff7, 0xfff7 };
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VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
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0xfffffff1, 0xfffffff1 };
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VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0,
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0xfffffffffffffff0 };
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VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf5, 0xf5, 0xf5, 0xf5,
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0xf5, 0xf5, 0xf5, 0xf5,
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0xf5, 0xf5, 0xf5, 0xf5,
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0xf5, 0xf5, 0xf5, 0xf5 };
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VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
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0xfff1, 0xfff1, 0xfff1, 0xfff1 };
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VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff0, 0xfffffff0,
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0xfffffff0, 0xfffffff0 };
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VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0,
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0xfffffffffffffff0 };
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VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf5, 0xf5, 0xf5, 0xf5,
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0xf5, 0xf5, 0xf5, 0xf5,
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0xf5, 0xf5, 0xf5, 0xf5,
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0xf5, 0xf5, 0xf5, 0xf5 };
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VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
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0xfff1, 0xfff1, 0xfff1, 0xfff1 };
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#if defined (FP16_SUPPORTED)
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VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xc880, 0xc880,
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0xc880, 0xc880,
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0xc880, 0xc880,
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0xc880, 0xc880 };
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#endif
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VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0xc1700000,
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0xc1700000, 0xc1700000 };
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/* Clean all results for vdup*_laneq tests. */
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clean_results ();
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/* Basic test: vec1=vdup_lane(vec2, lane), then store the result. */
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#define TEST_VDUP_LANEQ(Q, T1, T2, W, N, N2, L) \
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VECT_VAR(vector_res, T1, W, N) = \
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vdup##Q##_laneq_##T2##W(VECT_VAR(vector, T1, W, N2), L); \
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vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
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/* Input vector can only have 64 bits. */
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DECL_VARIABLE_128BITS_VARIANTS(vector);
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clean_results ();
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TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vector, buffer);
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#if defined (FP16_SUPPORTED)
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VLOAD(vector, buffer, q, float, f, 16, 8);
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#endif
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VLOAD(vector, buffer, q, float, f, 32, 4);
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/* Choose lane arbitrarily. */
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TEST_VDUP_LANEQ(, int, s, 8, 8, 16, 13);
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TEST_VDUP_LANEQ(, int, s, 16, 4, 8, 2);
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TEST_VDUP_LANEQ(, int, s, 32, 2, 4, 1);
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TEST_VDUP_LANEQ(, int, s, 64, 1, 2, 0);
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TEST_VDUP_LANEQ(, uint, u, 8, 8, 16, 15);
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TEST_VDUP_LANEQ(, uint, u, 16, 4, 8, 3);
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TEST_VDUP_LANEQ(, uint, u, 32, 2, 4, 1);
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TEST_VDUP_LANEQ(, uint, u, 64, 1, 2, 0);
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TEST_VDUP_LANEQ(, poly, p, 8, 8, 16, 7);
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TEST_VDUP_LANEQ(, poly, p, 16, 4, 8, 3);
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#if defined (FP16_SUPPORTED)
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TEST_VDUP_LANEQ(, float, f, 16, 4, 8, 3);
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#endif
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TEST_VDUP_LANEQ(, float, f, 32, 2, 4, 1);
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TEST_VDUP_LANEQ(q, int, s, 8, 16, 16, 11);
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TEST_VDUP_LANEQ(q, int, s, 16, 8, 8, 7);
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TEST_VDUP_LANEQ(q, int, s, 32, 4, 4, 1);
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TEST_VDUP_LANEQ(q, int, s, 64, 2, 2, 0);
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TEST_VDUP_LANEQ(q, uint, u, 8, 16, 16, 5);
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TEST_VDUP_LANEQ(q, uint, u, 16, 8, 8, 1);
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TEST_VDUP_LANEQ(q, uint, u, 32, 4, 4, 0);
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TEST_VDUP_LANEQ(q, uint, u, 64, 2, 2, 0);
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TEST_VDUP_LANEQ(q, poly, p, 8, 16, 16, 5);
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TEST_VDUP_LANEQ(q, poly, p, 16, 8, 8, 1);
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#if defined (FP16_SUPPORTED)
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TEST_VDUP_LANEQ(q, float, f, 16, 8, 8, 7);
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#endif
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TEST_VDUP_LANEQ(q, float, f, 32, 4, 4, 1);
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CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
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#if defined (FP16_SUPPORTED)
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CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
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CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
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#endif
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#endif /* __aarch64__. */
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}
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int main (void)
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137
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c
Normal file
137
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c
Normal file
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@ -0,0 +1,137 @@
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/* { dg-do run } */
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/* { dg-skip-if "" { arm*-*-* } } */
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#include <arm_neon.h>
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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#define A -16
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#define B -15
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#define C -14
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#define D -13
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#define E -12
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#define F -11
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#define G -10
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#define H -9
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#define F16_C(a) ((__fp16) a)
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#define AF F16_C (A)
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#define BF F16_C (B)
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#define CF F16_C (C)
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#define DF F16_C (D)
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#define EF F16_C (E)
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#define FF F16_C (F)
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#define GF F16_C (G)
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#define HF F16_C (H)
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#define S16_C(a) ((int16_t) a)
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#define AS S16_C (A)
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#define BS S16_C (B)
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#define CS S16_C (C)
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#define DS S16_C (D)
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#define ES S16_C (E)
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#define FS S16_C (F)
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#define GS S16_C (G)
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#define HS S16_C (H)
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#define U16_C(a) ((int16_t) a)
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#define AU U16_C (A)
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#define BU U16_C (B)
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#define CU U16_C (C)
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#define DU U16_C (D)
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#define EU U16_C (E)
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#define FU U16_C (F)
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#define GU U16_C (G)
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#define HU U16_C (H)
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#define P16_C(a) ((poly16_t) a)
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#define AP P16_C (A)
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#define BP P16_C (B)
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#define CP P16_C (C)
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#define DP P16_C (D)
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#define EP P16_C (E)
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#define FP P16_C (F)
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#define GP P16_C (G)
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#define HP P16_C (H)
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/* Expected results for vduph_lane. */
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float16_t expected_f16 = AF;
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int16_t expected_s16 = DS;
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uint16_t expected_u16 = BU;
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poly16_t expected_p16 = CP;
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/* Expected results for vduph_laneq. */
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float16_t expected_q_f16 = EF;
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int16_t expected_q_s16 = BS;
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uint16_t expected_q_u16 = GU;
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poly16_t expected_q_p16 = FP;
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void exec_vduph_lane_f16 (void)
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{
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/* vduph_lane. */
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DECL_VARIABLE(vsrc, float, 16, 4);
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DECL_VARIABLE(vsrc, int, 16, 4);
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DECL_VARIABLE(vsrc, uint, 16, 4);
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DECL_VARIABLE(vsrc, poly, 16, 4);
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VECT_VAR_DECL (buf_src, float, 16, 4) [] = {AF, BF, CF, DF};
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VECT_VAR_DECL (buf_src, int, 16, 4) [] = {AS, BS, CS, DS};
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VECT_VAR_DECL (buf_src, uint, 16, 4) [] = {AU, BU, CU, DU};
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VECT_VAR_DECL (buf_src, poly, 16, 4) [] = {AP, BP, CP, DP};
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VLOAD (vsrc, buf_src, , int, s, 16, 4);
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VLOAD (vsrc, buf_src, , float, f, 16, 4);
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VLOAD (vsrc, buf_src, , uint, u, 16, 4);
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VLOAD (vsrc, buf_src, , poly, p, 16, 4);
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float16_t res_f = vduph_lane_f16 (VECT_VAR (vsrc, float, 16, 4), 0);
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if (* (unsigned short *) &res_f != * (unsigned short *) &expected_f16)
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abort ();
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int16_t res_s = vduph_lane_s16 (VECT_VAR (vsrc, int, 16, 4), 3);
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if (* (unsigned short *) &res_s != * (unsigned short *) &expected_s16)
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abort ();
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uint16_t res_u = vduph_lane_u16 (VECT_VAR (vsrc, uint, 16, 4), 1);
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if (* (unsigned short *) &res_u != * (unsigned short *) &expected_u16)
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abort ();
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poly16_t res_p = vduph_lane_p16 (VECT_VAR (vsrc, poly, 16, 4), 2);
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if (* (unsigned short *) &res_p != * (unsigned short *) &expected_p16)
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abort ();
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/* vduph_laneq. */
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DECL_VARIABLE(vsrc, float, 16, 8);
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DECL_VARIABLE(vsrc, int, 16, 8);
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DECL_VARIABLE(vsrc, uint, 16, 8);
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DECL_VARIABLE(vsrc, poly, 16, 8);
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VECT_VAR_DECL (buf_src, float, 16, 8) [] = {AF, BF, CF, DF, EF, FF, GF, HF};
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VECT_VAR_DECL (buf_src, int, 16, 8) [] = {AS, BS, CS, DS, ES, FS, GS, HS};
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VECT_VAR_DECL (buf_src, uint, 16, 8) [] = {AU, BU, CU, DU, EU, FU, GU, HU};
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VECT_VAR_DECL (buf_src, poly, 16, 8) [] = {AP, BP, CP, DP, EP, FP, GP, HP};
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VLOAD (vsrc, buf_src, q, int, s, 16, 8);
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VLOAD (vsrc, buf_src, q, float, f, 16, 8);
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VLOAD (vsrc, buf_src, q, uint, u, 16, 8);
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VLOAD (vsrc, buf_src, q, poly, p, 16, 8);
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res_f = vduph_laneq_f16 (VECT_VAR (vsrc, float, 16, 8), 4);
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if (* (unsigned short *) &res_f != * (unsigned short *) &expected_q_f16)
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abort ();
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res_s = vduph_laneq_s16 (VECT_VAR (vsrc, int, 16, 8), 1);
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if (* (unsigned short *) &res_s != * (unsigned short *) &expected_q_s16)
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abort ();
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res_u = vduph_laneq_u16 (VECT_VAR (vsrc, uint, 16, 8), 6);
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if (* (unsigned short *) &res_u != * (unsigned short *) &expected_q_u16)
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abort ();
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res_p = vduph_laneq_p16 (VECT_VAR (vsrc, poly, 16, 8), 5);
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if (* (unsigned short *) &res_p != * (unsigned short *) &expected_q_p16)
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abort ();
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}
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int
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main (void)
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{
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exec_vduph_lane_f16 ();
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return 0;
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}
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263
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
Normal file
263
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
Normal file
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@ -0,0 +1,263 @@
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/* { dg-do run } */
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/* { dg-skip-if "" { arm*-*-* } } */
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#include <arm_neon.h>
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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/* Expected results. */
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VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0x11, 0xf2, 0x11,
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0xf4, 0x11, 0xf6, 0x11 };
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VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0x22, 0xfff2, 0x22 };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
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VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
|
||||
VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0x55, 0xf2, 0x55,
|
||||
0xf4, 0x55, 0xf6, 0x55 };
|
||||
VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0x66, 0xfff2, 0x66 };
|
||||
VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
|
||||
VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
|
||||
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0x55, 0xf2, 0x55,
|
||||
0xf4, 0x55, 0xf6, 0x55 };
|
||||
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0x66, 0xfff2, 0x66 };
|
||||
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0x4b4d,
|
||||
0xcb00, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0x11, 0xf2, 0x11,
|
||||
0xf4, 0x11, 0xf6, 0x11,
|
||||
0xf8, 0x11, 0xfa, 0x11,
|
||||
0xfc, 0x11, 0xfe, 0x11 };
|
||||
VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0x22, 0xfff2, 0x22,
|
||||
0xfff4, 0x22, 0xfff6, 0x22 };
|
||||
VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0x33,
|
||||
0xfffffff2, 0x33 };
|
||||
VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
|
||||
0x44 };
|
||||
VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0x55, 0xf2, 0x55,
|
||||
0xf4, 0x55, 0xf6, 0x55,
|
||||
0xf8, 0x55, 0xfa, 0x55,
|
||||
0xfc, 0x55, 0xfe, 0x55 };
|
||||
VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0x66, 0xfff2, 0x66,
|
||||
0xfff4, 0x66, 0xfff6, 0x66 };
|
||||
VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0x77,
|
||||
0xfffffff2, 0x77 };
|
||||
VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
|
||||
0x88 };
|
||||
VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0x55, 0xf2, 0x55,
|
||||
0xf4, 0x55, 0xf6, 0x55,
|
||||
0xf8, 0x55, 0xfa, 0x55,
|
||||
0xfc, 0x55, 0xfe, 0x55 };
|
||||
VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0x66, 0xfff2, 0x66,
|
||||
0xfff4, 0x66, 0xfff6, 0x66 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0x4b4d,
|
||||
0xcb00, 0x4b4d,
|
||||
0xca00, 0x4b4d,
|
||||
0xc900, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0x42073333,
|
||||
0xc1600000, 0x42073333 };
|
||||
|
||||
#define TEST_MSG "VTRN1"
|
||||
void exec_vtrn_half (void)
|
||||
{
|
||||
#define TEST_VTRN(PART, Q, T1, T2, W, N) \
|
||||
VECT_VAR(vector_res, T1, W, N) = \
|
||||
vtrn##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
|
||||
VECT_VAR(vector2, T1, W, N)); \
|
||||
vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
|
||||
|
||||
#define TEST_VTRN1(Q, T1, T2, W, N) TEST_VTRN(1, Q, T1, T2, W, N)
|
||||
|
||||
/* Input vector can only have 64 bits. */
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector);
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector2);
|
||||
DECL_VARIABLE(vector, float, 64, 2);
|
||||
DECL_VARIABLE(vector2, float, 64, 2);
|
||||
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector_res);
|
||||
DECL_VARIABLE(vector_res, float, 64, 2);
|
||||
|
||||
clean_results ();
|
||||
/* We don't have vtrn1_T64x1, so set expected to the clean value. */
|
||||
CLEAN(expected, int, 64, 1);
|
||||
CLEAN(expected, uint, 64, 1);
|
||||
|
||||
TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VLOAD(vector, buffer, , float, f, 16, 4);
|
||||
VLOAD(vector, buffer, q, float, f, 16, 8);
|
||||
#endif
|
||||
VLOAD(vector, buffer, , float, f, 32, 2);
|
||||
VLOAD(vector, buffer, q, float, f, 32, 4);
|
||||
VLOAD(vector, buffer, q, float, f, 64, 2);
|
||||
|
||||
/* Choose arbitrary initialization values. */
|
||||
VDUP(vector2, , int, s, 8, 8, 0x11);
|
||||
VDUP(vector2, , int, s, 16, 4, 0x22);
|
||||
VDUP(vector2, , int, s, 32, 2, 0x33);
|
||||
VDUP(vector2, , uint, u, 8, 8, 0x55);
|
||||
VDUP(vector2, , uint, u, 16, 4, 0x66);
|
||||
VDUP(vector2, , uint, u, 32, 2, 0x77);
|
||||
VDUP(vector2, , poly, p, 8, 8, 0x55);
|
||||
VDUP(vector2, , poly, p, 16, 4, 0x66);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VDUP (vector2, , float, f, 16, 4, 14.6f); /* 14.6f is 0x4b4d. */
|
||||
#endif
|
||||
VDUP(vector2, , float, f, 32, 2, 33.6f);
|
||||
|
||||
VDUP(vector2, q, int, s, 8, 16, 0x11);
|
||||
VDUP(vector2, q, int, s, 16, 8, 0x22);
|
||||
VDUP(vector2, q, int, s, 32, 4, 0x33);
|
||||
VDUP(vector2, q, int, s, 64, 2, 0x44);
|
||||
VDUP(vector2, q, uint, u, 8, 16, 0x55);
|
||||
VDUP(vector2, q, uint, u, 16, 8, 0x66);
|
||||
VDUP(vector2, q, uint, u, 32, 4, 0x77);
|
||||
VDUP(vector2, q, uint, u, 64, 2, 0x88);
|
||||
VDUP(vector2, q, poly, p, 8, 16, 0x55);
|
||||
VDUP(vector2, q, poly, p, 16, 8, 0x66);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VDUP (vector2, q, float, f, 16, 8, 14.6f);
|
||||
#endif
|
||||
VDUP(vector2, q, float, f, 32, 4, 33.8f);
|
||||
VDUP(vector2, q, float, f, 64, 2, 33.8f);
|
||||
|
||||
TEST_VTRN1(, int, s, 8, 8);
|
||||
TEST_VTRN1(, int, s, 16, 4);
|
||||
TEST_VTRN1(, int, s, 32, 2);
|
||||
TEST_VTRN1(, uint, u, 8, 8);
|
||||
TEST_VTRN1(, uint, u, 16, 4);
|
||||
TEST_VTRN1(, uint, u, 32, 2);
|
||||
TEST_VTRN1(, poly, p, 8, 8);
|
||||
TEST_VTRN1(, poly, p, 16, 4);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VTRN1(, float, f, 16, 4);
|
||||
#endif
|
||||
TEST_VTRN1(, float, f, 32, 2);
|
||||
|
||||
TEST_VTRN1(q, int, s, 8, 16);
|
||||
TEST_VTRN1(q, int, s, 16, 8);
|
||||
TEST_VTRN1(q, int, s, 32, 4);
|
||||
TEST_VTRN1(q, int, s, 64, 2);
|
||||
TEST_VTRN1(q, uint, u, 8, 16);
|
||||
TEST_VTRN1(q, uint, u, 16, 8);
|
||||
TEST_VTRN1(q, uint, u, 32, 4);
|
||||
TEST_VTRN1(q, uint, u, 64, 2);
|
||||
TEST_VTRN1(q, poly, p, 8, 16);
|
||||
TEST_VTRN1(q, poly, p, 16, 8);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VTRN1(q, float, f, 16, 8);
|
||||
#endif
|
||||
TEST_VTRN1(q, float, f, 32, 4);
|
||||
TEST_VTRN1(q, float, f, 64, 2);
|
||||
|
||||
#if defined (FP16_SUPPORTED)
|
||||
CHECK_RESULTS (TEST_MSG, "");
|
||||
#else
|
||||
CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
|
||||
#endif
|
||||
|
||||
#undef TEST_MSG
|
||||
#define TEST_MSG "VTRN2"
|
||||
|
||||
#define TEST_VTRN2(Q, T1, T2, W, N) TEST_VTRN(2, Q, T1, T2, W, N)
|
||||
|
||||
/* Expected results. */
|
||||
VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0x11, 0xf3, 0x11,
|
||||
0xf5, 0x11, 0xf7, 0x11 };
|
||||
VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff1, 0x22, 0xfff3, 0x22 };
|
||||
VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
|
||||
VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
|
||||
VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0x55, 0xf3, 0x55,
|
||||
0xf5, 0x55, 0xf7, 0x55 };
|
||||
VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff1, 0x66, 0xfff3, 0x66 };
|
||||
VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
|
||||
VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
|
||||
VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0x55, 0xf3, 0x55,
|
||||
0xf5, 0x55, 0xf7, 0x55 };
|
||||
VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff1, 0x66, 0xfff3, 0x66 };
|
||||
VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0x4b4d,
|
||||
0xca80, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0x11, 0xf3, 0x11,
|
||||
0xf5, 0x11, 0xf7, 0x11,
|
||||
0xf9, 0x11, 0xfb, 0x11,
|
||||
0xfd, 0x11, 0xff, 0x11 };
|
||||
VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff1, 0x22, 0xfff3, 0x22,
|
||||
0xfff5, 0x22, 0xfff7, 0x22 };
|
||||
VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0x33,
|
||||
0xfffffff3, 0x33 };
|
||||
VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
|
||||
0x44 };
|
||||
VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf1, 0x55, 0xf3, 0x55,
|
||||
0xf5, 0x55, 0xf7, 0x55,
|
||||
0xf9, 0x55, 0xfb, 0x55,
|
||||
0xfd, 0x55, 0xff, 0x55 };
|
||||
VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0x66, 0xfff3, 0x66,
|
||||
0xfff5, 0x66, 0xfff7, 0x66 };
|
||||
VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0x77,
|
||||
0xfffffff3, 0x77 };
|
||||
VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
|
||||
0x88 };
|
||||
VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf1, 0x55, 0xf3, 0x55,
|
||||
0xf5, 0x55, 0xf7, 0x55,
|
||||
0xf9, 0x55, 0xfb, 0x55,
|
||||
0xfd, 0x55, 0xff, 0x55 };
|
||||
VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0x66, 0xfff3, 0x66,
|
||||
0xfff5, 0x66, 0xfff7, 0x66 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xcb80, 0x4b4d,
|
||||
0xca80, 0x4b4d,
|
||||
0xc980, 0x4b4d,
|
||||
0xc880, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0x42073333,
|
||||
0xc1500000, 0x42073333 };
|
||||
clean_results ();
|
||||
CLEAN(expected2, int, 64, 1);
|
||||
CLEAN(expected2, uint, 64, 1);
|
||||
|
||||
TEST_VTRN2(, int, s, 8, 8);
|
||||
TEST_VTRN2(, int, s, 16, 4);
|
||||
TEST_VTRN2(, int, s, 32, 2);
|
||||
TEST_VTRN2(, uint, u, 8, 8);
|
||||
TEST_VTRN2(, uint, u, 16, 4);
|
||||
TEST_VTRN2(, uint, u, 32, 2);
|
||||
TEST_VTRN2(, poly, p, 8, 8);
|
||||
TEST_VTRN2(, poly, p, 16, 4);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VTRN2(, float, f, 16, 4);
|
||||
#endif
|
||||
TEST_VTRN2(, float, f, 32, 2);
|
||||
|
||||
TEST_VTRN2(q, int, s, 8, 16);
|
||||
TEST_VTRN2(q, int, s, 16, 8);
|
||||
TEST_VTRN2(q, int, s, 32, 4);
|
||||
TEST_VTRN2(q, int, s, 64, 2);
|
||||
TEST_VTRN2(q, uint, u, 8, 16);
|
||||
TEST_VTRN2(q, uint, u, 16, 8);
|
||||
TEST_VTRN2(q, uint, u, 32, 4);
|
||||
TEST_VTRN2(q, uint, u, 64, 2);
|
||||
TEST_VTRN2(q, poly, p, 8, 16);
|
||||
TEST_VTRN2(q, poly, p, 16, 8);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VTRN2(q, float, f, 16, 8);
|
||||
#endif
|
||||
TEST_VTRN2(q, float, f, 32, 4);
|
||||
TEST_VTRN2(q, float, f, 64, 2);
|
||||
|
||||
CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
|
||||
#if defined (FP16_SUPPORTED)
|
||||
CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
|
||||
CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
|
||||
#endif
|
||||
}
|
||||
|
||||
int main (void)
|
||||
{
|
||||
exec_vtrn_half ();
|
||||
return 0;
|
||||
}
|
||||
259
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
Normal file
259
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-skip-if "" { arm*-*-* } } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "arm-neon-ref.h"
|
||||
#include "compute-ref-data.h"
|
||||
|
||||
/* Expected results. */
|
||||
VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
|
||||
0x11, 0x11, 0x11, 0x11 };
|
||||
VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0x22, 0x22 };
|
||||
VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
|
||||
VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
|
||||
VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
|
||||
0x55, 0x55, 0x55, 0x55 };
|
||||
VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0x66, 0x66 };
|
||||
VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
|
||||
VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
|
||||
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
|
||||
0x55, 0x55, 0x55, 0x55 };
|
||||
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff2, 0x66, 0x66 };
|
||||
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb00,
|
||||
0x4b4d, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
|
||||
0xf8, 0xfa, 0xfc, 0xfe,
|
||||
0x11, 0x11, 0x11, 0x11,
|
||||
0x11, 0x11, 0x11, 0x11 };
|
||||
VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff2, 0xfff4, 0xfff6,
|
||||
0x22, 0x22, 0x22, 0x22 };
|
||||
VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff2,
|
||||
0x33, 0x33 };
|
||||
VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
|
||||
0x44 };
|
||||
VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
|
||||
0xf8, 0xfa, 0xfc, 0xfe,
|
||||
0x55, 0x55, 0x55, 0x55,
|
||||
0x55, 0x55, 0x55, 0x55 };
|
||||
VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff2, 0xfff4, 0xfff6,
|
||||
0x66, 0x66, 0x66, 0x66 };
|
||||
VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff2, 0x77, 0x77 };
|
||||
VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
|
||||
0x88 };
|
||||
VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
|
||||
0xf8, 0xfa, 0xfc, 0xfe,
|
||||
0x55, 0x55, 0x55, 0x55,
|
||||
0x55, 0x55, 0x55, 0x55 };
|
||||
VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff2, 0xfff4, 0xfff6,
|
||||
0x66, 0x66, 0x66, 0x66 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb00, 0xca00, 0xc900,
|
||||
0x4b4d, 0x4b4d, 0x4b4d, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1600000,
|
||||
0x42073333, 0x42073333 };
|
||||
|
||||
#define TEST_MSG "VUZP1"
|
||||
void exec_vuzp_half (void)
|
||||
{
|
||||
#define TEST_VUZP(PART, Q, T1, T2, W, N) \
|
||||
VECT_VAR(vector_res, T1, W, N) = \
|
||||
vuzp##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
|
||||
VECT_VAR(vector2, T1, W, N)); \
|
||||
vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
|
||||
|
||||
#define TEST_VUZP1(Q, T1, T2, W, N) TEST_VUZP(1, Q, T1, T2, W, N)
|
||||
|
||||
/* Input vector can only have 64 bits. */
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector);
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector2);
|
||||
DECL_VARIABLE(vector, float, 64, 2);
|
||||
DECL_VARIABLE(vector2, float, 64, 2);
|
||||
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector_res);
|
||||
DECL_VARIABLE(vector_res, float, 64, 2);
|
||||
|
||||
clean_results ();
|
||||
/* We don't have vuzp1_T64x1, so set expected to the clean value. */
|
||||
CLEAN(expected, int, 64, 1);
|
||||
CLEAN(expected, uint, 64, 1);
|
||||
|
||||
TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VLOAD(vector, buffer, , float, f, 16, 4);
|
||||
VLOAD(vector, buffer, q, float, f, 16, 8);
|
||||
#endif
|
||||
VLOAD(vector, buffer, , float, f, 32, 2);
|
||||
VLOAD(vector, buffer, q, float, f, 32, 4);
|
||||
VLOAD(vector, buffer, q, float, f, 64, 2);
|
||||
|
||||
/* Choose arbitrary initialization values. */
|
||||
VDUP(vector2, , int, s, 8, 8, 0x11);
|
||||
VDUP(vector2, , int, s, 16, 4, 0x22);
|
||||
VDUP(vector2, , int, s, 32, 2, 0x33);
|
||||
VDUP(vector2, , uint, u, 8, 8, 0x55);
|
||||
VDUP(vector2, , uint, u, 16, 4, 0x66);
|
||||
VDUP(vector2, , uint, u, 32, 2, 0x77);
|
||||
VDUP(vector2, , poly, p, 8, 8, 0x55);
|
||||
VDUP(vector2, , poly, p, 16, 4, 0x66);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VDUP (vector2, , float, f, 16, 4, 14.6f); /* 14.6f is 0x4b4d. */
|
||||
#endif
|
||||
VDUP(vector2, , float, f, 32, 2, 33.6f);
|
||||
|
||||
VDUP(vector2, q, int, s, 8, 16, 0x11);
|
||||
VDUP(vector2, q, int, s, 16, 8, 0x22);
|
||||
VDUP(vector2, q, int, s, 32, 4, 0x33);
|
||||
VDUP(vector2, q, int, s, 64, 2, 0x44);
|
||||
VDUP(vector2, q, uint, u, 8, 16, 0x55);
|
||||
VDUP(vector2, q, uint, u, 16, 8, 0x66);
|
||||
VDUP(vector2, q, uint, u, 32, 4, 0x77);
|
||||
VDUP(vector2, q, uint, u, 64, 2, 0x88);
|
||||
VDUP(vector2, q, poly, p, 8, 16, 0x55);
|
||||
VDUP(vector2, q, poly, p, 16, 8, 0x66);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VDUP (vector2, q, float, f, 16, 8, 14.6f);
|
||||
#endif
|
||||
VDUP(vector2, q, float, f, 32, 4, 33.8f);
|
||||
VDUP(vector2, q, float, f, 64, 2, 33.8f);
|
||||
|
||||
TEST_VUZP1(, int, s, 8, 8);
|
||||
TEST_VUZP1(, int, s, 16, 4);
|
||||
TEST_VUZP1(, int, s, 32, 2);
|
||||
TEST_VUZP1(, uint, u, 8, 8);
|
||||
TEST_VUZP1(, uint, u, 16, 4);
|
||||
TEST_VUZP1(, uint, u, 32, 2);
|
||||
TEST_VUZP1(, poly, p, 8, 8);
|
||||
TEST_VUZP1(, poly, p, 16, 4);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VUZP1(, float, f, 16, 4);
|
||||
#endif
|
||||
TEST_VUZP1(, float, f, 32, 2);
|
||||
|
||||
TEST_VUZP1(q, int, s, 8, 16);
|
||||
TEST_VUZP1(q, int, s, 16, 8);
|
||||
TEST_VUZP1(q, int, s, 32, 4);
|
||||
TEST_VUZP1(q, int, s, 64, 2);
|
||||
TEST_VUZP1(q, uint, u, 8, 16);
|
||||
TEST_VUZP1(q, uint, u, 16, 8);
|
||||
TEST_VUZP1(q, uint, u, 32, 4);
|
||||
TEST_VUZP1(q, uint, u, 64, 2);
|
||||
TEST_VUZP1(q, poly, p, 8, 16);
|
||||
TEST_VUZP1(q, poly, p, 16, 8);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VUZP1(q, float, f, 16, 8);
|
||||
#endif
|
||||
TEST_VUZP1(q, float, f, 32, 4);
|
||||
TEST_VUZP1(q, float, f, 64, 2);
|
||||
|
||||
#if defined (FP16_SUPPORTED)
|
||||
CHECK_RESULTS (TEST_MSG, "");
|
||||
#else
|
||||
CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
|
||||
#endif
|
||||
|
||||
#undef TEST_MSG
|
||||
#define TEST_MSG "VUZP2"
|
||||
|
||||
#define TEST_VUZP2(Q, T1, T2, W, N) TEST_VUZP(2, Q, T1, T2, W, N)
|
||||
|
||||
/* Expected results. */
|
||||
VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
|
||||
0x11, 0x11, 0x11, 0x11 };
|
||||
VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff1, 0xfff3, 0x22, 0x22 };
|
||||
VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
|
||||
VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
|
||||
VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
|
||||
0x55, 0x55, 0x55, 0x55 };
|
||||
VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff1, 0xfff3, 0x66, 0x66 };
|
||||
VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
|
||||
VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
|
||||
VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
|
||||
0x55, 0x55, 0x55, 0x55 };
|
||||
VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff1, 0xfff3, 0x66, 0x66 };
|
||||
VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0xca80,
|
||||
0x4b4d, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
|
||||
0xf9, 0xfb, 0xfd, 0xff,
|
||||
0x11, 0x11, 0x11, 0x11,
|
||||
0x11, 0x11, 0x11, 0x11 };
|
||||
VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff1, 0xfff3, 0xfff5, 0xfff7,
|
||||
0x22, 0x22, 0x22, 0x22 };
|
||||
VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff3,
|
||||
0x33, 0x33 };
|
||||
VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
|
||||
0x44 };
|
||||
VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
|
||||
0xf9, 0xfb, 0xfd, 0xff,
|
||||
0x55, 0x55, 0x55, 0x55,
|
||||
0x55, 0x55, 0x55, 0x55 };
|
||||
VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0xfff3, 0xfff5, 0xfff7,
|
||||
0x66, 0x66, 0x66, 0x66 };
|
||||
VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0xfffffff3, 0x77, 0x77 };
|
||||
VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
|
||||
0x88 };
|
||||
VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
|
||||
0xf9, 0xfb, 0xfd, 0xff,
|
||||
0x55, 0x55, 0x55, 0x55,
|
||||
0x55, 0x55, 0x55, 0x55 };
|
||||
VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0xfff3, 0xfff5, 0xfff7,
|
||||
0x66, 0x66, 0x66, 0x66 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xcb80, 0xca80, 0xc980, 0xc880,
|
||||
0x4b4d, 0x4b4d, 0x4b4d, 0x4b4d
|
||||
};
|
||||
#endif
|
||||
VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0xc1500000,
|
||||
0x42073333, 0x42073333 };
|
||||
|
||||
clean_results ();
|
||||
CLEAN(expected2, int, 64, 1);
|
||||
CLEAN(expected2, uint, 64, 1);
|
||||
|
||||
TEST_VUZP2(, int, s, 8, 8);
|
||||
TEST_VUZP2(, int, s, 16, 4);
|
||||
TEST_VUZP2(, int, s, 32, 2);
|
||||
TEST_VUZP2(, uint, u, 8, 8);
|
||||
TEST_VUZP2(, uint, u, 16, 4);
|
||||
TEST_VUZP2(, uint, u, 32, 2);
|
||||
TEST_VUZP2(, poly, p, 8, 8);
|
||||
TEST_VUZP2(, poly, p, 16, 4);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VUZP2(, float, f, 16, 4);
|
||||
#endif
|
||||
TEST_VUZP2(, float, f, 32, 2);
|
||||
|
||||
TEST_VUZP2(q, int, s, 8, 16);
|
||||
TEST_VUZP2(q, int, s, 16, 8);
|
||||
TEST_VUZP2(q, int, s, 32, 4);
|
||||
TEST_VUZP2(q, int, s, 64, 2);
|
||||
TEST_VUZP2(q, uint, u, 8, 16);
|
||||
TEST_VUZP2(q, uint, u, 16, 8);
|
||||
TEST_VUZP2(q, uint, u, 32, 4);
|
||||
TEST_VUZP2(q, uint, u, 64, 2);
|
||||
TEST_VUZP2(q, poly, p, 8, 16);
|
||||
TEST_VUZP2(q, poly, p, 16, 8);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VUZP2(q, float, f, 16, 8);
|
||||
#endif
|
||||
TEST_VUZP2(q, float, f, 32, 4);
|
||||
TEST_VUZP2(q, float, f, 64, 2);
|
||||
|
||||
CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
|
||||
#if defined (FP16_SUPPORTED)
|
||||
CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
|
||||
CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
|
||||
#endif
|
||||
}
|
||||
|
||||
int main (void)
|
||||
{
|
||||
exec_vuzp_half ();
|
||||
return 0;
|
||||
}
|
||||
263
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
Normal file
263
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
Normal file
|
|
@ -0,0 +1,263 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-skip-if "" { arm*-*-* } } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "arm-neon-ref.h"
|
||||
#include "compute-ref-data.h"
|
||||
|
||||
/* Expected results. */
|
||||
VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0x11, 0xf1, 0x11,
|
||||
0xf2, 0x11, 0xf3, 0x11 };
|
||||
VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0x22, 0xfff1, 0x22 };
|
||||
VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
|
||||
VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
|
||||
VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0x55, 0xf1, 0x55,
|
||||
0xf2, 0x55, 0xf3, 0x55 };
|
||||
VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0x66, 0xfff1, 0x66 };
|
||||
VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
|
||||
VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
|
||||
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0x55, 0xf1, 0x55,
|
||||
0xf2, 0x55, 0xf3, 0x55 };
|
||||
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0x66, 0xfff1, 0x66 };
|
||||
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0x4b4d,
|
||||
0xcb80, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0x11, 0xf1, 0x11,
|
||||
0xf2, 0x11, 0xf3, 0x11,
|
||||
0xf4, 0x11, 0xf5, 0x11,
|
||||
0xf6, 0x11, 0xf7, 0x11 };
|
||||
VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0x22, 0xfff1, 0x22,
|
||||
0xfff2, 0x22, 0xfff3, 0x22 };
|
||||
VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0x33,
|
||||
0xfffffff1, 0x33 };
|
||||
VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
|
||||
0x44 };
|
||||
VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0x55, 0xf1, 0x55,
|
||||
0xf2, 0x55, 0xf3, 0x55,
|
||||
0xf4, 0x55, 0xf5, 0x55,
|
||||
0xf6, 0x55, 0xf7, 0x55 };
|
||||
VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0x66, 0xfff1, 0x66,
|
||||
0xfff2, 0x66, 0xfff3, 0x66 };
|
||||
VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0x77,
|
||||
0xfffffff1, 0x77 };
|
||||
VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
|
||||
0x88 };
|
||||
VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0x55, 0xf1, 0x55,
|
||||
0xf2, 0x55, 0xf3, 0x55,
|
||||
0xf4, 0x55, 0xf5, 0x55,
|
||||
0xf6, 0x55, 0xf7, 0x55 };
|
||||
VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0x66, 0xfff1, 0x66,
|
||||
0xfff2, 0x66, 0xfff3, 0x66 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0x4b4d,
|
||||
0xcb80, 0x4b4d,
|
||||
0xcb00, 0x4b4d,
|
||||
0xca80, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0x42073333,
|
||||
0xc1700000, 0x42073333 };
|
||||
|
||||
#define TEST_MSG "VZIP1"
|
||||
void exec_vzip_half (void)
|
||||
{
|
||||
#define TEST_VZIP(PART, Q, T1, T2, W, N) \
|
||||
VECT_VAR(vector_res, T1, W, N) = \
|
||||
vzip##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
|
||||
VECT_VAR(vector2, T1, W, N)); \
|
||||
vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
|
||||
|
||||
#define TEST_VZIP1(Q, T1, T2, W, N) TEST_VZIP(1, Q, T1, T2, W, N)
|
||||
|
||||
/* Input vector can only have 64 bits. */
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector);
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector2);
|
||||
DECL_VARIABLE(vector, float, 64, 2);
|
||||
DECL_VARIABLE(vector2, float, 64, 2);
|
||||
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector_res);
|
||||
DECL_VARIABLE(vector_res, float, 64, 2);
|
||||
|
||||
clean_results ();
|
||||
/* We don't have vzip1_T64x1, so set expected to the clean value. */
|
||||
CLEAN(expected, int, 64, 1);
|
||||
CLEAN(expected, uint, 64, 1);
|
||||
|
||||
TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VLOAD(vector, buffer, , float, f, 16, 4);
|
||||
VLOAD(vector, buffer, q, float, f, 16, 8);
|
||||
#endif
|
||||
VLOAD(vector, buffer, , float, f, 32, 2);
|
||||
VLOAD(vector, buffer, q, float, f, 32, 4);
|
||||
VLOAD(vector, buffer, q, float, f, 64, 2);
|
||||
|
||||
/* Choose arbitrary initialization values. */
|
||||
VDUP(vector2, , int, s, 8, 8, 0x11);
|
||||
VDUP(vector2, , int, s, 16, 4, 0x22);
|
||||
VDUP(vector2, , int, s, 32, 2, 0x33);
|
||||
VDUP(vector2, , uint, u, 8, 8, 0x55);
|
||||
VDUP(vector2, , uint, u, 16, 4, 0x66);
|
||||
VDUP(vector2, , uint, u, 32, 2, 0x77);
|
||||
VDUP(vector2, , poly, p, 8, 8, 0x55);
|
||||
VDUP(vector2, , poly, p, 16, 4, 0x66);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VDUP (vector2, , float, f, 16, 4, 14.6f); /* 14.6f is 0x4b4d. */
|
||||
#endif
|
||||
VDUP(vector2, , float, f, 32, 2, 33.6f);
|
||||
|
||||
VDUP(vector2, q, int, s, 8, 16, 0x11);
|
||||
VDUP(vector2, q, int, s, 16, 8, 0x22);
|
||||
VDUP(vector2, q, int, s, 32, 4, 0x33);
|
||||
VDUP(vector2, q, int, s, 64, 2, 0x44);
|
||||
VDUP(vector2, q, uint, u, 8, 16, 0x55);
|
||||
VDUP(vector2, q, uint, u, 16, 8, 0x66);
|
||||
VDUP(vector2, q, uint, u, 32, 4, 0x77);
|
||||
VDUP(vector2, q, uint, u, 64, 2, 0x88);
|
||||
VDUP(vector2, q, poly, p, 8, 16, 0x55);
|
||||
VDUP(vector2, q, poly, p, 16, 8, 0x66);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VDUP (vector2, q, float, f, 16, 8, 14.6f);
|
||||
#endif
|
||||
VDUP(vector2, q, float, f, 32, 4, 33.8f);
|
||||
VDUP(vector2, q, float, f, 64, 2, 33.8f);
|
||||
|
||||
TEST_VZIP1(, int, s, 8, 8);
|
||||
TEST_VZIP1(, int, s, 16, 4);
|
||||
TEST_VZIP1(, int, s, 32, 2);
|
||||
TEST_VZIP1(, uint, u, 8, 8);
|
||||
TEST_VZIP1(, uint, u, 16, 4);
|
||||
TEST_VZIP1(, uint, u, 32, 2);
|
||||
TEST_VZIP1(, poly, p, 8, 8);
|
||||
TEST_VZIP1(, poly, p, 16, 4);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VZIP1(, float, f, 16, 4);
|
||||
#endif
|
||||
TEST_VZIP1(, float, f, 32, 2);
|
||||
|
||||
TEST_VZIP1(q, int, s, 8, 16);
|
||||
TEST_VZIP1(q, int, s, 16, 8);
|
||||
TEST_VZIP1(q, int, s, 32, 4);
|
||||
TEST_VZIP1(q, int, s, 64, 2);
|
||||
TEST_VZIP1(q, uint, u, 8, 16);
|
||||
TEST_VZIP1(q, uint, u, 16, 8);
|
||||
TEST_VZIP1(q, uint, u, 32, 4);
|
||||
TEST_VZIP1(q, uint, u, 64, 2);
|
||||
TEST_VZIP1(q, poly, p, 8, 16);
|
||||
TEST_VZIP1(q, poly, p, 16, 8);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VZIP1(q, float, f, 16, 8);
|
||||
#endif
|
||||
TEST_VZIP1(q, float, f, 32, 4);
|
||||
TEST_VZIP1(q, float, f, 64, 2);
|
||||
|
||||
#if defined (FP16_SUPPORTED)
|
||||
CHECK_RESULTS (TEST_MSG, "");
|
||||
#else
|
||||
CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
|
||||
#endif
|
||||
|
||||
#undef TEST_MSG
|
||||
#define TEST_MSG "VZIP2"
|
||||
|
||||
#define TEST_VZIP2(Q, T1, T2, W, N) TEST_VZIP(2, Q, T1, T2, W, N)
|
||||
|
||||
/* Expected results. */
|
||||
VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf4, 0x11, 0xf5, 0x11,
|
||||
0xf6, 0x11, 0xf7, 0x11 };
|
||||
VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff2, 0x22, 0xfff3, 0x22 };
|
||||
VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
|
||||
VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
|
||||
VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf4, 0x55, 0xf5, 0x55,
|
||||
0xf6, 0x55, 0xf7, 0x55 };
|
||||
VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff2, 0x66, 0xfff3, 0x66 };
|
||||
VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
|
||||
VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
|
||||
VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf4, 0x55, 0xf5, 0x55,
|
||||
0xf6, 0x55, 0xf7, 0x55 };
|
||||
VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff2, 0x66, 0xfff3, 0x66 };
|
||||
VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb00, 0x4b4d,
|
||||
0xca80, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf8, 0x11, 0xf9, 0x11,
|
||||
0xfa, 0x11, 0xfb, 0x11,
|
||||
0xfc, 0x11, 0xfd, 0x11,
|
||||
0xfe, 0x11, 0xff, 0x11 };
|
||||
VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff4, 0x22, 0xfff5, 0x22,
|
||||
0xfff6, 0x22, 0xfff7, 0x22 };
|
||||
VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff2, 0x33,
|
||||
0xfffffff3, 0x33 };
|
||||
VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
|
||||
0x44 };
|
||||
VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf8, 0x55, 0xf9, 0x55,
|
||||
0xfa, 0x55, 0xfb, 0x55,
|
||||
0xfc, 0x55, 0xfd, 0x55,
|
||||
0xfe, 0x55, 0xff, 0x55 };
|
||||
VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff4, 0x66, 0xfff5, 0x66,
|
||||
0xfff6, 0x66, 0xfff7, 0x66 };
|
||||
VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff2, 0x77,
|
||||
0xfffffff3, 0x77 };
|
||||
VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
|
||||
0x88 };
|
||||
VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf8, 0x55, 0xf9, 0x55,
|
||||
0xfa, 0x55, 0xfb, 0x55,
|
||||
0xfc, 0x55, 0xfd, 0x55,
|
||||
0xfe, 0x55, 0xff, 0x55 };
|
||||
VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff4, 0x66, 0xfff5, 0x66,
|
||||
0xfff6, 0x66, 0xfff7, 0x66 };
|
||||
#if defined (FP16_SUPPORTED)
|
||||
VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xca00, 0x4b4d,
|
||||
0xc980, 0x4b4d,
|
||||
0xc900, 0x4b4d,
|
||||
0xc880, 0x4b4d };
|
||||
#endif
|
||||
VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1600000, 0x42073333,
|
||||
0xc1500000, 0x42073333 };
|
||||
clean_results ();
|
||||
CLEAN(expected2, int, 64, 1);
|
||||
CLEAN(expected2, uint, 64, 1);
|
||||
|
||||
TEST_VZIP2(, int, s, 8, 8);
|
||||
TEST_VZIP2(, int, s, 16, 4);
|
||||
TEST_VZIP2(, int, s, 32, 2);
|
||||
TEST_VZIP2(, uint, u, 8, 8);
|
||||
TEST_VZIP2(, uint, u, 16, 4);
|
||||
TEST_VZIP2(, uint, u, 32, 2);
|
||||
TEST_VZIP2(, poly, p, 8, 8);
|
||||
TEST_VZIP2(, poly, p, 16, 4);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VZIP2(, float, f, 16, 4);
|
||||
#endif
|
||||
TEST_VZIP2(, float, f, 32, 2);
|
||||
|
||||
TEST_VZIP2(q, int, s, 8, 16);
|
||||
TEST_VZIP2(q, int, s, 16, 8);
|
||||
TEST_VZIP2(q, int, s, 32, 4);
|
||||
TEST_VZIP2(q, int, s, 64, 2);
|
||||
TEST_VZIP2(q, uint, u, 8, 16);
|
||||
TEST_VZIP2(q, uint, u, 16, 8);
|
||||
TEST_VZIP2(q, uint, u, 32, 4);
|
||||
TEST_VZIP2(q, uint, u, 64, 2);
|
||||
TEST_VZIP2(q, poly, p, 8, 16);
|
||||
TEST_VZIP2(q, poly, p, 16, 8);
|
||||
#if defined (FP16_SUPPORTED)
|
||||
TEST_VZIP2(q, float, f, 16, 8);
|
||||
#endif
|
||||
TEST_VZIP2(q, float, f, 32, 4);
|
||||
TEST_VZIP2(q, float, f, 64, 2);
|
||||
|
||||
CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
|
||||
#if defined (FP16_SUPPORTED)
|
||||
CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
|
||||
CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
|
||||
#endif
|
||||
}
|
||||
|
||||
int main (void)
|
||||
{
|
||||
exec_vzip_half ();
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue