diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 7838d99feec..db69e6983d0 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1035,7 +1035,10 @@ static const struct tune_params generic_tunings = 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + /* Enabling AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS significantly benefits + Neoverse V1. It does not have a noticeable effect on A64FX and should + have at most a very minor effect on SVE2 cores. */ + (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS), /* tune_flags. */ &generic_prefetch_tune }; @@ -14485,6 +14488,19 @@ aarch64_parse_override_string (const char* input_string, free (string_root); } +/* Adjust CURRENT_TUNE (a generic tuning struct) with settings that + are best for a generic target with the currently-enabled architecture + extensions. */ +static void +aarch64_adjust_generic_arch_tuning (struct tune_params ¤t_tune) +{ + /* Neoverse V1 is the only core that is known to benefit from + AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. There is therefore no + point enabling it for SVE2 and above. */ + if (TARGET_SVE2) + current_tune.extra_tuning_flags + &= ~AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS; +} static void aarch64_override_options_after_change_1 (struct gcc_options *opts) @@ -14555,6 +14571,8 @@ aarch64_override_options_internal (struct gcc_options *opts) we may later overwrite. */ aarch64_tune_params = *(selected_tune->tune); aarch64_architecture_version = selected_arch->architecture_version; + if (selected_tune->tune == &generic_tunings) + aarch64_adjust_generic_arch_tuning (aarch64_tune_params); if (opts->x_aarch64_override_tune_string) aarch64_parse_override_string (opts->x_aarch64_override_tune_string, diff --git a/gcc/testsuite/g++.target/aarch64/sve/aarch64-sve.exp b/gcc/testsuite/g++.target/aarch64/sve/aarch64-sve.exp index 4bbe2f50a32..d4761f2d807 100644 --- a/gcc/testsuite/g++.target/aarch64/sve/aarch64-sve.exp +++ b/gcc/testsuite/g++.target/aarch64/sve/aarch64-sve.exp @@ -38,6 +38,10 @@ if { [check_effective_target_aarch64_sve] } { set sve_flags "-march=armv8.2-a+sve" } +# Turn off any codegen tweaks by default that may affect expected assembly. +# Tests relying on those should turn them on explicitly. +set sve_flags "$sve_flags -moverride=tune=none" + # Main loop. dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] $sve_flags "" diff --git a/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp b/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp index 0734268313c..84ae95e2ccc 100644 --- a/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp +++ b/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp @@ -37,6 +37,10 @@ if { [check_effective_target_aarch64_sve] } { set sve_flags "-march=armv8.2-a+sve" } +# Turn off any codegen tweaks by default that may affect expected assembly. +# Tests relying on those should turn them on explicitly. +set sve_flags "$sve_flags -moverride=tune=none" + global gcc_runtest_parallelize_limit_minor if { [info exists gcc_runtest_parallelize_limit_minor] } { set old_limit_minor $gcc_runtest_parallelize_limit_minor diff --git a/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle.exp b/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle.exp index cb9de753e7a..8d3d8b4a8b3 100644 --- a/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle.exp +++ b/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle.exp @@ -44,6 +44,10 @@ if { [check_effective_target_aarch64_sve] } { set sve_flags "-march=armv8.2-a+sve" } +# Turn off any codegen tweaks by default that may affect expected assembly. +# Tests relying on those should turn them on explicitly. +set sve_flags "$sve_flags -moverride=tune=none" + # Main loop. set gcc_subdir [string replace $subdir 0 2 gcc] set files [glob -nocomplain \ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/aarch64-sve.exp b/gcc/testsuite/gcc.target/aarch64/sve/aarch64-sve.exp index 622fc92b528..1d3f56690e6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/aarch64-sve.exp +++ b/gcc/testsuite/gcc.target/aarch64/sve/aarch64-sve.exp @@ -44,6 +44,10 @@ if { [check_effective_target_aarch64_sve] } { set sve_flags "-march=armv8.2-a+sve" } +# Turn off any codegen tweaks by default that may affect expected assembly. +# Tests relying on those should turn them on explicitly. +set sve_flags "$sve_flags -moverride=tune=none" + # Most of the code-quality tests are written for LP64. Just do the # correctness tests for ILP32. if { [check_effective_target_ilp32] } { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp b/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp index 6146e659503..fcd07aaa040 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp @@ -37,6 +37,10 @@ if { [check_effective_target_aarch64_sve] } { set sve_flags "-march=armv8.2-a+sve" } +# Turn off any codegen tweaks by default that may affect expected assembly. +# Tests relying on those should turn them on explicitly. +set sve_flags "$sve_flags -moverride=tune=none" + global gcc_runtest_parallelize_limit_minor if { [info exists gcc_runtest_parallelize_limit_minor] } { set old_limit_minor $gcc_runtest_parallelize_limit_minor diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle.exp b/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle.exp index a33b65a2a74..2f36f1c57d1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle.exp +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle.exp @@ -44,6 +44,10 @@ if { [check_effective_target_aarch64_sve] } { set sve_flags "-march=armv8.2-a+sve" } +# Turn off any codegen tweaks by default that may affect expected assembly. +# Tests relying on those should turn them on explicitly. +set sve_flags "$sve_flags -moverride=tune=none" + # Main loop. set files [glob -nocomplain \ "$srcdir/$subdir/general/*.c" \