aarch64: Add vcopy(q)__lane(q)_bf16 intrinsics
gcc/ChangeLog 2020-10-20 Andrea Corallo <andrea.corallo@arm.com> * config/aarch64/arm_neon.h (vcopy_lane_bf16, vcopyq_lane_bf16) (vcopyq_laneq_bf16, vcopy_laneq_bf16): New intrinsics. gcc/testsuite/ChangeLog 2020-10-20 Andrea Corallo <andrea.corallo@arm.com> * gcc.target/aarch64/advsimd-intrinsics/bf16_vect_copy_lane_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_2.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_2.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_2.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_2.c: Likewise.
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Andrea Corallo
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10 changed files with 206 additions and 0 deletions
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@ -35716,6 +35716,42 @@ vcvtq_high_bf16_f32 (bfloat16x8_t __inactive, float32x4_t __a)
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return __builtin_aarch64_bfcvtn2v8bf (__inactive, __a);
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}
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__extension__ extern __inline bfloat16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcopy_lane_bf16 (bfloat16x4_t __a, const int __lane1,
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bfloat16x4_t __b, const int __lane2)
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{
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return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
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__a, __lane1);
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}
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__extension__ extern __inline bfloat16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcopyq_lane_bf16 (bfloat16x8_t __a, const int __lane1,
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bfloat16x4_t __b, const int __lane2)
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{
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return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
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__a, __lane1);
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}
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__extension__ extern __inline bfloat16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcopy_laneq_bf16 (bfloat16x4_t __a, const int __lane1,
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bfloat16x8_t __b, const int __lane2)
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{
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return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
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__a, __lane1);
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}
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__extension__ extern __inline bfloat16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcopyq_laneq_bf16 (bfloat16x8_t __a, const int __lane1,
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bfloat16x8_t __b, const int __lane2)
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{
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return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
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__a, __lane1);
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}
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#pragma GCC pop_options
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/* AdvSIMD 8-bit Integer Matrix Multiply (I8MM) intrinsics. */
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@ -0,0 +1,32 @@
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/* { dg-do assemble { target { aarch64*-*-* } } } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-additional-options "-march=armv8.2-a+bf16 -O3 --save-temps -std=gnu90" } */
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#include "arm_neon.h"
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bfloat16x4_t __attribute__((noinline,noclone))
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test_vcopy_lane_bf16 (bfloat16x4_t a, bfloat16x4_t b)
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{
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return vcopy_lane_bf16 (a, 1, b, 2);
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}
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bfloat16x8_t __attribute__((noinline,noclone))
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test_vcopyq_lane_bf16 (bfloat16x8_t a, bfloat16x4_t b)
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{
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return vcopyq_lane_bf16 (a, 1, b, 2);
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}
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bfloat16x4_t __attribute__((noinline,noclone))
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test_vcopy_laneq_bf16 (bfloat16x4_t a, bfloat16x8_t b)
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{
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return vcopy_laneq_bf16 (a, 1, b, 2);
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}
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bfloat16x8_t __attribute__((noinline,noclone))
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test_vcopyq_laneq_bf16 (bfloat16x8_t a, bfloat16x8_t b)
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{
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return vcopyq_laneq_bf16 (a, 1, b, 2);
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}
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/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[1\\\], v1.h\\\[2\\\]" 2 } } */
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/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[1\\\], v1.h\\\[0\\\]" 2 } } */
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@ -0,0 +1,18 @@
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/* { dg-do compile { target { aarch64*-*-* } } } */
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/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-add-options arm_v8_2a_bf16_neon } */
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#include <arm_neon.h>
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bfloat16x4_t
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test_vcopy_lane_bf16 (bfloat16x4_t a, bfloat16x4_t b)
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{
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bfloat16x4_t res;
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res = vcopy_lane_bf16 (a, 0, b, 4);
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res = vcopy_lane_bf16 (a, 0, b, -1);
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return res;
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}
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/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
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/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
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@ -0,0 +1,18 @@
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/* { dg-do compile { target { aarch64*-*-* } } } */
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/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-add-options arm_v8_2a_bf16_neon } */
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#include <arm_neon.h>
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bfloat16x4_t
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test_vcopy_lane_bf16 (bfloat16x4_t a, bfloat16x4_t b)
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{
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bfloat16x4_t res;
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res = vcopy_lane_bf16 (a, -1, b, 2);
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res = vcopy_lane_bf16 (a, 4, b, 2);
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return res;
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}
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/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
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/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
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@ -0,0 +1,17 @@
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/* { dg-do compile { target { aarch64*-*-* } } } */
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/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-add-options arm_v8_2a_bf16_neon } */
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#include <arm_neon.h>
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bfloat16x4_t
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test_vcopy_laneq_bf16 (bfloat16x4_t a, bfloat16x8_t b)
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{
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bfloat16x4_t res;
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/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
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res = vcopy_laneq_bf16 (a, -1, b, 2);
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/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
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res = vcopy_laneq_bf16 (a, 4, b, 2);
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return res;
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}
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@ -0,0 +1,17 @@
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/* { dg-do compile { target { aarch64*-*-* } } } */
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/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-add-options arm_v8_2a_bf16_neon } */
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#include <arm_neon.h>
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bfloat16x4_t
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test_vcopy_laneq_bf16 (bfloat16x4_t a, bfloat16x8_t b)
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{
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bfloat16x4_t res;
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/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
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res = vcopy_laneq_bf16 (a, 1, b, -1);
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/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
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res = vcopy_laneq_bf16 (a, 1, b, 8);
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return res;
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}
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@ -0,0 +1,17 @@
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/* { dg-do compile { target { aarch64*-*-* } } } */
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/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-add-options arm_v8_2a_bf16_neon } */
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#include <arm_neon.h>
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bfloat16x8_t
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test_vcopyq_lane_bf16 (bfloat16x8_t a, bfloat16x4_t b)
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{
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bfloat16x8_t res;
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/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
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res = vcopyq_lane_bf16 (a, -1, b, 2);
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/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
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res = vcopyq_lane_bf16 (a, 8, b, 2);
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return res;
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}
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@ -0,0 +1,17 @@
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/* { dg-do compile { target { aarch64*-*-* } } } */
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/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-add-options arm_v8_2a_bf16_neon } */
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#include <arm_neon.h>
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bfloat16x8_t
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test_vcopyq_lane_bf16 (bfloat16x8_t a, bfloat16x4_t b)
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{
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bfloat16x8_t res;
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/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
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res = vcopyq_lane_bf16 (a, 2, b, -1);
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/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
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res = vcopyq_lane_bf16 (a, 2, b, 4);
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return res;
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}
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@ -0,0 +1,17 @@
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/* { dg-do compile { target { aarch64*-*-* } } } */
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/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-add-options arm_v8_2a_bf16_neon } */
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#include <arm_neon.h>
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bfloat16x8_t
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test_vcopyq_laneq_bf16 (bfloat16x8_t a, bfloat16x8_t b)
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{
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bfloat16x8_t res;
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/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
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res = vcopyq_laneq_bf16 (a, -1, b, 2);
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/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
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res = vcopyq_laneq_bf16 (a, 8, b, 2);
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return res;
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}
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@ -0,0 +1,17 @@
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/* { dg-do compile { target { aarch64*-*-* } } } */
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/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-add-options arm_v8_2a_bf16_neon } */
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#include <arm_neon.h>
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bfloat16x8_t
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test_vcopyq_laneq_bf16 (bfloat16x8_t a, bfloat16x8_t b)
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{
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bfloat16x8_t res;
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/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
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res = vcopyq_laneq_bf16 (a, 2, b, -1);
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/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
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res = vcopyq_laneq_bf16 (a, 2, b, 8);
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return res;
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}
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