S/390: Remove TARGET_CPU_ZARCH
TARGET_CPU_ZARCH allowed to distinguish between g5/g6 and newer
machines. Since the former are now gone, we can assume that
TARGET_CPU_ZARCH is always true. As a side-effect, branch splitting
is now completely gone. Some parts of literal pool splitting are also
gone, but it's still there: we need to support it because floating
point and vector instructions still cannot use relative addressing.
gcc/ChangeLog:
2018-08-08 Ilya Leoshkevich <iii@linux.ibm.com>
* config/s390/s390.c (s390_loadrelative_operand_p):
Remove TARGET_CPU_ZARCH usages.
(s390_rtx_costs): Likewise.
(s390_legitimate_constant_p): Likewise.
(s390_cannot_force_const_mem): Likewise.
(legitimate_reload_constant_p): Likewise.
(s390_preferred_reload_class): Likewise.
(legitimize_pic_address): Likewise.
(legitimize_tls_address): Likewise.
(s390_split_branches): Removed.
(s390_add_execute): Removed.
(s390_dump_pool): Remove TARGET_CPU_ZARCH usages.
(s390_mainpool_start): Likewise.
(s390_mainpool_finish): Likewise.
(s390_mainpool_cancel): Removed.
(s390_chunkify_start): Remove TARGET_CPU_ZARCH usages.
(s390_chunkify_cancel): Likewise.
(s390_return_addr_rtx): Likewise.
(s390_register_info): Remove split_branches_pending_p uages.
(s390_optimize_register_info): Likewise.
(s390_init_frame_layout): Remove TARGET_CPU_ZARCH and
split_branches_pending_p usages.
(s390_can_eliminate): Remove TARGET_CPU_ZARCH usages.
(s390_load_got): Likewise.
(s390_expand_split_stack_prologue): Likewise.
(output_asm_nops): Likewise.
(s390_function_profiler): Likewise.
(s390_emit_call): Likewise.
(s390_conditional_register_usage): Likewise.
(s390_optimize_prologue): Likewise.
(s390_reorg): Remove TARGET_CPU_ZARCH and
split_branches_pending_p usages.
(s390_option_override_internal): Remove TARGET_CPU_ZARCH
usages.
(s390_output_indirect_thunk_function): Likewise.
* config/s390/s390.h (TARGET_CPU_ZARCH): Removed.
(TARGET_CPU_ZARCH_P): Removed.
(struct machine_function): Remove split_branches_pending_p.
* config/s390/s390.md: Remove TARGET_CPU_ZARCH usages.
From-SVN: r263394
This commit is contained in:
Ilya Leoshkevich
Andreas Krebbel
parent
52d4aa4fcf
commit
8cc6307c88
4 changed files with 183 additions and 1161 deletions
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@ -1,3 +1,45 @@
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2018-08-08 Ilya Leoshkevich <iii@linux.ibm.com>
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* config/s390/s390.c (s390_loadrelative_operand_p):
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Remove TARGET_CPU_ZARCH usages.
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(s390_rtx_costs): Likewise.
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(s390_legitimate_constant_p): Likewise.
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(s390_cannot_force_const_mem): Likewise.
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(legitimate_reload_constant_p): Likewise.
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(s390_preferred_reload_class): Likewise.
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(legitimize_pic_address): Likewise.
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(legitimize_tls_address): Likewise.
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(s390_split_branches): Removed.
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(s390_add_execute): Removed.
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(s390_dump_pool): Remove TARGET_CPU_ZARCH usages.
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(s390_mainpool_start): Likewise.
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(s390_mainpool_finish): Likewise.
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(s390_mainpool_cancel): Removed.
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(s390_chunkify_start): Remove TARGET_CPU_ZARCH usages.
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(s390_chunkify_cancel): Likewise.
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(s390_return_addr_rtx): Likewise.
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(s390_register_info): Remove split_branches_pending_p uages.
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(s390_optimize_register_info): Likewise.
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(s390_init_frame_layout): Remove TARGET_CPU_ZARCH and
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split_branches_pending_p usages.
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(s390_can_eliminate): Remove TARGET_CPU_ZARCH usages.
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(s390_load_got): Likewise.
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(s390_expand_split_stack_prologue): Likewise.
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(output_asm_nops): Likewise.
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(s390_function_profiler): Likewise.
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(s390_emit_call): Likewise.
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(s390_conditional_register_usage): Likewise.
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(s390_optimize_prologue): Likewise.
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(s390_reorg): Remove TARGET_CPU_ZARCH and
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split_branches_pending_p usages.
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(s390_option_override_internal): Remove TARGET_CPU_ZARCH
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usages.
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(s390_output_indirect_thunk_function): Likewise.
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* config/s390/s390.h (TARGET_CPU_ZARCH): Removed.
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(TARGET_CPU_ZARCH_P): Removed.
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(struct machine_function): Remove split_branches_pending_p.
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* config/s390/s390.md: Remove TARGET_CPU_ZARCH usages.
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2018-08-08 Ilya Leoshkevich <iii@linux.ibm.com>
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* common/config/s390/s390-common.c (processor_flags_table):
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File diff suppressed because it is too large
Load diff
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@ -54,10 +54,6 @@ enum processor_flags
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(s390_arch_flags & PF_IEEE_FLOAT)
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#define TARGET_CPU_IEEE_FLOAT_P(opts) \
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(opts->x_s390_arch_flags & PF_IEEE_FLOAT)
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#define TARGET_CPU_ZARCH \
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(s390_arch_flags & PF_ZARCH)
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#define TARGET_CPU_ZARCH_P(opts) \
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(opts->x_s390_arch_flags & PF_ZARCH)
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#define TARGET_CPU_LONG_DISPLACEMENT \
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(s390_arch_flags & PF_LONG_DISPLACEMENT)
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#define TARGET_CPU_LONG_DISPLACEMENT_P(opts) \
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@ -1119,9 +1115,6 @@ struct GTY(()) machine_function
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/* Literal pool base register. */
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rtx base_reg;
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/* True if we may need to perform branch splitting. */
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bool split_branches_pending_p;
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bool has_landing_pad_p;
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/* True if the current function may contain a tbegin clobbering
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@ -481,7 +481,7 @@
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; mnemonics which only get defined through if_then_else currently
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; don't get added to the list values automatically and hence need to
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; be listed here.
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(define_attr "mnemonic" "b,bas,bc,bcr_flush,unknown" (const_string "unknown"))
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(define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown"))
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;; Length in bytes.
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@ -525,8 +525,7 @@
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(match_test "TARGET_DFP"))
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(const_int 1)
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(and (eq_attr "cpu_facility" "cpu_zarch")
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(match_test "TARGET_CPU_ZARCH"))
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(eq_attr "cpu_facility" "cpu_zarch")
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(const_int 1)
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(and (eq_attr "cpu_facility" "z10")
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@ -1984,7 +1983,7 @@
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(define_insn "*movsi_larl"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(match_operand:SI 1 "larl_operand" "X"))]
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"!TARGET_64BIT && TARGET_CPU_ZARCH
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"!TARGET_64BIT
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&& !FP_REG_P (operands[0])"
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"larl\t%0,%1"
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[(set_attr "op_type" "RIL")
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@ -3225,7 +3224,7 @@
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(use (match_operand 2 "register_operand" ""))
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(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
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(clobber (match_operand 3 "register_operand" ""))]
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"reload_completed && TARGET_CPU_ZARCH"
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"reload_completed"
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[(set (match_dup 3) (label_ref (match_dup 4)))
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(parallel
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[(unspec [(match_dup 2) (mem:BLK (match_dup 3))
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@ -3446,7 +3445,7 @@
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(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
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(clobber (match_operand 2 "register_operand" ""))
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(clobber (reg:CC CC_REGNUM))]
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"reload_completed && TARGET_CPU_ZARCH"
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"reload_completed"
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[(set (match_dup 2) (label_ref (match_dup 3)))
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(parallel
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[(unspec [(match_dup 1) (mem:BLK (match_dup 2))
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@ -3637,7 +3636,7 @@
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(use (match_operand 2 "register_operand" ""))
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(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
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(clobber (match_operand 3 "register_operand" ""))]
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"reload_completed && TARGET_CPU_ZARCH"
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"reload_completed"
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[(set (match_dup 3) (label_ref (match_dup 4)))
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(parallel
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[(unspec [(match_dup 2) (mem:BLK (match_dup 3))
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@ -5600,7 +5599,7 @@
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(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
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(match_operand:DI 2 "general_operand" "do") ) )
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(clobber (reg:CC CC_REGNUM))]
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"!TARGET_ZARCH && TARGET_CPU_ZARCH"
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"!TARGET_ZARCH"
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"#"
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"&& reload_completed"
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[(parallel
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@ -5620,38 +5619,6 @@
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operands[7] = operand_subword (operands[1], 1, 0, DImode);
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operands[8] = operand_subword (operands[2], 1, 0, DImode);")
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(define_insn_and_split "*adddi3_31"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
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(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
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(match_operand:DI 2 "general_operand" "do") ) )
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(clobber (reg:CC CC_REGNUM))]
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"!TARGET_CPU_ZARCH"
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"#"
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"&& reload_completed"
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[(parallel
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[(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
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(clobber (reg:CC CC_REGNUM))])
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(parallel
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[(set (reg:CCL1 CC_REGNUM)
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(compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
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(match_dup 7)))
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(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
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(set (pc)
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(if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
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(pc)
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(label_ref (match_dup 9))))
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(parallel
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[(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
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(clobber (reg:CC CC_REGNUM))])
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(match_dup 9)]
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"operands[3] = operand_subword (operands[0], 0, 0, DImode);
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operands[4] = operand_subword (operands[1], 0, 0, DImode);
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operands[5] = operand_subword (operands[2], 0, 0, DImode);
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operands[6] = operand_subword (operands[0], 1, 0, DImode);
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operands[7] = operand_subword (operands[1], 1, 0, DImode);
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operands[8] = operand_subword (operands[2], 1, 0, DImode);
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operands[9] = gen_label_rtx ();")
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;
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; addsi3 instruction pattern(s).
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;
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@ -6102,7 +6069,7 @@
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(minus:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:DI 2 "general_operand" "do") ) )
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(clobber (reg:CC CC_REGNUM))]
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"!TARGET_ZARCH && TARGET_CPU_ZARCH"
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"!TARGET_ZARCH"
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"#"
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"&& reload_completed"
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[(parallel
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@ -6121,38 +6088,6 @@
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operands[7] = operand_subword (operands[1], 1, 0, DImode);
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operands[8] = operand_subword (operands[2], 1, 0, DImode);")
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(define_insn_and_split "*subdi3_31"
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[(set (match_operand:DI 0 "register_operand" "=&d")
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(minus:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:DI 2 "general_operand" "do") ) )
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(clobber (reg:CC CC_REGNUM))]
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"!TARGET_CPU_ZARCH"
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"#"
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"&& reload_completed"
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[(parallel
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[(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
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(clobber (reg:CC CC_REGNUM))])
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(parallel
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[(set (reg:CCL2 CC_REGNUM)
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(compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
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(match_dup 7)))
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(set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
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(set (pc)
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(if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
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(pc)
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(label_ref (match_dup 9))))
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(parallel
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[(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
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(clobber (reg:CC CC_REGNUM))])
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(match_dup 9)]
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"operands[3] = operand_subword (operands[0], 0, 0, DImode);
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operands[4] = operand_subword (operands[1], 0, 0, DImode);
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operands[5] = operand_subword (operands[2], 0, 0, DImode);
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operands[6] = operand_subword (operands[0], 1, 0, DImode);
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operands[7] = operand_subword (operands[1], 1, 0, DImode);
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operands[8] = operand_subword (operands[2], 1, 0, DImode);
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operands[9] = gen_label_rtx ();")
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;
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; subsi3 instruction pattern(s).
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;
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@ -6393,7 +6328,7 @@
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(match_dup 1)))
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(set (match_operand:GPR 0 "register_operand" "=d,d")
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(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
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"s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
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"s390_match_ccmode (insn, CCL1mode)"
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"@
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alc<g>r\t%0,%2
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alc<g>\t%0,%2"
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@ -6409,7 +6344,7 @@
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(match_operand:GPR 2 "general_operand" "d,T"))
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(match_dup 1)))
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(clobber (match_scratch:GPR 0 "=d,d"))]
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"s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
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"s390_match_ccmode (insn, CCL1mode)"
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"@
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alc<g>r\t%0,%2
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alc<g>\t%0,%2"
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@ -6428,7 +6363,7 @@
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(match_dup 2)))
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(set (match_operand:GPR 0 "register_operand" "=d,d")
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(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
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"s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
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"s390_match_ccmode (insn, CCL1mode)"
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"@
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alc<g>r\t%0,%2
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alc<g>\t%0,%2"
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@ -6443,7 +6378,7 @@
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(match_operand:GPR 2 "general_operand" "d,T"))
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(match_dup 2)))
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(clobber (match_scratch:GPR 0 "=d,d"))]
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"s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
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"s390_match_ccmode (insn, CCL1mode)"
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"@
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alc<g>r\t%0,%2
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alc<g>\t%0,%2"
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@ -6459,7 +6394,7 @@
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(const_int 0)))
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(set (match_operand:GPR 0 "register_operand" "=d,d")
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(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
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"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
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"s390_match_ccmode (insn, CCLmode)"
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"@
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alc<g>r\t%0,%2
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alc<g>\t%0,%2"
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@ -6472,7 +6407,7 @@
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(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
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(match_operand:GPR 2 "general_operand" "d,T")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_CPU_ZARCH"
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""
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"@
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alc<g>r\t%0,%2
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alc<g>\t%0,%2"
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@ -6488,7 +6423,7 @@
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(const_int 0)))
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(set (match_operand:GPR 0 "register_operand" "=d,d")
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(minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
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"s390_match_ccmode (insn, CCLmode)"
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"@
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slb<g>r\t%0,%2
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slb<g>\t%0,%2"
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@ -6502,7 +6437,7 @@
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(match_operand:GPR 2 "general_operand" "d,T"))
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(match_operand:GPR 3 "s390_slb_comparison" "")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_CPU_ZARCH"
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""
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"@
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slb<g>r\t%0,%2
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slb<g>\t%0,%2"
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@ -6514,7 +6449,7 @@
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(match_operand 1 "comparison_operator" "")
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(match_operand:GPR 2 "register_operand" "")
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(match_operand:GPR 3 "const_int_operand" "")]
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"TARGET_CPU_ZARCH"
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""
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"if (!s390_expand_addcc (GET_CODE (operands[1]),
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XEXP (operands[1], 0), XEXP (operands[1], 1),
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operands[0], operands[2],
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@ -6528,7 +6463,7 @@
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[(set (match_operand:GPR 0 "register_operand" "=&d")
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(match_operand:GPR 1 "s390_alc_comparison" ""))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_CPU_ZARCH"
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""
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"#"
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"&& reload_completed"
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[(set (match_dup 0) (const_int 0))
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@ -6542,7 +6477,7 @@
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[(set (match_operand:GPR 0 "register_operand" "=&d")
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(match_operand:GPR 1 "s390_slb_comparison" ""))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_CPU_ZARCH"
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""
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"#"
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"&& reload_completed"
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[(set (match_dup 0) (const_int 0))
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@ -6561,7 +6496,7 @@
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(match_operator:SI 1 "s390_scond_operator"
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[(match_operand:GPR 2 "register_operand" "")
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(match_operand:GPR 3 "general_operand" "")]))]
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"TARGET_CPU_ZARCH"
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""
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"if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
|
||||
operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
|
||||
|
||||
|
|
@ -6796,7 +6731,7 @@
|
|||
(match_operand:<DWH> 1 "register_operand" "%0,0"))
|
||||
(zero_extend:DW
|
||||
(match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
"@
|
||||
ml<tg>r\t%0,%2
|
||||
ml<tg>\t%0,%2"
|
||||
|
|
@ -7058,7 +6993,7 @@
|
|||
(set (match_operand:SI 3 "general_operand" "")
|
||||
(umod:SI (match_dup 1) (match_dup 2)))])
|
||||
(clobber (match_dup 4))]
|
||||
"!TARGET_ZARCH && TARGET_CPU_ZARCH"
|
||||
"!TARGET_ZARCH"
|
||||
{
|
||||
rtx div_equal, mod_equal, equal;
|
||||
rtx_insn *insn;
|
||||
|
|
@ -7101,187 +7036,13 @@
|
|||
(zero_extend:DI
|
||||
(truncate:SI
|
||||
(udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
|
||||
"!TARGET_ZARCH && TARGET_CPU_ZARCH"
|
||||
"!TARGET_ZARCH"
|
||||
"@
|
||||
dlr\t%0,%2
|
||||
dl\t%0,%2"
|
||||
[(set_attr "op_type" "RRE,RXY")
|
||||
(set_attr "type" "idiv")])
|
||||
|
||||
(define_expand "udivsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(udiv:SI (match_operand:SI 1 "general_operand" "")
|
||||
(match_operand:SI 2 "general_operand" "")))
|
||||
(clobber (match_dup 3))]
|
||||
"!TARGET_ZARCH && !TARGET_CPU_ZARCH"
|
||||
{
|
||||
rtx udiv_equal, umod_equal, equal;
|
||||
rtx_insn *insn;
|
||||
|
||||
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
|
||||
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
|
||||
equal = gen_rtx_IOR (DImode,
|
||||
gen_rtx_ASHIFT (DImode,
|
||||
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
|
||||
GEN_INT (32)),
|
||||
gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
|
||||
|
||||
operands[3] = gen_reg_rtx (DImode);
|
||||
|
||||
if (CONSTANT_P (operands[2]))
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
|
||||
{
|
||||
rtx_code_label *label1 = gen_label_rtx ();
|
||||
|
||||
operands[1] = make_safe_from (operands[1], operands[0]);
|
||||
emit_move_insn (operands[0], const0_rtx);
|
||||
emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
|
||||
SImode, 1, label1);
|
||||
emit_move_insn (operands[0], const1_rtx);
|
||||
emit_label (label1);
|
||||
}
|
||||
else
|
||||
{
|
||||
operands[2] = force_reg (SImode, operands[2]);
|
||||
operands[2] = make_safe_from (operands[2], operands[0]);
|
||||
|
||||
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
|
||||
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
|
||||
operands[2]));
|
||||
set_unique_reg_note (insn, REG_EQUAL, equal);
|
||||
|
||||
insn = emit_move_insn (operands[0],
|
||||
gen_lowpart (SImode, operands[3]));
|
||||
set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
rtx_code_label *label1 = gen_label_rtx ();
|
||||
rtx_code_label *label2 = gen_label_rtx ();
|
||||
rtx_code_label *label3 = gen_label_rtx ();
|
||||
|
||||
operands[1] = force_reg (SImode, operands[1]);
|
||||
operands[1] = make_safe_from (operands[1], operands[0]);
|
||||
operands[2] = force_reg (SImode, operands[2]);
|
||||
operands[2] = make_safe_from (operands[2], operands[0]);
|
||||
|
||||
emit_move_insn (operands[0], const0_rtx);
|
||||
emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
|
||||
SImode, 1, label3);
|
||||
emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
|
||||
SImode, 0, label2);
|
||||
emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
|
||||
SImode, 0, label1);
|
||||
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
|
||||
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
|
||||
operands[2]));
|
||||
set_unique_reg_note (insn, REG_EQUAL, equal);
|
||||
|
||||
insn = emit_move_insn (operands[0],
|
||||
gen_lowpart (SImode, operands[3]));
|
||||
set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
|
||||
|
||||
emit_jump (label3);
|
||||
emit_label (label1);
|
||||
emit_move_insn (operands[0], operands[1]);
|
||||
emit_jump (label3);
|
||||
emit_label (label2);
|
||||
emit_move_insn (operands[0], const1_rtx);
|
||||
emit_label (label3);
|
||||
}
|
||||
emit_move_insn (operands[0], operands[0]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "umodsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
|
||||
(match_operand:SI 2 "nonimmediate_operand" "")))
|
||||
(clobber (match_dup 3))]
|
||||
"!TARGET_ZARCH && !TARGET_CPU_ZARCH"
|
||||
{
|
||||
rtx udiv_equal, umod_equal, equal;
|
||||
rtx_insn *insn;
|
||||
|
||||
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
|
||||
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
|
||||
equal = gen_rtx_IOR (DImode,
|
||||
gen_rtx_ASHIFT (DImode,
|
||||
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
|
||||
GEN_INT (32)),
|
||||
gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
|
||||
|
||||
operands[3] = gen_reg_rtx (DImode);
|
||||
|
||||
if (CONSTANT_P (operands[2]))
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
|
||||
{
|
||||
rtx_code_label *label1 = gen_label_rtx ();
|
||||
|
||||
operands[1] = make_safe_from (operands[1], operands[0]);
|
||||
emit_move_insn (operands[0], operands[1]);
|
||||
emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
|
||||
SImode, 1, label1);
|
||||
emit_insn (gen_abssi2 (operands[0], operands[2]));
|
||||
emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
|
||||
emit_label (label1);
|
||||
}
|
||||
else
|
||||
{
|
||||
operands[2] = force_reg (SImode, operands[2]);
|
||||
operands[2] = make_safe_from (operands[2], operands[0]);
|
||||
|
||||
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
|
||||
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
|
||||
operands[2]));
|
||||
set_unique_reg_note (insn, REG_EQUAL, equal);
|
||||
|
||||
insn = emit_move_insn (operands[0],
|
||||
gen_highpart (SImode, operands[3]));
|
||||
set_unique_reg_note (insn, REG_EQUAL, umod_equal);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
rtx_code_label *label1 = gen_label_rtx ();
|
||||
rtx_code_label *label2 = gen_label_rtx ();
|
||||
rtx_code_label *label3 = gen_label_rtx ();
|
||||
|
||||
operands[1] = force_reg (SImode, operands[1]);
|
||||
operands[1] = make_safe_from (operands[1], operands[0]);
|
||||
operands[2] = force_reg (SImode, operands[2]);
|
||||
operands[2] = make_safe_from (operands[2], operands[0]);
|
||||
|
||||
emit_move_insn(operands[0], operands[1]);
|
||||
emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
|
||||
SImode, 1, label3);
|
||||
emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
|
||||
SImode, 0, label2);
|
||||
emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
|
||||
SImode, 0, label1);
|
||||
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
|
||||
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
|
||||
operands[2]));
|
||||
set_unique_reg_note (insn, REG_EQUAL, equal);
|
||||
|
||||
insn = emit_move_insn (operands[0],
|
||||
gen_highpart (SImode, operands[3]));
|
||||
set_unique_reg_note (insn, REG_EQUAL, umod_equal);
|
||||
|
||||
emit_jump (label3);
|
||||
emit_label (label1);
|
||||
emit_move_insn (operands[0], const0_rtx);
|
||||
emit_jump (label3);
|
||||
emit_label (label2);
|
||||
emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
|
||||
emit_label (label3);
|
||||
}
|
||||
DONE;
|
||||
})
|
||||
|
||||
;
|
||||
; div(df|sf)3 instruction pattern(s).
|
||||
;
|
||||
|
|
@ -8888,7 +8649,7 @@
|
|||
[(set (match_operand:GPR 0 "register_operand" "")
|
||||
(rotate:GPR (match_operand:GPR 1 "register_operand" "")
|
||||
(match_operand:SI 2 "nonmemory_operand" "")))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
"")
|
||||
|
||||
; rll, rllg
|
||||
|
|
@ -8896,7 +8657,7 @@
|
|||
[(set (match_operand:GPR 0 "register_operand" "=d")
|
||||
(rotate:GPR (match_operand:GPR 1 "register_operand" "d")
|
||||
(match_operand:SI 2 "nonmemory_operand" "an")))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
"rll<g>\t%0,%1,<addr_style_op_ops>"
|
||||
[(set_attr "op_type" "RSE")
|
||||
(set_attr "atype" "reg")
|
||||
|
|
@ -9042,7 +8803,7 @@
|
|||
(match_operand 2 "const_int_operand" "")])
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
{
|
||||
if (get_attr_length (insn) == 4)
|
||||
return "j%C1\t%l0";
|
||||
|
|
@ -9055,27 +8816,6 @@
|
|||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 6)))])
|
||||
|
||||
(define_insn "*cjump_31"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(match_operator 1 "s390_comparison" [(reg CC_REGNUM)
|
||||
(match_operand 2 "const_int_operand" "")])
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
"!TARGET_CPU_ZARCH"
|
||||
{
|
||||
gcc_assert (get_attr_length (insn) == 4);
|
||||
return "j%C1\t%l0";
|
||||
}
|
||||
[(set_attr "op_type" "RI")
|
||||
(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (not (match_test "flag_pic"))
|
||||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 6))
|
||||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 8))))])
|
||||
|
||||
(define_insn "*cjump_long"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
|
|
@ -9139,7 +8879,7 @@
|
|||
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
|
||||
(pc)
|
||||
(label_ref (match_operand 0 "" ""))))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
{
|
||||
if (get_attr_length (insn) == 4)
|
||||
return "j%D1\t%l0";
|
||||
|
|
@ -9152,26 +8892,6 @@
|
|||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 6)))])
|
||||
|
||||
(define_insn "*icjump_31"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
|
||||
(pc)
|
||||
(label_ref (match_operand 0 "" ""))))]
|
||||
"!TARGET_CPU_ZARCH"
|
||||
{
|
||||
gcc_assert (get_attr_length (insn) == 4);
|
||||
return "j%D1\t%l0";
|
||||
}
|
||||
[(set_attr "op_type" "RI")
|
||||
(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (not (match_test "flag_pic"))
|
||||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 6))
|
||||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 8))))])
|
||||
|
||||
(define_insn "*icjump_long"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
|
|
@ -9307,7 +9027,7 @@
|
|||
(set (match_operand:GPR 4 "nonimmediate_operand" "")
|
||||
(plus:GPR (match_dup 1) (match_dup 2)))
|
||||
(clobber (match_scratch:GPR 5 ""))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
"#"
|
||||
"!reload_completed && !reload_in_progress"
|
||||
[(set (match_dup 7) (match_dup 2)) ; the increment
|
||||
|
|
@ -9433,7 +9153,7 @@
|
|||
(subreg:SI (match_dup 2) 0)))
|
||||
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
|
||||
(clobber (reg:CC CC_REGNUM))]
|
||||
"!TARGET_ZARCH && TARGET_CPU_ZARCH"
|
||||
"!TARGET_ZARCH"
|
||||
{
|
||||
if (which_alternative != 0)
|
||||
return "#";
|
||||
|
|
@ -9468,9 +9188,7 @@
|
|||
(use (match_operand 1 "" ""))] ; label
|
||||
""
|
||||
{
|
||||
if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
|
||||
emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
|
||||
else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
|
||||
if (GET_MODE (operands[0]) == SImode)
|
||||
emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
|
||||
else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
|
||||
emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
|
||||
|
|
@ -9491,7 +9209,7 @@
|
|||
(plus:SI (match_dup 1) (const_int -1)))
|
||||
(clobber (match_scratch:SI 3 "=X,&1,&?d"))
|
||||
(clobber (reg:CC CC_REGNUM))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
{
|
||||
if (which_alternative != 0)
|
||||
return "#";
|
||||
|
|
@ -9522,77 +9240,6 @@
|
|||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 10)))])
|
||||
|
||||
(define_insn_and_split "doloop_si31"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(ne (match_operand:SI 1 "register_operand" "d,d,d")
|
||||
(const_int 1))
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))
|
||||
(set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
|
||||
(plus:SI (match_dup 1) (const_int -1)))
|
||||
(clobber (match_scratch:SI 3 "=X,&1,&?d"))
|
||||
(clobber (reg:CC CC_REGNUM))]
|
||||
"!TARGET_CPU_ZARCH"
|
||||
{
|
||||
if (which_alternative != 0)
|
||||
return "#";
|
||||
else if (get_attr_length (insn) == 4)
|
||||
return "brct\t%1,%l0";
|
||||
else
|
||||
gcc_unreachable ();
|
||||
}
|
||||
"&& reload_completed
|
||||
&& (! REG_P (operands[2])
|
||||
|| ! rtx_equal_p (operands[1], operands[2]))"
|
||||
[(set (match_dup 3) (match_dup 1))
|
||||
(parallel [(set (reg:CCAN CC_REGNUM)
|
||||
(compare:CCAN (plus:SI (match_dup 3) (const_int -1))
|
||||
(const_int 0)))
|
||||
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
|
||||
(set (match_dup 2) (match_dup 3))
|
||||
(set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
|
||||
(label_ref (match_dup 0))
|
||||
(pc)))]
|
||||
""
|
||||
[(set_attr "op_type" "RI")
|
||||
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
|
||||
; hurt us in the (rare) case of ahi.
|
||||
(set_attr "z10prop" "z10_super_E1")
|
||||
(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (not (match_test "flag_pic"))
|
||||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 6))
|
||||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 8))))])
|
||||
|
||||
(define_insn "*doloop_si_long"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(ne (match_operand:SI 1 "register_operand" "d")
|
||||
(const_int 1))
|
||||
(match_operand 0 "address_operand" "ZR")
|
||||
(pc)))
|
||||
(set (match_operand:SI 2 "register_operand" "=1")
|
||||
(plus:SI (match_dup 1) (const_int -1)))
|
||||
(clobber (match_scratch:SI 3 "=X"))
|
||||
(clobber (reg:CC CC_REGNUM))]
|
||||
"!TARGET_CPU_ZARCH"
|
||||
{
|
||||
if (get_attr_op_type (insn) == OP_TYPE_RR)
|
||||
return "bctr\t%1,%0";
|
||||
else
|
||||
return "bct\t%1,%a0";
|
||||
}
|
||||
[(set (attr "op_type")
|
||||
(if_then_else (match_operand 0 "register_operand" "")
|
||||
(const_string "RR") (const_string "RX")))
|
||||
(set_attr "type" "branch")
|
||||
(set_attr "atype" "agen")
|
||||
(set_attr "z10prop" "z10_c")
|
||||
(set_attr "z196prop" "z196_cracked")])
|
||||
|
||||
(define_insn_and_split "doloop_di"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
|
|
@ -9650,7 +9297,7 @@
|
|||
|
||||
(define_insn "*jump64"
|
||||
[(set (pc) (label_ref (match_operand 0 "" "")))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
{
|
||||
if (get_attr_length (insn) == 4)
|
||||
return "j\t%l0";
|
||||
|
|
@ -9663,22 +9310,6 @@
|
|||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 6)))])
|
||||
|
||||
(define_insn "*jump31"
|
||||
[(set (pc) (label_ref (match_operand 0 "" "")))]
|
||||
"!TARGET_CPU_ZARCH"
|
||||
{
|
||||
gcc_assert (get_attr_length (insn) == 4);
|
||||
return "j\t%l0";
|
||||
}
|
||||
[(set_attr "op_type" "RI")
|
||||
(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (not (match_test "flag_pic"))
|
||||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 6))
|
||||
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
||||
(const_int 4) (const_int 8))))])
|
||||
|
||||
;
|
||||
; indirect-jump instruction pattern(s).
|
||||
;
|
||||
|
|
@ -10147,7 +9778,7 @@
|
|||
(define_insn "*sibcall_brcl"
|
||||
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
|
||||
(match_operand 1 "const_int_operand" "n"))]
|
||||
"SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
|
||||
"SIBLING_CALL_P (insn)"
|
||||
"jg\t%0"
|
||||
[(set_attr "op_type" "RIL")
|
||||
(set_attr "type" "branch")])
|
||||
|
|
@ -10209,7 +9840,7 @@
|
|||
[(set (match_operand 0 "" "")
|
||||
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
|
||||
(match_operand 2 "const_int_operand" "n")))]
|
||||
"SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
|
||||
"SIBLING_CALL_P (insn)"
|
||||
"jg\t%1"
|
||||
[(set_attr "op_type" "RIL")
|
||||
(set_attr "type" "branch")])
|
||||
|
|
@ -10247,7 +9878,7 @@
|
|||
(match_operand 1 "const_int_operand" "n"))
|
||||
(clobber (match_operand 2 "register_operand" "=r"))]
|
||||
"!SIBLING_CALL_P (insn)
|
||||
&& TARGET_CPU_ZARCH
|
||||
|
||||
&& GET_MODE (operands[2]) == Pmode"
|
||||
"brasl\t%2,%0"
|
||||
[(set_attr "op_type" "RIL")
|
||||
|
|
@ -10353,7 +9984,7 @@
|
|||
(match_operand 2 "const_int_operand" "n")))
|
||||
(clobber (match_operand 3 "register_operand" "=r"))]
|
||||
"!SIBLING_CALL_P (insn)
|
||||
&& TARGET_CPU_ZARCH
|
||||
|
||||
&& GET_MODE (operands[3]) == Pmode"
|
||||
"brasl\t%3,%1"
|
||||
[(set_attr "op_type" "RIL")
|
||||
|
|
@ -10496,7 +10127,7 @@
|
|||
(clobber (match_operand 3 "register_operand" "=r"))
|
||||
(use (match_operand 4 "" ""))]
|
||||
"!SIBLING_CALL_P (insn)
|
||||
&& TARGET_CPU_ZARCH
|
||||
|
||||
&& GET_MODE (operands[3]) == Pmode"
|
||||
"brasl\t%3,%1%J4"
|
||||
[(set_attr "op_type" "RIL")
|
||||
|
|
@ -11034,7 +10665,7 @@
|
|||
|
||||
(define_insn "nop_6_byte"
|
||||
[(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
"brcl\t0, 0"
|
||||
[(set_attr "op_type" "RIL")])
|
||||
|
||||
|
|
@ -11082,28 +10713,10 @@
|
|||
}
|
||||
[(set_attr "length" "0")])
|
||||
|
||||
(define_insn "main_base_31_small"
|
||||
[(set (match_operand 0 "register_operand" "=a")
|
||||
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
|
||||
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
||||
"basr\t%0,0"
|
||||
[(set_attr "op_type" "RR")
|
||||
(set_attr "type" "la")
|
||||
(set_attr "z196prop" "z196_cracked")])
|
||||
|
||||
(define_insn "main_base_31_large"
|
||||
[(set (match_operand 0 "register_operand" "=a")
|
||||
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
|
||||
(set (pc) (label_ref (match_operand 2 "" "")))]
|
||||
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
||||
"bras\t%0,%2"
|
||||
[(set_attr "op_type" "RI")
|
||||
(set_attr "z196prop" "z196_cracked")])
|
||||
|
||||
(define_insn "main_base_64"
|
||||
[(set (match_operand 0 "register_operand" "=a")
|
||||
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
|
||||
"TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
||||
"GET_MODE (operands[0]) == Pmode"
|
||||
"larl\t%0,%1"
|
||||
[(set_attr "op_type" "RIL")
|
||||
(set_attr "type" "larl")
|
||||
|
|
@ -11117,22 +10730,12 @@
|
|||
gcc_unreachable ();
|
||||
}
|
||||
[(set (attr "type")
|
||||
(if_then_else (match_test "TARGET_CPU_ZARCH")
|
||||
(const_string "larl") (const_string "la")))])
|
||||
|
||||
(define_insn "reload_base_31"
|
||||
[(set (match_operand 0 "register_operand" "=a")
|
||||
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
|
||||
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
||||
"basr\t%0,0\;la\t%0,%1-.(%0)"
|
||||
[(set_attr "length" "6")
|
||||
(set_attr "type" "la")
|
||||
(set_attr "z196prop" "z196_cracked")])
|
||||
(const_string "larl"))])
|
||||
|
||||
(define_insn "reload_base_64"
|
||||
[(set (match_operand 0 "register_operand" "=a")
|
||||
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
|
||||
"TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
||||
"GET_MODE (operands[0]) == Pmode"
|
||||
"larl\t%0,%1"
|
||||
[(set_attr "op_type" "RIL")
|
||||
(set_attr "type" "larl")
|
||||
|
|
@ -11416,7 +11019,7 @@
|
|||
(define_insn "bswap<mode>2"
|
||||
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
|
||||
(bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
"@
|
||||
lrv<g>r\t%0,%1
|
||||
lrv<g>\t%0,%1
|
||||
|
|
@ -11428,7 +11031,7 @@
|
|||
(define_insn "bswaphi2"
|
||||
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T")
|
||||
(bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
"@
|
||||
#
|
||||
lrvh\t%0,%1
|
||||
|
|
@ -11440,7 +11043,7 @@
|
|||
(define_split
|
||||
[(set (match_operand:HI 0 "register_operand" "")
|
||||
(bswap:HI (match_operand:HI 1 "register_operand" "")))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
[(set (match_dup 2) (bswap:SI (match_dup 3)))
|
||||
(set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
|
||||
{
|
||||
|
|
@ -11878,7 +11481,7 @@
|
|||
(match_operand 2 "const_int_operand" "X")
|
||||
(match_operand 3 "const_int_operand" "X")]
|
||||
UNSPECV_SPLIT_STACK_DATA)]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
{
|
||||
switch_to_section (targetm.asm_out.function_rodata_section
|
||||
(current_function_decl));
|
||||
|
|
@ -11913,7 +11516,7 @@
|
|||
(define_expand "split_stack_call"
|
||||
[(match_operand 0 "bras_sym_operand" "X")
|
||||
(match_operand 1 "" "")]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
{
|
||||
if (TARGET_64BIT)
|
||||
emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
|
||||
|
|
@ -11927,7 +11530,7 @@
|
|||
(set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
|
||||
(reg:P 1)]
|
||||
UNSPECV_SPLIT_STACK_CALL))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
"jg\t%0"
|
||||
[(set_attr "op_type" "RIL")
|
||||
(set_attr "type" "branch")])
|
||||
|
|
@ -11938,7 +11541,7 @@
|
|||
[(match_operand 0 "bras_sym_operand" "X")
|
||||
(match_operand 1 "" "")
|
||||
(match_operand 2 "" "")]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
{
|
||||
if (TARGET_64BIT)
|
||||
emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
|
||||
|
|
@ -11956,7 +11559,7 @@
|
|||
(set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
|
||||
(reg:P 1)]
|
||||
UNSPECV_SPLIT_STACK_CALL))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
""
|
||||
"jg%C1\t%0"
|
||||
[(set_attr "op_type" "RIL")
|
||||
(set_attr "type" "branch")])
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue