From 8c5fd59f94de0dd09cd451c532fe746dab52dfca Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Wed, 14 Mar 2007 08:47:32 +0100 Subject: [PATCH] invoke.texi (i386 and x86-64 Options): Clarify -msahf option. * doc/invoke.texi (i386 and x86-64 Options): Clarify -msahf option. From-SVN: r122910 --- gcc/ChangeLog | 4 ++++ gcc/doc/invoke.texi | 11 ++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1e5a199e178..97d34f3c04e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2007-03-14 Uros Bizjak + + * doc/invoke.texi (i386 and x86-64 Options): Clarify -msahf option. + 2007-03-13 Seongbae Park PR tree-optimization/30590 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d5a5da58104..60122e0a891 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -10091,11 +10091,12 @@ atomic built-in functions: see @ref{Atomic Builtins} for details. @item -msahf @opindex -msahf -This option will enable GCC to use SAHF instruction in generated code. Early -Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported by AMD64 -until introduction of Pentium 4 G1 step in December 2005. LAHF and SAHF are -load and store instructions, respectively, for certain status flags. These -instructions are used for virtualization and floating-point condition handling. +This option will enable GCC to use SAHF instruction in generated 64-bit code. +Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported +by AMD64 until introduction of Pentium 4 G1 step in December 2005. LAHF and +SAHF are load and store instructions, respectively, for certain status flags. +In 64-bit mode, SAHF instruction is used to optimize @code{fmod}, @code{drem} +or @code{remainder} built-in functions: see @ref{Other Builtins} for details. @item -mpush-args @itemx -mno-push-args