Implement light-weight DImode support.
gcc/ Implement light-weight DImode support. * config/avr/avr-dimode.md: New file. * config/avr/avr.md: Include it. (adjust_len): Add plus64, compare64. (HIDI): Remove code iterator. (code_stdname): New code attribute. (rotx, rotsmode): Remove DI. (rotl<mode>3, *rotw<mode>, *rotb<mode>): Use HISI instead of HIDI as code iterator. * config/avr/avr-protos.h (avr_have_dimode): New. (avr_out_plus64, avr_out_compare64): New. * config/avr/avr.c (avr_out_compare): Handle DImode. (avr_have_dimode): New variable definition and initialization. (avr_out_compare64, avr_out_plus64): New functions. (avr_out_plus_1): Use simplify_unary_operation to negate xval. (adjust_insn_length): Handle ADJUST_LEN_COMPARE64, ADJUST_LEN_PLUS64. (avr_compare_pattern): Skip DImode comparisons. libgcc/ Implement light-weight DImode support. * config/avr/t-avr (LIB1ASMFUNCS): Add _adddi3, _adddi3_s8, _subdi3, _cmpdi2, _cmpdi2_s8, _rotldi3. * config/avr/lib1funcs.S (__adddi3, __adddi3_s8, __subdi3, __cmpdi2, __cmpdi2_s8, __rotldi3): New functions. From-SVN: r182794
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
5f595f1675
commit
8c57e5473e
8 changed files with 482 additions and 32 deletions
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@ -1,3 +1,23 @@
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2012-01-02 Georg-Johann Lay <avr@gjlay.de>
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Implement light-weight DImode support.
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* config/avr/avr-dimode.md: New file.
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* config/avr/avr.md: Include it.
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(adjust_len): Add plus64, compare64.
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(HIDI): Remove code iterator.
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(code_stdname): New code attribute.
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(rotx, rotsmode): Remove DI.
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(rotl<mode>3, *rotw<mode>, *rotb<mode>): Use HISI instead of HIDI
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as code iterator.
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* config/avr/avr-protos.h (avr_have_dimode): New.
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(avr_out_plus64, avr_out_compare64): New.
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* config/avr/avr.c (avr_out_compare): Handle DImode.
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(avr_have_dimode): New variable definition and initialization.
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(avr_out_compare64, avr_out_plus64): New functions.
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(avr_out_plus_1): Use simplify_unary_operation to negate xval.
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(adjust_insn_length): Handle ADJUST_LEN_COMPARE64, ADJUST_LEN_PLUS64.
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(avr_compare_pattern): Skip DImode comparisons.
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2012-01-02 Revital Eres <revital.eres@linaro.org>
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* ddg.c (def_has_ccmode_p): New function.
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283
gcc/config/avr/avr-dimode.md
Normal file
283
gcc/config/avr/avr-dimode.md
Normal file
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@ -0,0 +1,283 @@
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;; Machine description for GNU compiler,
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;; for Atmel AVR micro controllers.
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;; Copyright (C) 1998 - 2011
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;; Free Software Foundation, Inc.
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;; Contributed by Georg Lay (avr@gjlay.de)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The purpose of this file is to provide a light-weight DImode
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;; implementation for AVR. The trouble with DImode is that tree -> RTL
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;; lowering leads to really unpleasant code for operations that don't
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;; work byte-wise like NEG, PLUS, MINUS, etc. Defining optabs entries for
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;; them won't help because the optab machinery assumes these operations
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;; are cheap and does not check if a libgcc implementation is available.
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;;
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;; The DImode insns are all straight forward -- except movdi. The approach
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;; of this implementation is to provide DImode insns without the burden of
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;; introducing movdi.
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;;
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;; The caveat is that if there are insns for some mode, there must also be a
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;; respective move insn that describes reloads. Therefore, this
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;; implementation uses an accumulator-based model with two hard-coded,
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;; accumulator-like registers
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;;
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;; A[] = reg:DI 18
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;; B[] = reg:DI 10
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;;
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;; so that no DImode insn contains pseudos or needs reloading.
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(define_constants
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[(ACC_A 18)
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(ACC_B 10)])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Addition
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "adddi3"
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[(parallel [(match_operand:DI 0 "general_operand" "")
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(match_operand:DI 1 "general_operand" "")
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(match_operand:DI 2 "general_operand" "")])]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (DImode, ACC_A);
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emit_move_insn (acc_a, operands[1]);
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if (s8_operand (operands[2], VOIDmode))
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{
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emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
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emit_insn (gen_adddi3_const8_insn ());
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}
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else if (CONST_INT_P (operands[2])
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|| CONST_DOUBLE_P (operands[2]))
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{
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emit_insn (gen_adddi3_const_insn (operands[2]));
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}
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else
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{
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emit_move_insn (gen_rtx_REG (DImode, ACC_B), operands[2]);
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emit_insn (gen_adddi3_insn ());
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}
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emit_move_insn (operands[0], acc_a);
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DONE;
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})
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(define_insn "adddi3_insn"
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[(set (reg:DI ACC_A)
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(plus:DI (reg:DI ACC_A)
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(reg:DI ACC_B)))]
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"avr_have_dimode"
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"%~call __adddi3"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "clobber")])
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(define_insn "adddi3_const8_insn"
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[(set (reg:DI ACC_A)
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(plus:DI (reg:DI ACC_A)
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(sign_extend:DI (reg:QI REG_X))))]
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"avr_have_dimode"
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"%~call __adddi3_s8"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "clobber")])
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(define_insn "adddi3_const_insn"
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[(set (reg:DI ACC_A)
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(plus:DI (reg:DI ACC_A)
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(match_operand:DI 0 "const_double_operand" "n")))]
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"avr_have_dimode
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&& !s8_operand (operands[0], VOIDmode)"
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{
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return avr_out_plus64 (operands[0], NULL);
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}
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[(set_attr "adjust_len" "plus64")
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(set_attr "cc" "clobber")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Subtraction
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "subdi3"
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[(parallel [(match_operand:DI 0 "general_operand" "")
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(match_operand:DI 1 "general_operand" "")
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(match_operand:DI 2 "general_operand" "")])]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (DImode, ACC_A);
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emit_move_insn (acc_a, operands[1]);
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emit_move_insn (gen_rtx_REG (DImode, ACC_B), operands[2]);
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emit_insn (gen_subdi3_insn ());
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emit_move_insn (operands[0], acc_a);
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DONE;
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})
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(define_insn "subdi3_insn"
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[(set (reg:DI ACC_A)
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(minus:DI (reg:DI ACC_A)
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(reg:DI ACC_B)))]
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"avr_have_dimode"
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"%~call __subdi3"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "set_czn")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Negation
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "negdi2"
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[(parallel [(match_operand:DI 0 "general_operand" "")
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(match_operand:DI 1 "general_operand" "")])]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (DImode, ACC_A);
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emit_move_insn (acc_a, operands[1]);
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emit_insn (gen_negdi2_insn ());
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emit_move_insn (operands[0], acc_a);
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DONE;
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})
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(define_insn "negdi2_insn"
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[(set (reg:DI ACC_A)
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(neg:DI (reg:DI ACC_A)))]
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"avr_have_dimode"
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"%~call __negdi2"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "clobber")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Comparison
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "conditional_jump"
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[(set (pc)
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(if_then_else
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(match_operator 0 "ordered_comparison_operator" [(cc0)
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(const_int 0)])
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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"avr_have_dimode")
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(define_expand "cbranchdi4"
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[(parallel [(match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "nonmemory_operand" "")
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(match_operator 0 "ordered_comparison_operator" [(cc0)
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(const_int 0)])
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(label_ref (match_operand 3 "" ""))])]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (DImode, ACC_A);
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emit_move_insn (acc_a, operands[1]);
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if (s8_operand (operands[2], VOIDmode))
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{
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emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
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emit_insn (gen_compare_const8_di2 ());
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}
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else if (CONST_INT_P (operands[2])
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|| CONST_DOUBLE_P (operands[2]))
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{
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emit_insn (gen_compare_const_di2 (operands[2]));
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}
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else
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{
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emit_move_insn (gen_rtx_REG (DImode, ACC_B), operands[2]);
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emit_insn (gen_compare_di2 ());
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}
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emit_jump_insn (gen_conditional_jump (operands[0], operands[3]));
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DONE;
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})
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(define_insn "compare_di2"
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[(set (cc0)
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(compare (reg:DI ACC_A)
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(reg:DI ACC_B)))]
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"avr_have_dimode"
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"%~call __cmpdi2"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "compare")])
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(define_insn "compare_const8_di2"
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[(set (cc0)
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(compare (reg:DI ACC_A)
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(sign_extend:DI (reg:QI REG_X))))]
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"avr_have_dimode"
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"%~call __cmpdi2_s8"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "compare")])
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(define_insn "compare_const_di2"
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[(set (cc0)
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(compare (reg:DI ACC_A)
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(match_operand:DI 0 "const_double_operand" "n")))
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(clobber (match_scratch:QI 1 "=&d"))]
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"avr_have_dimode
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&& !s8_operand (operands[0], VOIDmode)"
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{
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return avr_out_compare64 (insn, operands, NULL);
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}
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[(set_attr "adjust_len" "compare64")
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(set_attr "cc" "compare")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Shifts and Rotate
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_code_iterator di_shifts
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[ashift ashiftrt lshiftrt rotate])
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;; Shift functions from libgcc are called without defining these insns,
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;; but with them we can describe their reduced register footprint.
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;; "ashldi3"
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;; "ashrdi3"
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;; "lshrdi3"
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;; "rotldi3"
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(define_expand "<code_stdname>di3"
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[(parallel [(match_operand:DI 0 "general_operand" "")
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(di_shifts:DI (match_operand:DI 1 "general_operand" "")
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(match_operand:QI 2 "general_operand" ""))])]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (DImode, ACC_A);
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emit_move_insn (acc_a, operands[1]);
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emit_move_insn (gen_rtx_REG (QImode, 16), operands[2]);
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emit_insn (gen_<code_stdname>di3_insn ());
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emit_move_insn (operands[0], acc_a);
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DONE;
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})
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(define_insn "<code_stdname>di3_insn"
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[(set (reg:DI ACC_A)
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(di_shifts:DI (reg:DI ACC_A)
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(reg:QI 16)))]
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"avr_have_dimode"
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"%~call __<code_stdname>di3"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "clobber")])
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@ -56,6 +56,7 @@ extern const char *avr_out_tstsi (rtx, rtx*, int*);
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extern const char *avr_out_tsthi (rtx, rtx*, int*);
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extern const char *avr_out_tstpsi (rtx, rtx*, int*);
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extern const char *avr_out_compare (rtx, rtx*, int*);
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extern const char *avr_out_compare64 (rtx, rtx*, int*);
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extern const char *ret_cond_branch (rtx x, int len, int reverse);
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extern const char *avr_out_movpsi (rtx, rtx*, int*);
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@ -89,6 +90,7 @@ extern const char *avr_out_sbxx_branch (rtx insn, rtx operands[]);
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extern const char* avr_out_bitop (rtx, rtx*, int*);
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extern const char* avr_out_plus (rtx*, int*, int*);
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extern const char* avr_out_plus_noclobber (rtx*, int*, int*);
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extern const char* avr_out_plus64 (rtx, int*);
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extern const char* avr_out_addto_sp (rtx*, int*);
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extern const char* avr_out_xload (rtx, rtx*, int*);
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extern const char* avr_out_movmem (rtx, rtx*, int*);
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@ -128,6 +130,8 @@ extern bool avr_xload_libgcc_p (enum machine_mode);
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extern void asm_output_float (FILE *file, REAL_VALUE_TYPE n);
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#endif
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extern bool avr_have_dimode;
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/* From avr-log.c */
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#define avr_edump (avr_log_set_caller_e (__FUNCTION__))
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@ -164,6 +164,9 @@ static GTY(()) section *progmem_swtable_section;
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or to address space __pgm*. */
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static GTY(()) section *progmem_section[6];
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/* Condition for insns/expanders from avr-dimode.md. */
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bool avr_have_dimode = true;
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/* To track if code will use .bss and/or .data. */
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bool avr_need_clear_bss_p = false;
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bool avr_need_copy_data_p = false;
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@ -4091,14 +4094,17 @@ avr_out_compare (rtx insn, rtx *xop, int *plen)
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/* Value (0..0xff) held in clobber register xop[2] or -1 if unknown. */
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int clobber_val = -1;
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gcc_assert (REG_P (xreg)
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&& CONST_INT_P (xval));
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gcc_assert (REG_P (xreg));
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gcc_assert ((CONST_INT_P (xval) && n_bytes <= 4)
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|| (const_double_operand (xval, VOIDmode) && n_bytes == 8));
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if (plen)
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*plen = 0;
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/* Comparisons == +/-1 and != +/-1 can be done similar to camparing
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against 0 by ORing the bytes. This is one instruction shorter. */
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against 0 by ORing the bytes. This is one instruction shorter.
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Notice that DImode comparisons are always against reg:DI 18
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and therefore don't use this. */
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if (!test_hard_reg_class (LD_REGS, xreg)
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&& compare_eq_p (insn)
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@ -4216,6 +4222,20 @@ avr_out_compare (rtx insn, rtx *xop, int *plen)
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}
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/* Prepare operands of compare_const_di2 to be used with avr_out_compare. */
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const char*
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avr_out_compare64 (rtx insn, rtx *op, int *plen)
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{
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rtx xop[3];
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xop[0] = gen_rtx_REG (DImode, 18);
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xop[1] = op[0];
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xop[2] = op[1];
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return avr_out_compare (insn, xop, plen);
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}
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/* Output test instruction for HImode. */
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const char*
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@ -5855,7 +5875,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc)
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*pcc = (MINUS == code) ? CC_SET_CZN : CC_CLOBBER;
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if (MINUS == code)
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xval = gen_int_mode (-UINTVAL (xval), mode);
|
||||
xval = simplify_unary_operation (NEG, mode, xval, mode);
|
||||
|
||||
op[2] = xop[3];
|
||||
|
||||
|
|
@ -6030,6 +6050,25 @@ avr_out_plus_noclobber (rtx *xop, int *plen, int *pcc)
|
|||
return avr_out_plus (op, plen, pcc);
|
||||
}
|
||||
|
||||
|
||||
/* Prepare operands of adddi3_const_insn to be used with avr_out_plus_1. */
|
||||
|
||||
const char*
|
||||
avr_out_plus64 (rtx addend, int *plen)
|
||||
{
|
||||
int cc_dummy;
|
||||
rtx op[4];
|
||||
|
||||
op[0] = gen_rtx_REG (DImode, 18);
|
||||
op[1] = op[0];
|
||||
op[2] = addend;
|
||||
op[3] = NULL_RTX;
|
||||
|
||||
avr_out_plus_1 (op, plen, MINUS, &cc_dummy);
|
||||
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Output bit operation (IOR, AND, XOR) with register XOP[0] and compile
|
||||
time constant XOP[2]:
|
||||
|
||||
|
|
@ -6415,6 +6454,7 @@ adjust_insn_length (rtx insn, int len)
|
|||
case ADJUST_LEN_OUT_BITOP: avr_out_bitop (insn, op, &len); break;
|
||||
|
||||
case ADJUST_LEN_OUT_PLUS: avr_out_plus (op, &len, NULL); break;
|
||||
case ADJUST_LEN_PLUS64: avr_out_plus64 (op[0], &len); break;
|
||||
case ADJUST_LEN_OUT_PLUS_NOCLOBBER:
|
||||
avr_out_plus_noclobber (op, &len, NULL); break;
|
||||
|
||||
|
|
@ -6431,6 +6471,7 @@ adjust_insn_length (rtx insn, int len)
|
|||
case ADJUST_LEN_TSTPSI: avr_out_tstpsi (insn, op, &len); break;
|
||||
case ADJUST_LEN_TSTSI: avr_out_tstsi (insn, op, &len); break;
|
||||
case ADJUST_LEN_COMPARE: avr_out_compare (insn, op, &len); break;
|
||||
case ADJUST_LEN_COMPARE64: avr_out_compare64 (insn, op, &len); break;
|
||||
|
||||
case ADJUST_LEN_LSHRQI: lshrqi3_out (insn, op, &len); break;
|
||||
case ADJUST_LEN_LSHRHI: lshrhi3_out (insn, op, &len); break;
|
||||
|
|
@ -8389,7 +8430,9 @@ avr_compare_pattern (rtx insn)
|
|||
if (pattern
|
||||
&& NONJUMP_INSN_P (insn)
|
||||
&& SET_DEST (pattern) == cc0_rtx
|
||||
&& GET_CODE (SET_SRC (pattern)) == COMPARE)
|
||||
&& GET_CODE (SET_SRC (pattern)) == COMPARE
|
||||
&& DImode != GET_MODE (XEXP (SET_SRC (pattern), 0))
|
||||
&& DImode != GET_MODE (XEXP (SET_SRC (pattern), 1)))
|
||||
{
|
||||
return pattern;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -142,8 +142,8 @@
|
|||
;; Otherwise do special processing depending on the attribute.
|
||||
|
||||
(define_attr "adjust_len"
|
||||
"out_bitop, out_plus, out_plus_noclobber, addto_sp,
|
||||
tsthi, tstpsi, tstsi, compare, call,
|
||||
"out_bitop, out_plus, out_plus_noclobber, plus64, addto_sp,
|
||||
tsthi, tstpsi, tstsi, compare, compare64, call,
|
||||
mov8, mov16, mov24, mov32, reload_in16, reload_in24, reload_in32,
|
||||
xload, movmem,
|
||||
ashlqi, ashrqi, lshrqi,
|
||||
|
|
@ -218,7 +218,6 @@
|
|||
(define_mode_iterator QIHI2 [(QI "") (HI "")])
|
||||
(define_mode_iterator QISI [(QI "") (HI "") (PSI "") (SI "")])
|
||||
(define_mode_iterator QIDI [(QI "") (HI "") (PSI "") (SI "") (DI "")])
|
||||
(define_mode_iterator HIDI [(HI "") (PSI "") (SI "") (DI "")])
|
||||
(define_mode_iterator HISI [(HI "") (PSI "") (SI "")])
|
||||
|
||||
;; All supported move-modes
|
||||
|
|
@ -247,6 +246,12 @@
|
|||
[(zero_extend "r")
|
||||
(sign_extend "d")])
|
||||
|
||||
;; Map RTX code to its standard insn name
|
||||
(define_code_attr code_stdname
|
||||
[(ashift "ashl")
|
||||
(ashiftrt "ashr")
|
||||
(lshiftrt "lshr")
|
||||
(rotate "rotl")])
|
||||
|
||||
;;========================================================================
|
||||
;; The following is used by nonlocal_goto and setjmp.
|
||||
|
|
@ -3094,23 +3099,21 @@
|
|||
[(set_attr "length" "2,4,4,1,3,5,3,0")
|
||||
(set_attr "cc" "set_n,set_n,clobber,none,set_n,set_n,clobber,none")])
|
||||
|
||||
;; Split all rotates of HI,SI and DImode registers where rotation is by
|
||||
;; Split all rotates of HI,SI and PSImode registers where rotation is by
|
||||
;; a whole number of bytes. The split creates the appropriate moves and
|
||||
;; considers all overlap situations. DImode is split before reload.
|
||||
;; considers all overlap situations.
|
||||
|
||||
;; HImode does not need scratch. Use attribute for this constraint.
|
||||
;; Use QI scratch for DI mode as this is often split into byte sized operands.
|
||||
|
||||
(define_mode_attr rotx [(DI "&r,&r,X") (SI "&r,&r,X") (PSI "&r,&r,X") (HI "X,X,X")])
|
||||
(define_mode_attr rotsmode [(DI "QI") (SI "HI") (PSI "QI") (HI "QI")])
|
||||
(define_mode_attr rotx [(SI "&r,&r,X") (PSI "&r,&r,X") (HI "X,X,X")])
|
||||
(define_mode_attr rotsmode [(SI "HI") (PSI "QI") (HI "QI")])
|
||||
|
||||
;; "rotlhi3"
|
||||
;; "rotlpsi3"
|
||||
;; "rotlsi3"
|
||||
;; "rotldi3"
|
||||
(define_expand "rotl<mode>3"
|
||||
[(parallel [(set (match_operand:HIDI 0 "register_operand" "")
|
||||
(rotate:HIDI (match_operand:HIDI 1 "register_operand" "")
|
||||
[(parallel [(set (match_operand:HISI 0 "register_operand" "")
|
||||
(rotate:HISI (match_operand:HISI 1 "register_operand" "")
|
||||
(match_operand:VOID 2 "const_int_operand" "")))
|
||||
(clobber (match_dup 3))])]
|
||||
""
|
||||
|
|
@ -3129,9 +3132,8 @@
|
|||
else
|
||||
operands[3] = gen_rtx_SCRATCH (QImode);
|
||||
}
|
||||
else if (<MODE>mode != DImode
|
||||
&& (offset == 1
|
||||
|| offset == GET_MODE_BITSIZE (<MODE>mode) -1))
|
||||
else if (offset == 1
|
||||
|| offset == GET_MODE_BITSIZE (<MODE>mode) -1)
|
||||
{
|
||||
/*; Support rotate left/right by 1 */
|
||||
|
||||
|
|
@ -3207,18 +3209,17 @@
|
|||
|
||||
;; "*rotwhi"
|
||||
;; "*rotwsi"
|
||||
;; "*rotwdi"
|
||||
(define_insn_and_split "*rotw<mode>"
|
||||
[(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
|
||||
(rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
|
||||
(match_operand 2 "const_int_operand" "n,n,n")))
|
||||
[(set (match_operand:HISI 0 "register_operand" "=r,r,#&r")
|
||||
(rotate:HISI (match_operand:HISI 1 "register_operand" "0,r,r")
|
||||
(match_operand 2 "const_int_operand" "n,n,n")))
|
||||
(clobber (match_scratch:<rotsmode> 3 "=<rotx>"))]
|
||||
"AVR_HAVE_MOVW
|
||||
&& CONST_INT_P (operands[2])
|
||||
&& GET_MODE_SIZE (<MODE>mode) % 2 == 0
|
||||
&& 0 == INTVAL (operands[2]) % 16"
|
||||
"#"
|
||||
"&& (reload_completed || <MODE>mode == DImode)"
|
||||
"&& reload_completed"
|
||||
[(const_int 0)]
|
||||
{
|
||||
avr_rotate_bytes (operands);
|
||||
|
|
@ -3231,11 +3232,10 @@
|
|||
;; "*rotbhi"
|
||||
;; "*rotbpsi"
|
||||
;; "*rotbsi"
|
||||
;; "*rotbdi"
|
||||
(define_insn_and_split "*rotb<mode>"
|
||||
[(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
|
||||
(rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
|
||||
(match_operand 2 "const_int_operand" "n,n,n")))
|
||||
[(set (match_operand:HISI 0 "register_operand" "=r,r,#&r")
|
||||
(rotate:HISI (match_operand:HISI 1 "register_operand" "0,r,r")
|
||||
(match_operand 2 "const_int_operand" "n,n,n")))
|
||||
(clobber (match_scratch:QI 3 "=<rotx>"))]
|
||||
"CONST_INT_P (operands[2])
|
||||
&& (8 == INTVAL (operands[2]) % 16
|
||||
|
|
@ -3243,7 +3243,7 @@
|
|||
|| GET_MODE_SIZE (<MODE>mode) % 2 != 0)
|
||||
&& 0 == INTVAL (operands[2]) % 16))"
|
||||
"#"
|
||||
"&& (reload_completed || <MODE>mode == DImode)"
|
||||
"&& reload_completed"
|
||||
[(const_int 0)]
|
||||
{
|
||||
avr_rotate_bytes (operands);
|
||||
|
|
@ -5949,6 +5949,8 @@
|
|||
operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
|
||||
})
|
||||
|
||||
(include "avr-dimode.md")
|
||||
|
||||
(define_insn_and_split "*extzv.qihi2"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
(zero_extend:HI
|
||||
|
|
|
|||
|
|
@ -1,3 +1,11 @@
|
|||
2012-01-02 Georg-Johann Lay <avr@gjlay.de>
|
||||
|
||||
Implement light-weight DImode support.
|
||||
* config/avr/t-avr (LIB1ASMFUNCS): Add _adddi3, _adddi3_s8,
|
||||
_subdi3, _cmpdi2, _cmpdi2_s8, _rotldi3.
|
||||
* config/avr/lib1funcs.S (__adddi3, __adddi3_s8, __subdi3,
|
||||
__cmpdi2, __cmpdi2_s8, __rotldi3): New functions.
|
||||
|
||||
2011-12-30 Nathan Sidwell <nathan@acm.org>
|
||||
|
||||
* libgcov.c (gcov_crc32): Remove global var.
|
||||
|
|
|
|||
|
|
@ -1558,6 +1558,71 @@ ENDF __divdi3_moddi3
|
|||
|
||||
#endif /* L_divdi3 */
|
||||
|
||||
.section .text.libgcc, "ax", @progbits
|
||||
|
||||
#define TT __tmp_reg__
|
||||
|
||||
#if defined (L_adddi3)
|
||||
;; (set (reg:DI 18)
|
||||
;; (plus:DI (reg:DI 18)
|
||||
;; (reg:DI 10)))
|
||||
DEFUN __adddi3
|
||||
ADD A0,B0 $ adc A1,B1 $ adc A2,B2 $ adc A3,B3
|
||||
adc A4,B4 $ adc A5,B5 $ adc A6,B6 $ adc A7,B7
|
||||
ret
|
||||
ENDF __adddi3
|
||||
#endif /* L_adddi3 */
|
||||
|
||||
#if defined (L_adddi3_s8)
|
||||
;; (set (reg:DI 18)
|
||||
;; (plus:DI (reg:DI 18)
|
||||
;; (sign_extend:SI (reg:QI 26))))
|
||||
DEFUN __adddi3_s8
|
||||
clr TT
|
||||
sbrc r26, 7
|
||||
com TT
|
||||
ADD A0,r26 $ adc A1,TT $ adc A2,TT $ adc A3,TT
|
||||
adc A4,TT $ adc A5,TT $ adc A6,TT $ adc A7,TT
|
||||
ret
|
||||
ENDF __adddi3_s8
|
||||
#endif /* L_adddi3_s8 */
|
||||
|
||||
#if defined (L_subdi3)
|
||||
;; (set (reg:DI 18)
|
||||
;; (minus:DI (reg:DI 18)
|
||||
;; (reg:DI 10)))
|
||||
DEFUN __subdi3
|
||||
SUB A0,B0 $ sbc A1,B1 $ sbc A2,B2 $ sbc A3,B3
|
||||
sbc A4,B4 $ sbc A5,B5 $ sbc A6,B6 $ sbc A7,B7
|
||||
ret
|
||||
ENDF __subdi3
|
||||
#endif /* L_subdi3 */
|
||||
|
||||
#if defined (L_cmpdi2)
|
||||
;; (set (cc0)
|
||||
;; (compare (reg:DI 18)
|
||||
;; (reg:DI 10)))
|
||||
DEFUN __cmpdi2
|
||||
CP A0,B0 $ cpc A1,B1 $ cpc A2,B2 $ cpc A3,B3
|
||||
cpc A4,B4 $ cpc A5,B5 $ cpc A6,B6 $ cpc A7,B7
|
||||
ret
|
||||
ENDF __cmpdi2
|
||||
#endif /* L_cmpdi2 */
|
||||
|
||||
#if defined (L_cmpdi2_s8)
|
||||
;; (set (cc0)
|
||||
;; (compare (reg:DI 18)
|
||||
;; (sign_extend:SI (reg:QI 26))))
|
||||
DEFUN __cmpdi2_s8
|
||||
clr TT
|
||||
sbrc r26, 7
|
||||
com TT
|
||||
CP A0,r26 $ cpc A1,TT $ cpc A2,TT $ cpc A3,TT
|
||||
cpc A4,TT $ cpc A5,TT $ cpc A6,TT $ cpc A7,TT
|
||||
ret
|
||||
ENDF __cmpdi2_s8
|
||||
#endif /* L_cmpdi2_s8 */
|
||||
|
||||
#if defined (L_negdi2)
|
||||
DEFUN __negdi2
|
||||
|
||||
|
|
@ -1571,6 +1636,8 @@ DEFUN __negdi2
|
|||
ENDF __negdi2
|
||||
#endif /* L_negdi2 */
|
||||
|
||||
#undef TT
|
||||
|
||||
#undef C7
|
||||
#undef C6
|
||||
#undef C5
|
||||
|
|
@ -2470,6 +2537,29 @@ DEFUN __ashldi3
|
|||
ENDF __ashldi3
|
||||
#endif /* defined (L_ashldi3) */
|
||||
|
||||
#if defined (L_rotldi3)
|
||||
;; Shift left
|
||||
;; r25:r18 = rotl64 (r25:r18, r17:r16)
|
||||
DEFUN __rotldi3
|
||||
push r16
|
||||
andi r16, 63
|
||||
breq 2f
|
||||
1: lsl r18
|
||||
rol r19
|
||||
rol r20
|
||||
rol r21
|
||||
rol r22
|
||||
rol r23
|
||||
rol r24
|
||||
rol r25
|
||||
adc r18, __zero_reg__
|
||||
dec r16
|
||||
brne 1b
|
||||
2: pop r16
|
||||
ret
|
||||
ENDF __rotldi3
|
||||
#endif /* defined (L_rotldi3) */
|
||||
|
||||
|
||||
.section .text.libgcc.fmul, "ax", @progbits
|
||||
|
||||
|
|
|
|||
|
|
@ -49,9 +49,9 @@ LIB1ASMFUNCS = \
|
|||
_popcountqi2 \
|
||||
_bswapsi2 \
|
||||
_bswapdi2 \
|
||||
_ashldi3 \
|
||||
_ashrdi3 \
|
||||
_lshrdi3 \
|
||||
_ashldi3 _ashrdi3 _lshrdi3 _rotldi3 \
|
||||
_adddi3 _adddi3_s8 _subdi3 \
|
||||
_cmpdi2 _cmpdi2_s8 \
|
||||
_fmul _fmuls _fmulsu
|
||||
|
||||
LIB2FUNCS_EXCLUDE = \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue