rs6000: Vector string isolate instructions
Adds new instructions vstribr, vstrihr, vstribl, and vstrihl, with overloaded built-in support. [gcc] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/altivec.h (vec_strir): New #define. (vec_stril): Likewise. (vec_strir_p): Likewise. (vec_stril_p): Likewise. * config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant. (UNSPEC_VSTRIL): Likewise. (vstrir_<mode>): New expansion. (vstrir_code_<mode>): New insn. (vstrir_p_<mode>): New expansion. (vstrir_p_code_<mode>): New insn. (vstril_<mode>): New expansion. (vstril_code_<mode>): New insn. (vstril_p_<mode>): New expansion. (vstril_p_code_<mode>): New insn. * config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr): New built-in function. (__builtin_altivec_vstrihr): Likewise. (__builtin_altivec_vstribl): Likewise. (__builtin_altivec_vstrihl): Likewise. (__builtin_altivec_vstribr_p): Likewise. (__builtin_altivec_vstrihr_p): Likewise. (__builtin_altivec_vstribl_p): Likewise. (__builtin_altivec_vstrihl_p): Likewise. (__builtin_vec_strir): New overloaded built-in function. (__builtin_vec_stril): Likewise. (__builtin_vec_strir_p): Likewise. (__builtin_vec_stril_p): Likewise. * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Define overloaded forms of __builtin_vec_strir, __builtin_vec_stril, __builtin_vec_strir_p, and __builtin_vec_stril_p. * doc/extend.texi (PowerPC AltiVec Built-in Functions Available for a Future Architecture): Add description of vec_stril, vec_stril_p, vec_strir, and vec_strir_p built-in functions. [gcc] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/vec-stril-0.c: New. * gcc.target/powerpc/vec-stril-1.c: New. * gcc.target/powerpc/vec-stril-10.c: New. * gcc.target/powerpc/vec-stril-11.c: New. * gcc.target/powerpc/vec-stril-12.c: New. * gcc.target/powerpc/vec-stril-13.c: New. * gcc.target/powerpc/vec-stril-14.c: New. * gcc.target/powerpc/vec-stril-15.c: New. * gcc.target/powerpc/vec-stril-16.c: New. * gcc.target/powerpc/vec-stril-17.c: New. * gcc.target/powerpc/vec-stril-18.c: New. * gcc.target/powerpc/vec-stril-19.c: New. * gcc.target/powerpc/vec-stril-2.c: New. * gcc.target/powerpc/vec-stril-20.c: New. * gcc.target/powerpc/vec-stril-21.c: New. * gcc.target/powerpc/vec-stril-22.c: New. * gcc.target/powerpc/vec-stril-23.c: New. * gcc.target/powerpc/vec-stril-3.c: New. * gcc.target/powerpc/vec-stril-4.c: New. * gcc.target/powerpc/vec-stril-5.c: New. * gcc.target/powerpc/vec-stril-6.c: New. * gcc.target/powerpc/vec-stril-7.c: New. * gcc.target/powerpc/vec-stril-8.c: New. * gcc.target/powerpc/vec-stril-9.c: New. * gcc.target/powerpc/vec-stril_p-0.c: New. * gcc.target/powerpc/vec-stril_p-1.c: New. * gcc.target/powerpc/vec-stril_p-10.c: New. * gcc.target/powerpc/vec-stril_p-11.c: New. * gcc.target/powerpc/vec-stril_p-2.c: New. * gcc.target/powerpc/vec-stril_p-3.c: New. * gcc.target/powerpc/vec-stril_p-4.c: New. * gcc.target/powerpc/vec-stril_p-5.c: New. * gcc.target/powerpc/vec-stril_p-6.c: New. * gcc.target/powerpc/vec-stril_p-7.c: New. * gcc.target/powerpc/vec-stril_p-8.c: New. * gcc.target/powerpc/vec-stril_p-9.c: New. * gcc.target/powerpc/vec-strir-0.c: New. * gcc.target/powerpc/vec-strir-1.c: New. * gcc.target/powerpc/vec-strir-10.c: New. * gcc.target/powerpc/vec-strir-11.c: New. * gcc.target/powerpc/vec-strir-12.c: New. * gcc.target/powerpc/vec-strir-13.c: New. * gcc.target/powerpc/vec-strir-14.c: New. * gcc.target/powerpc/vec-strir-15.c: New. * gcc.target/powerpc/vec-strir-16.c: New. * gcc.target/powerpc/vec-strir-17.c: New. * gcc.target/powerpc/vec-strir-18.c: New. * gcc.target/powerpc/vec-strir-19.c: New. * gcc.target/powerpc/vec-strir-2.c: New. * gcc.target/powerpc/vec-strir-20.c: New. * gcc.target/powerpc/vec-strir-21.c: New. * gcc.target/powerpc/vec-strir-22.c: New. * gcc.target/powerpc/vec-strir-23.c: New. * gcc.target/powerpc/vec-strir-3.c: New. * gcc.target/powerpc/vec-strir-4.c: New. * gcc.target/powerpc/vec-strir-5.c: New. * gcc.target/powerpc/vec-strir-6.c: New. * gcc.target/powerpc/vec-strir-7.c: New. * gcc.target/powerpc/vec-strir-8.c: New. * gcc.target/powerpc/vec-strir-9.c: New. * gcc.target/powerpc/vec-strir_p-0.c: New. * gcc.target/powerpc/vec-strir_p-1.c: New. * gcc.target/powerpc/vec-strir_p-10.c: New. * gcc.target/powerpc/vec-strir_p-11.c: New. * gcc.target/powerpc/vec-strir_p-2.c: New. * gcc.target/powerpc/vec-strir_p-3.c: New. * gcc.target/powerpc/vec-strir_p-4.c: New. * gcc.target/powerpc/vec-strir_p-5.c: New. * gcc.target/powerpc/vec-strir_p-6.c: New. * gcc.target/powerpc/vec-strir_p-7.c: New. * gcc.target/powerpc/vec-strir_p-8.c: New. * gcc.target/powerpc/vec-strir_p-9.c: New.
This commit is contained in:
Kelvin Nilsen
Bill Schmidt
parent
840ac85ced
commit
89ce32902a
79 changed files with 2956 additions and 0 deletions
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@ -1,3 +1,40 @@
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2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
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* config/rs6000/altivec.h (vec_strir): New #define.
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(vec_stril): Likewise.
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(vec_strir_p): Likewise.
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(vec_stril_p): Likewise.
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* config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
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(UNSPEC_VSTRIL): Likewise.
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(vstrir_<mode>): New expansion.
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(vstrir_code_<mode>): New insn.
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(vstrir_p_<mode>): New expansion.
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(vstrir_p_code_<mode>): New insn.
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(vstril_<mode>): New expansion.
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(vstril_code_<mode>): New insn.
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(vstril_p_<mode>): New expansion.
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(vstril_p_code_<mode>): New insn.
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* config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
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New built-in function.
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(__builtin_altivec_vstrihr): Likewise.
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(__builtin_altivec_vstribl): Likewise.
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(__builtin_altivec_vstrihl): Likewise.
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(__builtin_altivec_vstribr_p): Likewise.
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(__builtin_altivec_vstrihr_p): Likewise.
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(__builtin_altivec_vstribl_p): Likewise.
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(__builtin_altivec_vstrihl_p): Likewise.
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(__builtin_vec_strir): New overloaded built-in function.
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(__builtin_vec_stril): Likewise.
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(__builtin_vec_strir_p): Likewise.
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(__builtin_vec_stril_p): Likewise.
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* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
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Define overloaded forms of __builtin_vec_strir,
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__builtin_vec_stril, __builtin_vec_strir_p, and
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__builtin_vec_stril_p.
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* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
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for a Future Architecture): Add description of vec_stril,
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vec_stril_p, vec_strir, and vec_strir_p built-in functions.
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2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
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* config/rs6000/altivec.h (vec_ternarylogic): New #define.
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@ -700,6 +700,12 @@ __altivec_scalar_pred(vec_any_nle,
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#define vec_clrl(a, b) __builtin_vec_clrl (a, b)
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#define vec_clrr(a, b) __builtin_vec_clrr (a, b)
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#define vec_ternarylogic(a, b, c, d) __builtin_vec_xxeval (a, b, c, d)
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#define vec_strir(a) __builtin_vec_strir (a)
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#define vec_stril(a) __builtin_vec_stril (a)
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#define vec_strir_p(a) __builtin_vec_strir_p (a)
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#define vec_stril_p(a) __builtin_vec_stril_p (a)
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#endif
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#endif /* _ALTIVEC_H */
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@ -169,6 +169,8 @@
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UNSPEC_VCLRLB
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UNSPEC_VCLRRB
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UNSPEC_XXEVAL
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UNSPEC_VSTRIR
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UNSPEC_VSTRIL
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])
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(define_c_enum "unspecv"
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@ -781,6 +783,109 @@
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DONE;
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})
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(define_expand "vstrir_<mode>"
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[(set (match_operand:VIshort 0 "altivec_register_operand")
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(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
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UNSPEC_VSTRIR))]
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"TARGET_FUTURE"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_vstrir_code_<mode> (operands[0], operands[1]));
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else
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emit_insn (gen_vstril_code_<mode> (operands[0], operands[1]));
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DONE;
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})
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(define_insn "vstrir_code_<mode>"
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[(set (match_operand:VIshort 0 "altivec_register_operand" "=v")
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(unspec:VIshort
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[(match_operand:VIshort 1 "altivec_register_operand" "v")]
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UNSPEC_VSTRIR))]
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"TARGET_FUTURE"
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"vstri<wd>r %0,%1"
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[(set_attr "type" "vecsimple")])
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;; This expands into same code as vstrir_<mode> followed by condition logic
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;; so that a single vstribr. or vstrihr. or vstribl. or vstrihl. instruction
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;; can, for example, satisfy the needs of a vec_strir () function paired
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;; with a vec_strir_p () function if both take the same incoming arguments.
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(define_expand "vstrir_p_<mode>"
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[(match_operand:SI 0 "gpc_reg_operand")
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(match_operand:VIshort 1 "altivec_register_operand")]
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"TARGET_FUTURE"
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{
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rtx scratch = gen_reg_rtx (<MODE>mode);
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_vstrir_p_code_<mode> (scratch, operands[1]));
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else
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emit_insn (gen_vstril_p_code_<mode> (scratch, operands[1]));
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emit_insn (gen_cr6_test_for_zero (operands[0]));
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DONE;
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})
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(define_insn "vstrir_p_code_<mode>"
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[(set (match_operand:VIshort 0 "altivec_register_operand" "=v")
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(unspec:VIshort
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[(match_operand:VIshort 1 "altivec_register_operand" "v")]
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UNSPEC_VSTRIR))
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(set (reg:CC CR6_REGNO)
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(unspec:CC [(match_dup 1)]
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UNSPEC_VSTRIR))]
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"TARGET_FUTURE"
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"vstri<wd>r. %0,%1"
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[(set_attr "type" "vecsimple")])
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(define_expand "vstril_<mode>"
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[(set (match_operand:VIshort 0 "altivec_register_operand")
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(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
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UNSPEC_VSTRIR))]
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"TARGET_FUTURE"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_vstril_code_<mode> (operands[0], operands[1]));
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else
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emit_insn (gen_vstrir_code_<mode> (operands[0], operands[1]));
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DONE;
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})
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(define_insn "vstril_code_<mode>"
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[(set (match_operand:VIshort 0 "altivec_register_operand" "=v")
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(unspec:VIshort
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[(match_operand:VIshort 1 "altivec_register_operand" "v")]
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UNSPEC_VSTRIL))]
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"TARGET_FUTURE"
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"vstri<wd>l %0,%1"
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[(set_attr "type" "vecsimple")])
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;; This expands into same code as vstril_<mode> followed by condition logic
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;; so that a single vstribr. or vstrihr. or vstribl. or vstrihl. instruction
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;; can, for example, satisfy the needs of a vec_stril () function paired
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;; with a vec_stril_p () function if both take the same incoming arguments.
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(define_expand "vstril_p_<mode>"
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[(match_operand:SI 0 "gpc_reg_operand")
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(match_operand:VIshort 1 "altivec_register_operand")]
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"TARGET_FUTURE"
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{
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rtx scratch = gen_reg_rtx (<MODE>mode);
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_vstril_p_code_<mode> (scratch, operands[1]));
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else
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emit_insn (gen_vstrir_p_code_<mode> (scratch, operands[1]));
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emit_insn (gen_cr6_test_for_zero (operands[0]));
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DONE;
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})
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(define_insn "vstril_p_code_<mode>"
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[(set (match_operand:VIshort 0 "altivec_register_operand" "=v")
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(unspec:VIshort
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[(match_operand:VIshort 1 "altivec_register_operand" "v")]
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UNSPEC_VSTRIL))
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(set (reg:CC CR6_REGNO)
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(unspec:CC [(match_dup 1)]
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UNSPEC_VSTRIR))]
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"TARGET_FUTURE"
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"vstri<wd>l. %0,%1"
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[(set_attr "type" "vecsimple")])
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;; Fused multiply subtract
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(define_insn "*altivec_vnmsubfp"
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@ -2612,12 +2612,27 @@ BU_FUTURE_V_2 (VPEXTD, "vpextd", CONST, vpextd)
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BU_FUTURE_V_2 (VGNB, "vgnb", CONST, vgnb)
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BU_FUTURE_V_4 (XXEVAL, "xxeval", CONST, xxeval)
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BU_FUTURE_V_1 (VSTRIBR, "vstribr", CONST, vstrir_v16qi)
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BU_FUTURE_V_1 (VSTRIHR, "vstrihr", CONST, vstrir_v8hi)
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BU_FUTURE_V_1 (VSTRIBL, "vstribl", CONST, vstril_v16qi)
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BU_FUTURE_V_1 (VSTRIHL, "vstrihl", CONST, vstril_v8hi)
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BU_FUTURE_V_1 (VSTRIBR_P, "vstribr_p", CONST, vstrir_p_v16qi)
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BU_FUTURE_V_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi)
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BU_FUTURE_V_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi)
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BU_FUTURE_V_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi)
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/* Future architecture overloaded vector built-ins. */
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BU_FUTURE_OVERLOAD_2 (CLRL, "clrl")
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BU_FUTURE_OVERLOAD_2 (CLRR, "clrr")
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BU_FUTURE_OVERLOAD_2 (GNB, "gnb")
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BU_FUTURE_OVERLOAD_4 (XXEVAL, "xxeval")
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BU_FUTURE_OVERLOAD_1 (VSTRIR, "strir")
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BU_FUTURE_OVERLOAD_1 (VSTRIL, "stril")
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BU_FUTURE_OVERLOAD_1 (VSTRIR_P, "strir_p")
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BU_FUTURE_OVERLOAD_1 (VSTRIL_P, "stril_p")
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/* 1 argument crypto functions. */
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BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox_v2di)
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@ -5551,6 +5551,46 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
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{ FUTURE_BUILTIN_VEC_VSTRIL, FUTURE_BUILTIN_VSTRIBL,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIL, FUTURE_BUILTIN_VSTRIBL,
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIL, FUTURE_BUILTIN_VSTRIHL,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIL, FUTURE_BUILTIN_VSTRIHL,
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RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIL_P, FUTURE_BUILTIN_VSTRIBL_P,
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RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIL_P, FUTURE_BUILTIN_VSTRIBL_P,
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RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIL_P, FUTURE_BUILTIN_VSTRIHL_P,
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RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIL_P, FUTURE_BUILTIN_VSTRIHL_P,
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RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIR, FUTURE_BUILTIN_VSTRIBR,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIR, FUTURE_BUILTIN_VSTRIBR,
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIR, FUTURE_BUILTIN_VSTRIHR,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIR, FUTURE_BUILTIN_VSTRIHR,
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RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIR_P, FUTURE_BUILTIN_VSTRIBR_P,
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RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIR_P, FUTURE_BUILTIN_VSTRIBR_P,
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RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIR_P, FUTURE_BUILTIN_VSTRIHR_P,
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RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
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{ FUTURE_BUILTIN_VEC_VSTRIR_P, FUTURE_BUILTIN_VSTRIHR_P,
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RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
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{ RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
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};
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@ -20833,6 +20833,62 @@ Perform a vector parallel bit extract operation, as if implemented by
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the Future @code{vpextd} instruction.
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@findex vec_pext
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||||
|
||||
@smallexample
|
||||
@exdent vector unsigned char vec_stril (vector unsigned char)
|
||||
@exdent vector signed char vec_stril (vector signed char)
|
||||
@exdent vector unsigned short vec_stril (vector unsigned short)
|
||||
@exdent vector signed short vec_stril (vector signed short)
|
||||
@end smallexample
|
||||
Isolate the left-most non-zero elements of the incoming vector argument,
|
||||
replacing all elements to the right of the left-most zero element
|
||||
found within the argument with zero. The typical implementation uses
|
||||
the @code{vstribl} or @code{vstrihl} instruction on big-endian targets
|
||||
and uses the @code{vstribr} or @code{vstrihr} instruction on
|
||||
little-endian targets.
|
||||
@findex vec_stril
|
||||
|
||||
@smallexample
|
||||
@exdent int vec_stril_p (vector unsigned char)
|
||||
@exdent int vec_stril_p (vector signed char)
|
||||
@exdent int short vec_stril_p (vector unsigned short)
|
||||
@exdent int vec_stril_p (vector signed short)
|
||||
@end smallexample
|
||||
Return a non-zero value if and only if the argument contains a zero
|
||||
element. The typical implementation uses
|
||||
the @code{vstribl.} or @code{vstrihl.} instruction on big-endian targets
|
||||
and uses the @code{vstribr.} or @code{vstrihr.} instruction on
|
||||
little-endian targets. Choose this built-in to check for presence of
|
||||
zero element if the same argument is also passed to @code{vec_stril}.
|
||||
@findex vec_stril_p
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned char vec_strir (vector unsigned char)
|
||||
@exdent vector signed char vec_strir (vector signed char)
|
||||
@exdent vector unsigned short vec_strir (vector unsigned short)
|
||||
@exdent vector signed short vec_strir (vector signed short)
|
||||
@end smallexample
|
||||
Isolate the right-most non-zero elements of the incoming vector argument,
|
||||
replacing all elements to the left of the right-most zero element
|
||||
found within the argument with zero. The typical implementation uses
|
||||
the @code{vstribr} or @code{vstrihr} instruction on big-endian targets
|
||||
and uses the @code{vstribl} or @code{vstrihl} instruction on
|
||||
little-endian targets.
|
||||
@findex vec_strir
|
||||
|
||||
@smallexample
|
||||
@exdent int vec_strir_p (vector unsigned char)
|
||||
@exdent int vec_strir_p (vector signed char)
|
||||
@exdent int short vec_strir_p (vector unsigned short)
|
||||
@exdent int vec_strir_p (vector signed short)
|
||||
@end smallexample
|
||||
Return a non-zero value if and only if the argument contains a zero
|
||||
element. The typical implementation uses
|
||||
the @code{vstribr.} or @code{vstrihr.} instruction on big-endian targets
|
||||
and uses the @code{vstribl.} or @code{vstrihl.} instruction on
|
||||
little-endian targets. Choose this built-in to check for presence of
|
||||
zero element if the same argument is also passed to @code{vec_strir}.
|
||||
@findex vec_strir_p
|
||||
|
||||
@node PowerPC Hardware Transactional Memory Built-in Functions
|
||||
@subsection PowerPC Hardware Transactional Memory Built-in Functions
|
||||
GCC provides two interfaces for accessing the Hardware Transactional
|
||||
|
|
|
|||
|
|
@ -1,3 +1,78 @@
|
|||
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
|
||||
|
||||
* gcc.target/powerpc/vec-stril-0.c: New.
|
||||
* gcc.target/powerpc/vec-stril-1.c: New.
|
||||
* gcc.target/powerpc/vec-stril-10.c: New.
|
||||
* gcc.target/powerpc/vec-stril-11.c: New.
|
||||
* gcc.target/powerpc/vec-stril-12.c: New.
|
||||
* gcc.target/powerpc/vec-stril-13.c: New.
|
||||
* gcc.target/powerpc/vec-stril-14.c: New.
|
||||
* gcc.target/powerpc/vec-stril-15.c: New.
|
||||
* gcc.target/powerpc/vec-stril-16.c: New.
|
||||
* gcc.target/powerpc/vec-stril-17.c: New.
|
||||
* gcc.target/powerpc/vec-stril-18.c: New.
|
||||
* gcc.target/powerpc/vec-stril-19.c: New.
|
||||
* gcc.target/powerpc/vec-stril-2.c: New.
|
||||
* gcc.target/powerpc/vec-stril-20.c: New.
|
||||
* gcc.target/powerpc/vec-stril-21.c: New.
|
||||
* gcc.target/powerpc/vec-stril-22.c: New.
|
||||
* gcc.target/powerpc/vec-stril-23.c: New.
|
||||
* gcc.target/powerpc/vec-stril-3.c: New.
|
||||
* gcc.target/powerpc/vec-stril-4.c: New.
|
||||
* gcc.target/powerpc/vec-stril-5.c: New.
|
||||
* gcc.target/powerpc/vec-stril-6.c: New.
|
||||
* gcc.target/powerpc/vec-stril-7.c: New.
|
||||
* gcc.target/powerpc/vec-stril-8.c: New.
|
||||
* gcc.target/powerpc/vec-stril-9.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-0.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-1.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-10.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-11.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-2.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-3.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-4.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-5.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-6.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-7.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-8.c: New.
|
||||
* gcc.target/powerpc/vec-stril_p-9.c: New.
|
||||
* gcc.target/powerpc/vec-strir-0.c: New.
|
||||
* gcc.target/powerpc/vec-strir-1.c: New.
|
||||
* gcc.target/powerpc/vec-strir-10.c: New.
|
||||
* gcc.target/powerpc/vec-strir-11.c: New.
|
||||
* gcc.target/powerpc/vec-strir-12.c: New.
|
||||
* gcc.target/powerpc/vec-strir-13.c: New.
|
||||
* gcc.target/powerpc/vec-strir-14.c: New.
|
||||
* gcc.target/powerpc/vec-strir-15.c: New.
|
||||
* gcc.target/powerpc/vec-strir-16.c: New.
|
||||
* gcc.target/powerpc/vec-strir-17.c: New.
|
||||
* gcc.target/powerpc/vec-strir-18.c: New.
|
||||
* gcc.target/powerpc/vec-strir-19.c: New.
|
||||
* gcc.target/powerpc/vec-strir-2.c: New.
|
||||
* gcc.target/powerpc/vec-strir-20.c: New.
|
||||
* gcc.target/powerpc/vec-strir-21.c: New.
|
||||
* gcc.target/powerpc/vec-strir-22.c: New.
|
||||
* gcc.target/powerpc/vec-strir-23.c: New.
|
||||
* gcc.target/powerpc/vec-strir-3.c: New.
|
||||
* gcc.target/powerpc/vec-strir-4.c: New.
|
||||
* gcc.target/powerpc/vec-strir-5.c: New.
|
||||
* gcc.target/powerpc/vec-strir-6.c: New.
|
||||
* gcc.target/powerpc/vec-strir-7.c: New.
|
||||
* gcc.target/powerpc/vec-strir-8.c: New.
|
||||
* gcc.target/powerpc/vec-strir-9.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-0.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-1.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-10.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-11.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-2.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-3.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-4.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-5.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-6.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-7.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-8.c: New.
|
||||
* gcc.target/powerpc/vec-strir_p-9.c: New.
|
||||
|
||||
2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
|
||||
|
||||
* gcc.target/powerpc/vec-ternarylogic-0.c: New.
|
||||
|
|
|
|||
21
gcc/testsuite/gcc.target/powerpc/vec-stril-0.c
Normal file
21
gcc/testsuite/gcc.target/powerpc/vec-stril-0.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of unsigned char. */
|
||||
vector unsigned char
|
||||
silj (vector unsigned char arg)
|
||||
{
|
||||
return vec_stril (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { le } } } } */
|
||||
52
gcc/testsuite/gcc.target/powerpc/vec-stril-1.c
Normal file
52
gcc/testsuite/gcc.target/powerpc/vec-stril-1.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of unsigned char. */
|
||||
vector unsigned char
|
||||
silj (vector unsigned char arg)
|
||||
{
|
||||
return vec_stril (arg);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char input1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char expected1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char input2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char expected2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 00, 0x0 };
|
||||
vector unsigned char input3 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char expected3 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
|
||||
vector unsigned char input4 =
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char expected4 =
|
||||
{ 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
|
||||
if (!vec_all_eq (silj (input1), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input2), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input3), expected3))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input4), expected4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
27
gcc/testsuite/gcc.target/powerpc/vec-stril-10.c
Normal file
27
gcc/testsuite/gcc.target/powerpc/vec-stril-10.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-stril-11.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector signed char
|
||||
doString(vector signed char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector signed char result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { be } }} } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { le } }} } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { le } } } } */
|
||||
29
gcc/testsuite/gcc.target/powerpc/vec-stril-11.c
Normal file
29
gcc/testsuite/gcc.target/powerpc/vec-stril-11.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector signed char
|
||||
doString(vector signed char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both and should
|
||||
convert tail recursion to iteration with two copies of the "loop
|
||||
body" when compiled with -O2 or -O3. */
|
||||
vector signed char result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that exactly two dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 2 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 2 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { le } } } } */
|
||||
|
||||
27
gcc/testsuite/gcc.target/powerpc/vec-stril-12.c
Normal file
27
gcc/testsuite/gcc.target/powerpc/vec-stril-12.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-stril-13.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector unsigned short
|
||||
doString(vector unsigned short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector unsigned short result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
28
gcc/testsuite/gcc.target/powerpc/vec-stril-13.c
Normal file
28
gcc/testsuite/gcc.target/powerpc/vec-stril-13.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector unsigned short
|
||||
doString(vector unsigned short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both and should
|
||||
convert tail recursion to iteration with two copies of the "loop
|
||||
body" when compiled with -O2 or -O3. */
|
||||
vector unsigned short result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that exactly two dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 2 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 2 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
27
gcc/testsuite/gcc.target/powerpc/vec-stril-14.c
Normal file
27
gcc/testsuite/gcc.target/powerpc/vec-stril-14.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-stril-15.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector signed short
|
||||
doString(vector signed short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector signed short result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
28
gcc/testsuite/gcc.target/powerpc/vec-stril-15.c
Normal file
28
gcc/testsuite/gcc.target/powerpc/vec-stril-15.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector signed short
|
||||
doString(vector signed short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both and should
|
||||
convert tail recursion to iteration with two copies of the "loop
|
||||
body" when compiled with -O2 or -O3. */
|
||||
vector signed short result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that exactly two dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 2 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 2 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
56
gcc/testsuite/gcc.target/powerpc/vec-stril-16.c
Normal file
56
gcc/testsuite/gcc.target/powerpc/vec-stril-16.c
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-stril-17.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector unsigned char
|
||||
doString(vector unsigned char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector unsigned char result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char composed_string [4] = {
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 }
|
||||
};
|
||||
|
||||
vector unsigned char expected0 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char expected1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 00, 0x0 };
|
||||
vector unsigned char expected2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
|
||||
vector unsigned char expected3 =
|
||||
{ 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
54
gcc/testsuite/gcc.target/powerpc/vec-stril-17.c
Normal file
54
gcc/testsuite/gcc.target/powerpc/vec-stril-17.c
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector unsigned char
|
||||
doString(vector unsigned char *vp)
|
||||
{
|
||||
/* Tail recursion replaced with iteration with -O2. */
|
||||
vector unsigned char result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char composed_string [4] = {
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 }
|
||||
};
|
||||
|
||||
vector unsigned char expected0 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char expected1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 00, 0x0 };
|
||||
vector unsigned char expected2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
|
||||
vector unsigned char expected3 =
|
||||
{ 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
56
gcc/testsuite/gcc.target/powerpc/vec-stril-18.c
Normal file
56
gcc/testsuite/gcc.target/powerpc/vec-stril-18.c
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-stril-19.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector signed char
|
||||
doString(vector signed char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector signed char result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char composed_string [4] = {
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 }
|
||||
};
|
||||
|
||||
vector signed char expected0 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector signed char expected1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 00, 0x0 };
|
||||
vector signed char expected2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
|
||||
vector signed char expected3 =
|
||||
{ 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
54
gcc/testsuite/gcc.target/powerpc/vec-stril-19.c
Normal file
54
gcc/testsuite/gcc.target/powerpc/vec-stril-19.c
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector signed char
|
||||
doString(vector signed char *vp)
|
||||
{
|
||||
/* Tail recursion replaced with iteration with -O2. */
|
||||
vector signed char result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char composed_string [4] = {
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 }
|
||||
};
|
||||
|
||||
vector signed char expected0 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector signed char expected1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 00, 0x0 };
|
||||
vector signed char expected2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
|
||||
vector signed char expected3 =
|
||||
{ 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
21
gcc/testsuite/gcc.target/powerpc/vec-stril-2.c
Normal file
21
gcc/testsuite/gcc.target/powerpc/vec-stril-2.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of signed char. */
|
||||
vector signed char
|
||||
silj (vector signed char arg)
|
||||
{
|
||||
return vec_stril (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M} 0 { target { le } } } } */
|
||||
46
gcc/testsuite/gcc.target/powerpc/vec-stril-20.c
Normal file
46
gcc/testsuite/gcc.target/powerpc/vec-stril-20.c
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-stril-21.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector unsigned short
|
||||
doString(vector unsigned short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector unsigned short result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short composed_string [4] = {
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 },
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 }
|
||||
};
|
||||
|
||||
vector unsigned short expected0 = { 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected1 = { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector unsigned short expected2 = { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector unsigned short expected3 = { 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
|
||||
|
||||
44
gcc/testsuite/gcc.target/powerpc/vec-stril-21.c
Normal file
44
gcc/testsuite/gcc.target/powerpc/vec-stril-21.c
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector unsigned short
|
||||
doString(vector unsigned short *vp)
|
||||
{
|
||||
/* Iteration replaces tail recursion with -O2. */
|
||||
vector unsigned short result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short composed_string [4] = {
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 },
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 }
|
||||
};
|
||||
|
||||
vector unsigned short expected0 = { 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected1 = { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector unsigned short expected2 = { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector unsigned short expected3 = { 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
|
||||
|
||||
44
gcc/testsuite/gcc.target/powerpc/vec-stril-22.c
Normal file
44
gcc/testsuite/gcc.target/powerpc/vec-stril-22.c
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-stril-23.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector signed short
|
||||
doString(vector signed short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector signed short result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short composed_string [4] = {
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 },
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 }
|
||||
};
|
||||
|
||||
vector signed short expected0 = { 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected1 = { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed short expected2 = { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed short expected3 = { 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
42
gcc/testsuite/gcc.target/powerpc/vec-stril-23.c
Normal file
42
gcc/testsuite/gcc.target/powerpc/vec-stril-23.c
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector signed short
|
||||
doString(vector signed short *vp)
|
||||
{
|
||||
/* Iteration replaces tail recursion with -O2. */
|
||||
vector signed short result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short composed_string [4] = {
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 },
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 }
|
||||
};
|
||||
|
||||
vector signed short expected0 = { 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected1 = { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed short expected2 = { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed short expected3 = { 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
52
gcc/testsuite/gcc.target/powerpc/vec-stril-3.c
Normal file
52
gcc/testsuite/gcc.target/powerpc/vec-stril-3.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed char. */
|
||||
vector signed char
|
||||
silj (vector signed char arg)
|
||||
{
|
||||
return vec_stril (arg);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char input1 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char expected1 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char input2 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector signed char expected2 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
|
||||
vector signed char input3 =
|
||||
{ 0x1, 0x2, 0xf3, 0x0, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
vector signed char expected3 =
|
||||
{ 0x1, 0x2, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed char input4 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
vector signed char expected4 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x0 };
|
||||
|
||||
if (!vec_all_eq (silj (input1), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input2), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input3), expected3))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input4), expected4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
21
gcc/testsuite/gcc.target/powerpc/vec-stril-4.c
Normal file
21
gcc/testsuite/gcc.target/powerpc/vec-stril-4.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of unsigned short. */
|
||||
vector unsigned short
|
||||
silj (vector unsigned short arg)
|
||||
{
|
||||
return vec_stril (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
45
gcc/testsuite/gcc.target/powerpc/vec-stril-5.c
Normal file
45
gcc/testsuite/gcc.target/powerpc/vec-stril-5.c
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of unsigned short. */
|
||||
vector unsigned short
|
||||
silj (vector unsigned short arg)
|
||||
{
|
||||
return vec_stril (arg);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected2 =
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector unsigned short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short expected3 =
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector unsigned short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short expected4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
|
||||
if (!vec_all_eq (silj (input1), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input2), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input3), expected3))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input4), expected4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
21
gcc/testsuite/gcc.target/powerpc/vec-stril-6.c
Normal file
21
gcc/testsuite/gcc.target/powerpc/vec-stril-6.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of signed short. */
|
||||
vector signed short
|
||||
silj (vector signed short arg)
|
||||
{
|
||||
return vec_stril (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
43
gcc/testsuite/gcc.target/powerpc/vec-stril-7.c
Normal file
43
gcc/testsuite/gcc.target/powerpc/vec-stril-7.c
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of signed short. */
|
||||
vector signed short
|
||||
silj (vector signed short arg)
|
||||
{
|
||||
return vec_stril (arg);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected2 =
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector signed short expected3 =
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector signed short expected4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (!vec_all_eq (silj (input1), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input2), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input3), expected3))
|
||||
abort ();
|
||||
if (!vec_all_eq (silj (input4), expected4))
|
||||
abort ();
|
||||
}
|
||||
27
gcc/testsuite/gcc.target/powerpc/vec-stril-8.c
Normal file
27
gcc/testsuite/gcc.target/powerpc/vec-stril-8.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future -O1" } */
|
||||
/* See vec-stril-9.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector unsigned char
|
||||
doString(vector unsigned char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector unsigned char result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { le } } } } */
|
||||
28
gcc/testsuite/gcc.target/powerpc/vec-stril-9.c
Normal file
28
gcc/testsuite/gcc.target/powerpc/vec-stril-9.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector unsigned char
|
||||
doString(vector unsigned char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both and should
|
||||
convert tail recursion to iteration with two copies of the "loop
|
||||
body" when compiled with -O2 or -O3. */
|
||||
vector unsigned char result = vec_stril (*vp);
|
||||
if (vec_stril_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that exactly two dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 2 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 2 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { le } } } } */
|
||||
24
gcc/testsuite/gcc.target/powerpc/vec-stril_p-0.c
Normal file
24
gcc/testsuite/gcc.target/powerpc/vec-stril_p-0.c
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified predicate on array of
|
||||
unsigned char. */
|
||||
int
|
||||
silj_p (vector unsigned char arg)
|
||||
{
|
||||
return vec_stril_p (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { le } } } } */
|
||||
41
gcc/testsuite/gcc.target/powerpc/vec-stril_p-1.c
Normal file
41
gcc/testsuite/gcc.target/powerpc/vec-stril_p-1.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified predicate on array of
|
||||
unsigned char. */
|
||||
int
|
||||
silj_p (vector unsigned char arg)
|
||||
{
|
||||
return vec_stril_p (arg);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char input1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char input2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input3 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input4 =
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
|
||||
if (silj_p (input1))
|
||||
abort ();
|
||||
if (!silj_p (input2))
|
||||
abort ();
|
||||
if (!silj_p (input3))
|
||||
abort ();
|
||||
if (!silj_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
37
gcc/testsuite/gcc.target/powerpc/vec-stril_p-10.c
Normal file
37
gcc/testsuite/gcc.target/powerpc/vec-stril_p-10.c
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (vec_stril_p (input1))
|
||||
abort ();
|
||||
if (!vec_stril_p (input2))
|
||||
abort ();
|
||||
if (!vec_stril_p (input3))
|
||||
abort ();
|
||||
if (!vec_stril_p (input4))
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* Enforce that exactly four dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 4 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 4 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
37
gcc/testsuite/gcc.target/powerpc/vec-stril_p-11.c
Normal file
37
gcc/testsuite/gcc.target/powerpc/vec-stril_p-11.c
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector signed short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (vec_stril_p (input1))
|
||||
abort ();
|
||||
if (!vec_stril_p (input2))
|
||||
abort ();
|
||||
if (!vec_stril_p (input3))
|
||||
abort ();
|
||||
if (!vec_stril_p (input4))
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* Enforce that exactly four dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 4 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 4 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
23
gcc/testsuite/gcc.target/powerpc/vec-stril_p-2.c
Normal file
23
gcc/testsuite/gcc.target/powerpc/vec-stril_p-2.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of signed char. */
|
||||
int
|
||||
silj_p (vector signed char arg)
|
||||
{
|
||||
return vec_stril_p (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { le } } } } */
|
||||
40
gcc/testsuite/gcc.target/powerpc/vec-stril_p-3.c
Normal file
40
gcc/testsuite/gcc.target/powerpc/vec-stril_p-3.c
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed char. */
|
||||
int
|
||||
silj_p (vector signed char arg)
|
||||
{
|
||||
return vec_stril_p (arg);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char input1 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char input2 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector signed char input3 =
|
||||
{ 0x1, 0x2, 0xf3, 0x0, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
vector signed char input4 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
|
||||
if (silj_p (input1))
|
||||
abort ();
|
||||
if (!silj_p (input2))
|
||||
abort ();
|
||||
if (!silj_p (input3))
|
||||
abort ();
|
||||
if (!silj_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
23
gcc/testsuite/gcc.target/powerpc/vec-stril_p-4.c
Normal file
23
gcc/testsuite/gcc.target/powerpc/vec-stril_p-4.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of unsigned short. */
|
||||
int
|
||||
silj_p (vector unsigned short arg)
|
||||
{
|
||||
return vec_stril_p (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
35
gcc/testsuite/gcc.target/powerpc/vec-stril_p-5.c
Normal file
35
gcc/testsuite/gcc.target/powerpc/vec-stril_p-5.c
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of unsigned short. */
|
||||
int
|
||||
silj_p (vector unsigned short arg)
|
||||
{
|
||||
return vec_stril_p (arg);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (silj_p (input1))
|
||||
abort ();
|
||||
if (!silj_p (input2))
|
||||
abort ();
|
||||
if (!silj_p (input3))
|
||||
abort ();
|
||||
if (!silj_p (input4))
|
||||
abort ();
|
||||
}
|
||||
23
gcc/testsuite/gcc.target/powerpc/vec-stril_p-6.c
Normal file
23
gcc/testsuite/gcc.target/powerpc/vec-stril_p-6.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of signed short. */
|
||||
int
|
||||
silj_p (vector signed short arg)
|
||||
{
|
||||
return vec_stril_p (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { le } } } } */
|
||||
36
gcc/testsuite/gcc.target/powerpc/vec-stril_p-7.c
Normal file
36
gcc/testsuite/gcc.target/powerpc/vec-stril_p-7.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate left-justified on array of signed short. */
|
||||
int
|
||||
silj_p (vector signed short arg)
|
||||
{
|
||||
return vec_stril_p (arg);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector signed short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (silj_p (input1))
|
||||
abort ();
|
||||
if (!silj_p (input2))
|
||||
abort ();
|
||||
if (!silj_p (input3))
|
||||
abort ();
|
||||
if (!silj_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
42
gcc/testsuite/gcc.target/powerpc/vec-stril_p-8.c
Normal file
42
gcc/testsuite/gcc.target/powerpc/vec-stril_p-8.c
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char input1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char input2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input3 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input4 =
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
|
||||
if (vec_stril_p (input1))
|
||||
abort ();
|
||||
if (!vec_stril_p (input2))
|
||||
abort ();
|
||||
if (!vec_stril_p (input3))
|
||||
abort ();
|
||||
if (!vec_stril_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
|
||||
/* Enforce that exactly four dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 4 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 4 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { le } } } } */
|
||||
42
gcc/testsuite/gcc.target/powerpc/vec-stril_p-9.c
Normal file
42
gcc/testsuite/gcc.target/powerpc/vec-stril_p-9.c
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char input1 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char input2 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector signed char input3 =
|
||||
{ 0x1, 0x2, 0xf3, 0x0, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
vector signed char input4 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
|
||||
if (vec_stril_p (input1))
|
||||
abort ();
|
||||
if (!vec_stril_p (input2))
|
||||
abort ();
|
||||
if (!vec_stril_p (input3))
|
||||
abort ();
|
||||
if (!vec_stril_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
|
||||
/* Enforce that exactly four dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 4 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 4 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { le } } } } */
|
||||
21
gcc/testsuite/gcc.target/powerpc/vec-strir-0.c
Normal file
21
gcc/testsuite/gcc.target/powerpc/vec-strir-0.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of unsigned char. */
|
||||
vector unsigned char
|
||||
sirj (vector unsigned char arg)
|
||||
{
|
||||
return vec_strir (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
52
gcc/testsuite/gcc.target/powerpc/vec-strir-1.c
Normal file
52
gcc/testsuite/gcc.target/powerpc/vec-strir-1.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of unsigned char. */
|
||||
vector unsigned char
|
||||
sirj (vector unsigned char arg)
|
||||
{
|
||||
return vec_strir (arg);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char input1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char expected1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char input2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input3 =
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input4 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char expected4 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
|
||||
if (!vec_all_eq (sirj (input1), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input2), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input3), expected3))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input4), expected4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
27
gcc/testsuite/gcc.target/powerpc/vec-strir-10.c
Normal file
27
gcc/testsuite/gcc.target/powerpc/vec-strir-10.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-strir-11.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector signed char
|
||||
doString(vector signed char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector signed char result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
28
gcc/testsuite/gcc.target/powerpc/vec-strir-11.c
Normal file
28
gcc/testsuite/gcc.target/powerpc/vec-strir-11.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector signed char
|
||||
doString(vector signed char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both and should
|
||||
convert tail recursion to iteration with two copies of the "loop
|
||||
body" when compiled with -O2 or -O3. */
|
||||
vector signed char result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that exactly two dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 2 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 2 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
28
gcc/testsuite/gcc.target/powerpc/vec-strir-12.c
Normal file
28
gcc/testsuite/gcc.target/powerpc/vec-strir-12.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-strir-13.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector unsigned short
|
||||
doString(vector unsigned short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector unsigned short result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
|
||||
29
gcc/testsuite/gcc.target/powerpc/vec-strir-13.c
Normal file
29
gcc/testsuite/gcc.target/powerpc/vec-strir-13.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector unsigned short
|
||||
doString(vector unsigned short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both and should
|
||||
convert tail recursion to iteration with two copies of the "loop
|
||||
body" when compiled with -O2 or -O3. */
|
||||
vector unsigned short result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that exactly two dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 2 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 2 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
|
||||
27
gcc/testsuite/gcc.target/powerpc/vec-strir-14.c
Normal file
27
gcc/testsuite/gcc.target/powerpc/vec-strir-14.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-strir-15.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector signed short
|
||||
doString(vector signed short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector signed short result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
28
gcc/testsuite/gcc.target/powerpc/vec-strir-15.c
Normal file
28
gcc/testsuite/gcc.target/powerpc/vec-strir-15.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector signed short
|
||||
doString(vector signed short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both and should
|
||||
convert tail recursion to iteration with two copies of the "loop
|
||||
body" when compiled with -O2 or -O3. */
|
||||
vector signed short result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that exactly two dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 2 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 2 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
56
gcc/testsuite/gcc.target/powerpc/vec-strir-16.c
Normal file
56
gcc/testsuite/gcc.target/powerpc/vec-strir-16.c
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-strir-17.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector unsigned char
|
||||
doString(vector unsigned char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector unsigned char result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char composed_string [4] = {
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x0, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 }
|
||||
};
|
||||
|
||||
vector unsigned char expected0 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char expected1 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
54
gcc/testsuite/gcc.target/powerpc/vec-strir-17.c
Normal file
54
gcc/testsuite/gcc.target/powerpc/vec-strir-17.c
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector unsigned char
|
||||
doString(vector unsigned char *vp)
|
||||
{
|
||||
/* Tail recursion replaced with iteration with -O2. */
|
||||
vector unsigned char result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char composed_string [4] = {
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x0, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 }
|
||||
};
|
||||
|
||||
vector unsigned char expected0 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char expected1 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
56
gcc/testsuite/gcc.target/powerpc/vec-strir-18.c
Normal file
56
gcc/testsuite/gcc.target/powerpc/vec-strir-18.c
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-strir-19.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector signed char
|
||||
doString(vector signed char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector signed char result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char composed_string [4] = {
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0xf3, 0x0, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 },
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 }
|
||||
};
|
||||
|
||||
vector signed char expected0 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char expected1 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
vector signed char expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11 };
|
||||
vector signed char expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
54
gcc/testsuite/gcc.target/powerpc/vec-strir-19.c
Normal file
54
gcc/testsuite/gcc.target/powerpc/vec-strir-19.c
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector signed char
|
||||
doString(vector signed char *vp)
|
||||
{
|
||||
/* Tail recursion replaced with iteration with -O2. */
|
||||
vector signed char result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char composed_string [4] = {
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 },
|
||||
{ 0x1, 0x2, 0xf3, 0x0, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 },
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 }
|
||||
};
|
||||
|
||||
vector signed char expected0 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char expected1 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
vector signed char expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11 };
|
||||
vector signed char expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11 };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
21
gcc/testsuite/gcc.target/powerpc/vec-strir-2.c
Normal file
21
gcc/testsuite/gcc.target/powerpc/vec-strir-2.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed char. */
|
||||
vector signed char
|
||||
sirj (vector signed char arg)
|
||||
{
|
||||
return vec_strir (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
48
gcc/testsuite/gcc.target/powerpc/vec-strir-20.c
Normal file
48
gcc/testsuite/gcc.target/powerpc/vec-strir-20.c
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-strir-21.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector unsigned short
|
||||
doString(vector unsigned short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector unsigned short result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short composed_string [4] = {
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 },
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0x0, 0xd, 0xe }
|
||||
};
|
||||
|
||||
vector unsigned short expected0 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected1 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector unsigned short expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xe };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
46
gcc/testsuite/gcc.target/powerpc/vec-strir-21.c
Normal file
46
gcc/testsuite/gcc.target/powerpc/vec-strir-21.c
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector unsigned short
|
||||
doString(vector unsigned short *vp)
|
||||
{
|
||||
/* Iteration replaces tail recursion with -O2. */
|
||||
vector unsigned short result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short composed_string [4] = {
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 },
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0x0, 0xd, 0xe }
|
||||
};
|
||||
|
||||
vector unsigned short expected0 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected1 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector unsigned short expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xe };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
48
gcc/testsuite/gcc.target/powerpc/vec-strir-22.c
Normal file
48
gcc/testsuite/gcc.target/powerpc/vec-strir-22.c
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-strir-23.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector signed short
|
||||
doString(vector signed short *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector signed short result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short composed_string [4] = {
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 },
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0x0, 0xd, 0xe }
|
||||
};
|
||||
|
||||
vector signed short expected0 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected1 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed short expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xe };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
46
gcc/testsuite/gcc.target/powerpc/vec-strir-23.c
Normal file
46
gcc/testsuite/gcc.target/powerpc/vec-strir-23.c
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
vector signed short
|
||||
doString(vector signed short *vp)
|
||||
{
|
||||
/* Iteration replaces tail recursion with -O2. */
|
||||
vector signed short result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short composed_string [4] = {
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf },
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 },
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0x0, 0xd, 0xe }
|
||||
};
|
||||
|
||||
vector signed short expected0 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected1 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed short expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xe };
|
||||
|
||||
if (!vec_all_eq (doString (&composed_string[0]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[1]), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[2]), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (doString (&composed_string[3]), expected3))
|
||||
abort ();
|
||||
}
|
||||
52
gcc/testsuite/gcc.target/powerpc/vec-strir-3.c
Normal file
52
gcc/testsuite/gcc.target/powerpc/vec-strir-3.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed char. */
|
||||
vector signed char
|
||||
sirj (vector signed char arg)
|
||||
{
|
||||
return vec_strir (arg);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char input1 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char expected1 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char input2 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector signed char expected2 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x11 };
|
||||
vector signed char input3 =
|
||||
{ 0x1, 0x2, 0xf3, 0x0, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
vector signed char expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11 };
|
||||
vector signed char input4 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
vector signed char expected4 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11 };
|
||||
|
||||
if (!vec_all_eq (sirj (input1), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input2), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input3), expected3))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input4), expected4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
21
gcc/testsuite/gcc.target/powerpc/vec-strir-4.c
Normal file
21
gcc/testsuite/gcc.target/powerpc/vec-strir-4.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of unsigned short. */
|
||||
vector unsigned short
|
||||
sirj (vector unsigned short arg)
|
||||
{
|
||||
return vec_strir (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
44
gcc/testsuite/gcc.target/powerpc/vec-strir-5.c
Normal file
44
gcc/testsuite/gcc.target/powerpc/vec-strir-5.c
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of unsigned short. */
|
||||
vector unsigned short
|
||||
sirj (vector unsigned short arg)
|
||||
{
|
||||
return vec_strir (arg);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected2 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector unsigned short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short expected4 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
|
||||
if (!vec_all_eq (sirj (input1), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input2), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input3), expected3))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input4), expected4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
21
gcc/testsuite/gcc.target/powerpc/vec-strir-6.c
Normal file
21
gcc/testsuite/gcc.target/powerpc/vec-strir-6.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed short. */
|
||||
vector signed short
|
||||
sirj (vector signed short arg)
|
||||
{
|
||||
return vec_strir (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
44
gcc/testsuite/gcc.target/powerpc/vec-strir-7.c
Normal file
44
gcc/testsuite/gcc.target/powerpc/vec-strir-7.c
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed short. */
|
||||
vector signed short
|
||||
sirj (vector signed short arg)
|
||||
{
|
||||
return vec_strir (arg);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short expected2 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector signed short expected3 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector signed short expected4 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
|
||||
if (!vec_all_eq (sirj (input1), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input2), expected2))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input3), expected3))
|
||||
abort ();
|
||||
if (!vec_all_eq (sirj (input4), expected4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
27
gcc/testsuite/gcc.target/powerpc/vec-strir-8.c
Normal file
27
gcc/testsuite/gcc.target/powerpc/vec-strir-8.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O1 -mdejagnu-cpu=future" } */
|
||||
/* See vec-strir-9.c for the same test with -O2 optimization. */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector unsigned char
|
||||
doString(vector unsigned char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both with -O1. */
|
||||
vector unsigned char result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
28
gcc/testsuite/gcc.target/powerpc/vec-strir-9.c
Normal file
28
gcc/testsuite/gcc.target/powerpc/vec-strir-9.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector unsigned char
|
||||
doString(vector unsigned char *vp)
|
||||
{
|
||||
/* Though two built-in functions are called, the implementation
|
||||
should use a single instruction to implement both and should
|
||||
convert tail recursion to iteration with two copies of the "loop
|
||||
body" when compiled with -O2 or -O3. */
|
||||
vector unsigned char result = vec_strir (*vp);
|
||||
if (vec_strir_p (*vp))
|
||||
return result;
|
||||
else
|
||||
return doString (vp + 1);
|
||||
}
|
||||
|
||||
/* Enforce that exactly two dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 2 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 2 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
23
gcc/testsuite/gcc.target/powerpc/vec-strir_p-0.c
Normal file
23
gcc/testsuite/gcc.target/powerpc/vec-strir_p-0.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of unsigned char. */
|
||||
int
|
||||
sirj_p (vector unsigned char arg)
|
||||
{
|
||||
return vec_strir_p (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
39
gcc/testsuite/gcc.target/powerpc/vec-strir_p-1.c
Normal file
39
gcc/testsuite/gcc.target/powerpc/vec-strir_p-1.c
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of unsigned char. */
|
||||
int
|
||||
sirj_p (vector unsigned char arg)
|
||||
{
|
||||
return vec_strir_p (arg);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char input1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char input2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input3 =
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input4 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
|
||||
if (sirj_p (input1))
|
||||
abort ();
|
||||
if (!sirj_p (input2))
|
||||
abort ();
|
||||
if (!sirj_p (input3))
|
||||
abort ();
|
||||
if (!sirj_p (input4))
|
||||
abort ();
|
||||
}
|
||||
46
gcc/testsuite/gcc.target/powerpc/vec-strir_p-10.c
Normal file
46
gcc/testsuite/gcc.target/powerpc/vec-strir_p-10.c
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected2 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short expected3 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short expected4 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
|
||||
if (vec_strir_p (input1))
|
||||
abort ();
|
||||
if (!vec_strir_p (input2))
|
||||
abort ();
|
||||
if (!vec_strir_p (input3))
|
||||
abort ();
|
||||
if (!vec_strir_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
|
||||
/* Enforce that exactly four dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 4 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 4 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
38
gcc/testsuite/gcc.target/powerpc/vec-strir_p-11.c
Normal file
38
gcc/testsuite/gcc.target/powerpc/vec-strir_p-11.c
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector signed short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (vec_strir_p (input1))
|
||||
abort ();
|
||||
if (!vec_strir_p (input2))
|
||||
abort ();
|
||||
if (!vec_strir_p (input3))
|
||||
abort ();
|
||||
if (!vec_strir_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
|
||||
/* Enforce that exactly four dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 4 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 4 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
23
gcc/testsuite/gcc.target/powerpc/vec-strir_p-2.c
Normal file
23
gcc/testsuite/gcc.target/powerpc/vec-strir_p-2.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed char. */
|
||||
int
|
||||
sirj_p (vector signed char arg)
|
||||
{
|
||||
return vec_strir_p (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
40
gcc/testsuite/gcc.target/powerpc/vec-strir_p-3.c
Normal file
40
gcc/testsuite/gcc.target/powerpc/vec-strir_p-3.c
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed char. */
|
||||
int
|
||||
sirj_p (vector signed char arg)
|
||||
{
|
||||
return vec_strir_p (arg);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char input1 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char input2 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector signed char input3 =
|
||||
{ 0x1, 0x2, 0xf3, 0x0, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
vector signed char input4 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
|
||||
if (sirj_p (input1))
|
||||
abort ();
|
||||
if (!sirj_p (input2))
|
||||
abort ();
|
||||
if (!sirj_p (input3))
|
||||
abort ();
|
||||
if (!sirj_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
23
gcc/testsuite/gcc.target/powerpc/vec-strir_p-4.c
Normal file
23
gcc/testsuite/gcc.target/powerpc/vec-strir_p-4.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of unsigned short. */
|
||||
int
|
||||
sirj_p (vector unsigned short arg)
|
||||
{
|
||||
return vec_strir_p (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
44
gcc/testsuite/gcc.target/powerpc/vec-strir_p-5.c
Normal file
44
gcc/testsuite/gcc.target/powerpc/vec-strir_p-5.c
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of unsigned short. */
|
||||
int
|
||||
sirj_p (vector unsigned short arg)
|
||||
{
|
||||
return vec_strir_p (arg);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector unsigned short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short expected2 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector unsigned short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short expected3 =
|
||||
{ 0x0, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector unsigned short expected4 =
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
|
||||
if (sirj_p (input1))
|
||||
abort ();
|
||||
if (!sirj_p (input2))
|
||||
abort ();
|
||||
if (!sirj_p (input3))
|
||||
abort ();
|
||||
if (!sirj_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
23
gcc/testsuite/gcc.target/powerpc/vec-strir_p-6.c
Normal file
23
gcc/testsuite/gcc.target/powerpc/vec-strir_p-6.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed short. */
|
||||
int
|
||||
sirj_p (vector signed short arg)
|
||||
{
|
||||
return vec_strir_p (arg);
|
||||
}
|
||||
|
||||
/* Enforce that a single dot-form instruction which is properly biased
|
||||
for the target's endianness implements this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\.} 1 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\.} 1 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
|
||||
36
gcc/testsuite/gcc.target/powerpc/vec-strir_p-7.c
Normal file
36
gcc/testsuite/gcc.target/powerpc/vec-strir_p-7.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string isolate right-justified on array of signed short. */
|
||||
int
|
||||
sirj_p (vector signed short arg)
|
||||
{
|
||||
return vec_strir_p (arg);
|
||||
}
|
||||
|
||||
int main (int argc, short *argv [])
|
||||
{
|
||||
vector signed short input1 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input2 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf };
|
||||
vector signed short input3 =
|
||||
{ 0x1, 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
vector signed short input4 =
|
||||
{ 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0x0 };
|
||||
|
||||
if (sirj_p (input1))
|
||||
abort ();
|
||||
if (!sirj_p (input2))
|
||||
abort ();
|
||||
if (!sirj_p (input3))
|
||||
abort ();
|
||||
if (!sirj_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
43
gcc/testsuite/gcc.target/powerpc/vec-strir_p-8.c
Normal file
43
gcc/testsuite/gcc.target/powerpc/vec-strir_p-8.c
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector unsigned char input1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector unsigned char input2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input3 =
|
||||
{ 0x1, 0x2, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector unsigned char input4 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
|
||||
if (!vec_strir_p (input1))
|
||||
abort ();
|
||||
if (!vec_strir_p (input2))
|
||||
abort ();
|
||||
if (!vec_strir_p (input3))
|
||||
abort ();
|
||||
if (!vec_strir_p (input4))
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* Enforce that exactly four dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 4 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 4 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
|
||||
|
||||
42
gcc/testsuite/gcc.target/powerpc/vec-strir_p-9.c
Normal file
42
gcc/testsuite/gcc.target/powerpc/vec-strir_p-9.c
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char input1 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0xf, 0x11 };
|
||||
vector signed char input2 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0xf, 0x11 };
|
||||
vector signed char input3 =
|
||||
{ 0x1, 0x2, 0xf3, 0x0, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
vector signed char input4 =
|
||||
{ 0x1, 0x2, 0xf3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe2, 0x0, 0x11 };
|
||||
|
||||
if (vec_strir_p (input1))
|
||||
abort ();
|
||||
if (!vec_strir_p (input2))
|
||||
abort ();
|
||||
if (!vec_strir_p (input3))
|
||||
abort ();
|
||||
if (!vec_strir_p (input4))
|
||||
abort ();
|
||||
|
||||
}
|
||||
|
||||
/* Enforce that exactly four dot-form instructions which are properly biased
|
||||
for the target's endianness implement this built-in. */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\.} 4 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr\M[^.]} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl} 0 { target { be } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\.} 4 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribl\M[^.]} 0 { target { le } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvstribr} 0 { target { le } } } } */
|
||||
Loading…
Add table
Reference in a new issue