aarch64: Emit single-instruction for smin (x, 0) and smax (x, 0)
Motivated by https://reviews.llvm.org/D148249, we can expand to a single instruction for the SMIN (x, 0) and SMAX (x, 0) cases using the combined AND/BIC and ASR operations. Given that we already have well-fitting TARGET_CSSC patterns and expanders for the min/max codes in the backend this patch does some minor refactoring to ensure we emit the right SMAX/SMIN RTL codes for TARGET_CSSC, fall back to the generic expanders or emit a simple SMIN/SMAX with 0 RTX for !TARGET_CSSC that is now matched by a separate pattern. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64.md (aarch64_umax<mode>3_insn): Delete. (umax<mode>3): Emit raw UMAX RTL instead of going through gen_ function for umax. (<optab><mode>3): New define_expand for MAXMIN_NOUMAX codes. (*aarch64_<optab><mode>3_zero): Define. (*aarch64_<optab><mode>3_cssc): Likewise. * config/aarch64/iterators.md (maxminand): New code attribute. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sminmax-asr_1.c: New test.
This commit is contained in:
Kyrylo Tkachov
parent
573624ec90
commit
88195141ae
3 changed files with 97 additions and 15 deletions
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@ -4412,17 +4412,6 @@
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[(set_attr "type" "csel")]
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)
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(define_insn "aarch64_umax<mode>3_insn"
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[(set (match_operand:GPI 0 "register_operand" "=r,r")
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(umax:GPI (match_operand:GPI 1 "register_operand" "r,r")
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(match_operand:GPI 2 "aarch64_uminmax_operand" "r,Uum")))]
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"TARGET_CSSC"
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"@
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umax\\t%<w>0, %<w>1, %<w>2
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umax\\t%<w>0, %<w>1, %2"
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[(set_attr "type" "alu_sreg,alu_imm")]
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)
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;; If X can be loaded by a single CNT[BHWD] instruction,
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;;
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;; A = UMAX (B, X)
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@ -4466,8 +4455,8 @@
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operands[1] = force_reg (<MODE>mode, operands[1]);
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if (!aarch64_uminmax_operand (operands[2], <MODE>mode))
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operands[2] = force_reg (<MODE>mode, operands[2]);
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emit_insn (gen_aarch64_umax<mode>3_insn (operands[0], operands[1],
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operands[2]));
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emit_move_insn (operands[0], gen_rtx_UMAX (<MODE>mode, operands[1],
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operands[2]));
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DONE;
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}
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else
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@ -6759,9 +6748,30 @@
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[(set_attr "type" "ffarith<stype>")]
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)
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(define_insn "<optab><mode>3"
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;; Expander for integer smin, smax, umin. Mainly used to generate
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;; straightforward RTL for TARGET_CSSC. When that is not available
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;; FAIL and let the generic expanders generate the CMP + CSEL sequences,
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;; except for the SMIN and SMAX with zero cases, for which we have a
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;; single instruction even for the base architecture.
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(define_expand "<optab><mode>3"
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[(set (match_operand:GPI 0 "register_operand")
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(MAXMIN_NOUMAX:GPI
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(match_operand:GPI 1 "register_operand")
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(match_operand:GPI 2 "aarch64_<su>minmax_operand")))]
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""
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{
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if (!TARGET_CSSC)
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{
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if (operands[2] != CONST0_RTX (<MODE>mode)
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|| !(<CODE> == SMAX || <CODE> == SMIN))
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FAIL;
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}
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}
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)
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(define_insn "*aarch64_<optab><mode>3_cssc"
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[(set (match_operand:GPI 0 "register_operand" "=r,r")
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(MAXMIN_NOUMAX:GPI (match_operand:GPI 1 "register_operand" "r,r")
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(MAXMIN:GPI (match_operand:GPI 1 "register_operand" "r,r")
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(match_operand:GPI 2 "aarch64_<su>minmax_operand" "r,U<su>m")))]
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"TARGET_CSSC"
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"@
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@ -6770,6 +6780,16 @@
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[(set_attr "type" "alu_sreg,alu_imm")]
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)
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(define_insn "*aarch64_<optab><mode>3_zero"
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[(set (match_operand:GPI 0 "register_operand" "=r")
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(FMAXMIN:GPI
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(match_operand:GPI 1 "register_operand" "r")
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(const_int 0)))]
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""
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"<maxminand>\\t%<w>0, %<w>1, %<w>1, asr <sizem1>";
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[(set_attr "type" "logic_shift_imm")]
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)
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;; Given that smax/smin do not specify the result when either input is NaN,
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;; we could use either FMAXNM or FMAX for smax, and either FMINNM or FMIN
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;; for smin.
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@ -2435,6 +2435,8 @@
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(umax "max")
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(umin "min")])
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(define_code_attr maxminand [(smax "bic") (smin "and")])
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;; MLA/MLS attributes.
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(define_code_attr as [(ss_plus "a") (ss_minus "s")])
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60
gcc/testsuite/gcc.target/aarch64/sminmax-asr_1.c
Normal file
60
gcc/testsuite/gcc.target/aarch64/sminmax-asr_1.c
Normal file
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@ -0,0 +1,60 @@
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/* { dg-do compile } */
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/* { dg-options "-O --save-temps" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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#include <stdint.h>
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#pragma GCC target "+nocssc"
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#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
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#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
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/*
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** minzero:
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** and w0, w0, w0, asr #31
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** ret
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*/
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int32_t
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minzero (int32_t a)
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{
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return MIN (a, 0);
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}
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/*
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** maxzero:
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** bic w0, w0, w0, asr #31
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** ret
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*/
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int32_t
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maxzero (int32_t a)
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{
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return MAX (a, 0);
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}
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/*
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** minzerol:
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** and x0, x0, x0, asr #63
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** ret
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*/
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int64_t
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minzerol (int64_t a)
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{
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return MIN (a, 0);
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}
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/*
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** maxzerol:
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** bic x0, x0, x0, asr #63
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** ret
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*/
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int64_t
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maxzerol (int64_t a)
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{
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return MAX (a, 0);
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}
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