aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins
Implement the ACLE builtins for 128-bit system register manipulation:
* __uint128_t __arm_rsr128(const char *special_register);
* void __arm_wsr128(const char *special_register, __uint128_t value);
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc (AARCH64_RSR128): New
`enum aarch64_builtins' value.
(AARCH64_WSR128): Likewise.
(aarch64_init_rwsr_builtins): Init `__builtin_aarch64_rsr128'
and `__builtin_aarch64_wsr128' builtins.
(aarch64_expand_rwsr_builtin): Extend function to handle
`__builtin_aarch64_{rsr|wsr}128'.
* config/aarch64/aarch64-protos.h (aarch64_retrieve_sysreg):
Update function signature.
* config/aarch64/aarch64.cc (F_REG_128): New.
(aarch64_retrieve_sysreg): Add 128-bit register mode check.
* config/aarch64/aarch64.md (UNSPEC_SYSREG_RTI): New.
(UNSPEC_SYSREG_WTI): Likewise.
(aarch64_read_sysregti): Likewise.
(aarch64_write_sysregti): Likewise.
* config/aarch64/arm_acle.h (__arm_rsr128): New.
(__arm_wsr128): Likewise.
This commit is contained in:
Victor Do Nascimento
parent
eac59af05a
commit
88157c8817
5 changed files with 80 additions and 11 deletions
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@ -815,11 +815,13 @@ enum aarch64_builtins
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AARCH64_RSR64,
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AARCH64_RSRF,
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AARCH64_RSRF64,
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AARCH64_RSR128,
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AARCH64_WSR,
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AARCH64_WSRP,
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AARCH64_WSR64,
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AARCH64_WSRF,
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AARCH64_WSRF64,
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AARCH64_WSR128,
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AARCH64_BUILTIN_MAX
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};
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@ -1842,6 +1844,10 @@ aarch64_init_rwsr_builtins (void)
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= build_function_type_list (double_type_node, const_char_ptr_type, NULL);
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AARCH64_INIT_RWSR_BUILTINS_DECL (RSRF64, rsrf64, fntype);
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fntype
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= build_function_type_list (uint128_type_node, const_char_ptr_type, NULL);
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AARCH64_INIT_RWSR_BUILTINS_DECL (RSR128, rsr128, fntype);
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fntype
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= build_function_type_list (void_type_node, const_char_ptr_type,
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uint32_type_node, NULL);
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@ -1867,6 +1873,12 @@ aarch64_init_rwsr_builtins (void)
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= build_function_type_list (void_type_node, const_char_ptr_type,
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double_type_node, NULL);
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AARCH64_INIT_RWSR_BUILTINS_DECL (WSRF64, wsrf64, fntype);
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fntype
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= build_function_type_list (void_type_node, const_char_ptr_type,
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uint128_type_node, NULL);
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AARCH64_INIT_RWSR_BUILTINS_DECL (WSR128, wsr128, fntype);
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}
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/* Initialize the memory tagging extension (MTE) builtins. */
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@ -2710,6 +2722,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
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tree arg0, arg1;
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rtx const_str, input_val, subreg;
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enum machine_mode mode;
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enum insn_code icode;
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class expand_operand ops[2];
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arg0 = CALL_EXPR_ARG (exp, 0);
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@ -2718,7 +2731,18 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
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|| fcode == AARCH64_WSRP
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|| fcode == AARCH64_WSR64
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|| fcode == AARCH64_WSRF
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|| fcode == AARCH64_WSRF64);
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|| fcode == AARCH64_WSRF64
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|| fcode == AARCH64_WSR128);
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bool op128 = (fcode == AARCH64_RSR128 || fcode == AARCH64_WSR128);
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enum machine_mode sysreg_mode = op128 ? TImode : DImode;
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if (op128 && !TARGET_D128)
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{
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error_at (EXPR_LOCATION (exp), "128-bit system register support requires"
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" the %<d128%> extension");
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return const0_rtx;
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}
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/* Argument 0 (system register name) must be a string literal. */
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gcc_assert (TREE_CODE (arg0) == ADDR_EXPR
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@ -2740,7 +2764,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
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for (unsigned pos = 0; pos <= len; pos++)
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sysreg_name[pos] = TOLOWER (sysreg_name[pos]);
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const char *name_output = aarch64_retrieve_sysreg (sysreg_name, write_op);
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const char* name_output = aarch64_retrieve_sysreg ((const char *) sysreg_name,
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write_op, op128);
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if (name_output == NULL)
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{
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error_at (EXPR_LOCATION (exp), "invalid system register name %qs",
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@ -2760,13 +2785,17 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
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mode = TYPE_MODE (TREE_TYPE (arg1));
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input_val = copy_to_mode_reg (mode, expand_normal (arg1));
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icode = (op128 ? CODE_FOR_aarch64_write_sysregti
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: CODE_FOR_aarch64_write_sysregdi);
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switch (fcode)
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{
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case AARCH64_WSR:
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case AARCH64_WSRP:
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case AARCH64_WSR64:
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case AARCH64_WSRF64:
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subreg = lowpart_subreg (DImode, input_val, mode);
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case AARCH64_WSR128:
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subreg = lowpart_subreg (sysreg_mode, input_val, mode);
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break;
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case AARCH64_WSRF:
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subreg = gen_lowpart_SUBREG (SImode, input_val);
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@ -2775,8 +2804,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
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}
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create_fixed_operand (&ops[0], const_str);
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create_input_operand (&ops[1], subreg, DImode);
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expand_insn (CODE_FOR_aarch64_write_sysregdi, 2, ops);
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create_input_operand (&ops[1], subreg, sysreg_mode);
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expand_insn (icode, 2, ops);
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return target;
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}
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@ -2784,10 +2813,13 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
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/* Read operations are implied by !write_op. */
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gcc_assert (call_expr_nargs (exp) == 1);
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icode = (op128 ? CODE_FOR_aarch64_read_sysregti
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: CODE_FOR_aarch64_read_sysregdi);
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/* Emit the initial read_sysregdi rtx. */
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create_output_operand (&ops[0], target, DImode);
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create_output_operand (&ops[0], target, sysreg_mode);
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create_fixed_operand (&ops[1], const_str);
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expand_insn (CODE_FOR_aarch64_read_sysregdi, 2, ops);
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expand_insn (icode, 2, ops);
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target = ops[0].value;
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/* Do any necessary post-processing on the result. */
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@ -2797,7 +2829,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
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case AARCH64_RSRP:
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case AARCH64_RSR64:
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case AARCH64_RSRF64:
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return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, DImode);
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case AARCH64_RSR128:
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return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
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case AARCH64_RSRF:
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subreg = gen_lowpart_SUBREG (SImode, target);
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return gen_lowpart_SUBREG (SFmode, subreg);
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@ -3044,11 +3077,13 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target,
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case AARCH64_RSR64:
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case AARCH64_RSRF:
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case AARCH64_RSRF64:
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case AARCH64_RSR128:
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case AARCH64_WSR:
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case AARCH64_WSRP:
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case AARCH64_WSR64:
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case AARCH64_WSRF:
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case AARCH64_WSRF64:
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case AARCH64_WSR128:
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return aarch64_expand_rwsr_builtin (exp, target, fcode);
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}
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@ -840,7 +840,7 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);
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bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,
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enum simd_immediate_check w = AARCH64_CHECK_MOV);
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bool aarch64_valid_sysreg_name_p (const char *);
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const char *aarch64_retrieve_sysreg (const char *, bool);
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const char *aarch64_retrieve_sysreg (const char *, bool, bool);
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rtx aarch64_check_zero_based_sve_index_immediate (rtx);
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bool aarch64_maybe_generate_simd_constant (rtx, rtx, machine_mode);
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bool aarch64_simd_special_constant_p (rtx, machine_mode);
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@ -498,6 +498,8 @@ typedef struct {
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#define F_ARCHEXT (1 << 4)
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/* Flag indicating register name is alias for another system register. */
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#define F_REG_ALIAS (1 << 5)
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/* Flag indicatinig registers which may be implemented with 128-bits. */
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#define F_REG_128 (1 << 6)
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/* Database of system registers, their encodings and architectural
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requirements. */
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@ -29083,9 +29085,10 @@ aarch64_valid_sysreg_name_p (const char *regname)
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/* Return the generic sysreg specification for a valid system register
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name, otherwise NULL. WRITE_P is true iff the register is being
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written to. */
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written to. IS128OP indicates the requested system register should
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be checked for a 128-bit implementation. */
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const char *
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aarch64_retrieve_sysreg (const char *regname, bool write_p)
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aarch64_retrieve_sysreg (const char *regname, bool write_p, bool is128op)
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{
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const sysreg_t *sysreg = aarch64_lookup_sysreg_map (regname);
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if (sysreg == NULL)
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@ -29095,6 +29098,8 @@ aarch64_retrieve_sysreg (const char *regname, bool write_p)
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else
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return NULL;
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}
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if (is128op && !(sysreg->properties & F_REG_128))
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return NULL;
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if ((write_p && (sysreg->properties & F_REG_READ))
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|| (!write_p && (sysreg->properties & F_REG_WRITE)))
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return NULL;
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@ -339,7 +339,9 @@
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UNSPEC_RDFFR
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UNSPEC_WRFFR
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UNSPEC_SYSREG_RDI
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UNSPEC_SYSREG_RTI
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UNSPEC_SYSREG_WDI
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UNSPEC_SYSREG_WTI
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;; Represents an SVE-style lane index, in which the indexing applies
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;; within the containing 128-bit block.
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UNSPEC_SVE_LANE_SELECT
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@ -558,6 +560,14 @@
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"mrs\t%x0, %1"
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)
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(define_insn "aarch64_read_sysregti"
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[(set (match_operand:TI 0 "register_operand" "=r")
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(unspec_volatile:TI [(match_operand 1 "aarch64_sysreg_string" "")]
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UNSPEC_SYSREG_RTI))]
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"TARGET_D128"
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"mrrs\t%x0, %H0, %x1"
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)
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(define_insn "aarch64_write_sysregdi"
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[(unspec_volatile:DI [(match_operand 0 "aarch64_sysreg_string" "")
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(match_operand:DI 1 "register_operand" "rZ")]
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@ -566,6 +576,14 @@
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"msr\t%0, %x1"
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)
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(define_insn "aarch64_write_sysregti"
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[(unspec_volatile:TI [(match_operand 0 "aarch64_sysreg_string" "")
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(match_operand:TI 1 "register_operand" "r")]
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UNSPEC_SYSREG_WTI)]
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"TARGET_D128"
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"msrr\t%x0, %x1, %H1"
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)
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(define_insn "indirect_jump"
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[(set (pc) (match_operand:DI 0 "register_operand" "r"))]
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""
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@ -344,6 +344,17 @@ __rndrrs (uint64_t *__res)
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#define __arm_wsrf64(__regname, __value) \
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__builtin_aarch64_wsrf64 (__regname, __value)
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#pragma GCC push_options
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#pragma GCC target ("+nothing+d128")
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#define __arm_rsr128(__regname) \
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__builtin_aarch64_rsr128 (__regname)
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#define __arm_wsr128(__regname, __value) \
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__builtin_aarch64_wsr128 (__regname, __value)
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#pragma GCC pop_options
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#ifdef __cplusplus
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}
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#endif
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