AArch64: support encoding integer immediates using floating point moves
This patch extends our immediate SIMD generation cases to support generating
integer immediates using floating point operation if the integer immediate maps
to an exact FP value.
As an example:
uint32x4_t f1() {
return vdupq_n_u32(0x3f800000);
}
currently generates:
f1:
adrp x0, .LC0
ldr q0, [x0, #:lo12:.LC0]
ret
i.e. a load, but with this change:
f1:
fmov v0.4s, 1.0e+0
ret
Such immediates are common in e.g. our Math routines in glibc because they are
created to extract or mark part of an FP immediate as masks.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_sve_valid_immediate,
aarch64_simd_valid_immediate): Refactor accepting modes and values.
(aarch64_float_const_representable_p): Refactor and extract FP checks
into ...
(aarch64_real_float_const_representable_p): ...This and fix fail
fallback from real_to_integer.
(aarch64_advsimd_valid_immediate): Use it.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/const_create_using_fmov.c: New test.
This commit is contained in:
Tamar Christina
parent
fc35079277
commit
87dc6b1992
2 changed files with 241 additions and 128 deletions
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@ -22899,19 +22899,19 @@ aarch64_advsimd_valid_immediate_hs (unsigned int val32,
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return false;
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}
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/* Return true if replicating VAL64 is a valid immediate for the
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/* Return true if replicating VAL64 with mode MODE is a valid immediate for the
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Advanced SIMD operation described by WHICH. If INFO is nonnull,
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use it to describe valid immediates. */
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static bool
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aarch64_advsimd_valid_immediate (unsigned HOST_WIDE_INT val64,
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scalar_int_mode mode,
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simd_immediate_info *info,
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enum simd_immediate_check which)
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{
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unsigned int val32 = val64 & 0xffffffff;
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unsigned int val16 = val64 & 0xffff;
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unsigned int val8 = val64 & 0xff;
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if (val32 == (val64 >> 32))
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if (mode != DImode)
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{
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if ((which & AARCH64_CHECK_ORR) != 0
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&& aarch64_advsimd_valid_immediate_hs (val32, info, which,
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@ -22924,9 +22924,7 @@ aarch64_advsimd_valid_immediate (unsigned HOST_WIDE_INT val64,
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return true;
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/* Try using a replicated byte. */
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if (which == AARCH64_CHECK_MOV
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&& val16 == (val32 >> 16)
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&& val8 == (val16 >> 8))
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if (which == AARCH64_CHECK_MOV && mode == QImode)
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{
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if (info)
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*info = simd_immediate_info (QImode, val8);
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@ -22954,28 +22952,15 @@ aarch64_advsimd_valid_immediate (unsigned HOST_WIDE_INT val64,
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return false;
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}
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/* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
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instruction. If INFO is nonnull, use it to describe valid immediates. */
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/* Return true if replicating IVAL with MODE gives a valid immediate for an SVE
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MOV instruction. If INFO is nonnull, use it to describe valid
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immediates. */
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static bool
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aarch64_sve_valid_immediate (unsigned HOST_WIDE_INT val64,
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aarch64_sve_valid_immediate (unsigned HOST_WIDE_INT ival, scalar_int_mode mode,
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simd_immediate_info *info)
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{
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scalar_int_mode mode = DImode;
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unsigned int val32 = val64 & 0xffffffff;
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if (val32 == (val64 >> 32))
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{
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mode = SImode;
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unsigned int val16 = val32 & 0xffff;
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if (val16 == (val32 >> 16))
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{
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mode = HImode;
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unsigned int val8 = val16 & 0xff;
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if (val8 == (val16 >> 8))
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mode = QImode;
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}
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}
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HOST_WIDE_INT val = trunc_int_for_mode (val64, mode);
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HOST_WIDE_INT val = trunc_int_for_mode (ival, mode);
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if (IN_RANGE (val, -0x80, 0x7f))
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{
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/* DUP with no shift. */
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@ -22990,7 +22975,7 @@ aarch64_sve_valid_immediate (unsigned HOST_WIDE_INT val64,
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*info = simd_immediate_info (mode, val);
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return true;
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}
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if (aarch64_bitmask_imm (val64, mode))
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if (aarch64_bitmask_imm (ival, mode))
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{
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/* DUPM. */
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if (info)
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@ -23071,6 +23056,91 @@ aarch64_sve_pred_valid_immediate (rtx x, simd_immediate_info *info)
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return false;
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}
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/* We can only represent floating point constants which will fit in
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"quarter-precision" values. These values are characterised by
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a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
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by:
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(-1)^s * (n/16) * 2^r
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Where:
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's' is the sign bit.
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'n' is an integer in the range 16 <= n <= 31.
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'r' is an integer in the range -3 <= r <= 4.
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Return true iff R represents a vale encodable into an AArch64 floating point
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move instruction as an immediate. Othewise false. */
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static bool
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aarch64_real_float_const_representable_p (REAL_VALUE_TYPE r)
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{
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/* This represents our current view of how many bits
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make up the mantissa. */
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int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
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int exponent;
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unsigned HOST_WIDE_INT mantissa, mask;
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REAL_VALUE_TYPE m;
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bool fail = false;
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/* We cannot represent infinities, NaNs or +/-zero. We won't
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know if we have +zero until we analyse the mantissa, but we
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can reject the other invalid values. */
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if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r)
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|| REAL_VALUE_MINUS_ZERO (r))
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return false;
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/* Extract exponent. */
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r = real_value_abs (&r);
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exponent = REAL_EXP (&r);
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/* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
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highest (sign) bit, with a fixed binary point at bit point_pos.
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m1 holds the low part of the mantissa, m2 the high part.
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WARNING: If we ever have a representation using more than 2 * H_W_I - 1
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bits for the mantissa, this can fail (low bits will be lost). */
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real_ldexp (&m, &r, point_pos - exponent);
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wide_int w = real_to_integer (&m, &fail, HOST_BITS_PER_WIDE_INT * 2);
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/* If the low part of the mantissa has bits set we cannot represent
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the value. */
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if (fail || w.ulow () != 0)
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return false;
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/* We have rejected the lower HOST_WIDE_INT, so update our
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understanding of how many bits lie in the mantissa and
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look only at the high HOST_WIDE_INT. */
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mantissa = w.elt (1);
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point_pos -= HOST_BITS_PER_WIDE_INT;
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/* We can only represent values with a mantissa of the form 1.xxxx. */
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mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
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if ((mantissa & mask) != 0)
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return false;
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/* Having filtered unrepresentable values, we may now remove all
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but the highest 5 bits. */
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mantissa >>= point_pos - 5;
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/* We cannot represent the value 0.0, so reject it. This is handled
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elsewhere. */
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if (mantissa == 0)
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return false;
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/* Then, as bit 4 is always set, we can mask it off, leaving
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the mantissa in the range [0, 15]. */
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mantissa &= ~(1 << 4);
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gcc_assert (mantissa <= 15);
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/* GCC internally does not use IEEE754-like encoding (where normalized
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significands are in the range [1, 2). GCC uses [0.5, 1) (see real.cc).
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Our mantissa values are shifted 4 places to the left relative to
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normalized IEEE754 so we must modify the exponent returned by REAL_EXP
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by 5 places to correct for GCC's representation. */
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exponent = 5 - exponent;
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return (exponent >= 0 && exponent <= 7);
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}
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/* Return true if OP is a valid SIMD immediate for the operation
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described by WHICH. If INFO is nonnull, use it to describe valid
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immediates. */
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@ -23124,20 +23194,6 @@ aarch64_simd_valid_immediate (rtx op, simd_immediate_info *info,
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else
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return false;
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scalar_float_mode elt_float_mode;
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if (n_elts == 1
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&& is_a <scalar_float_mode> (elt_mode, &elt_float_mode))
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{
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rtx elt = CONST_VECTOR_ENCODED_ELT (op, 0);
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if (aarch64_float_const_zero_rtx_p (elt)
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|| aarch64_float_const_representable_p (elt))
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{
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if (info)
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*info = simd_immediate_info (elt_float_mode, elt);
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return true;
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}
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}
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/* If all elements in an SVE vector have the same value, we have a free
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choice between using the element mode and using the container mode.
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Using the element mode means that unused parts of the vector are
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@ -23199,10 +23255,57 @@ aarch64_simd_valid_immediate (rtx op, simd_immediate_info *info,
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val64 |= ((unsigned HOST_WIDE_INT) bytes[i % nbytes]
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<< (i * BITS_PER_UNIT));
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/* Try encoding the integer immediate as a floating point value if it's an
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exact value. */
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scalar_float_mode fmode = DFmode;
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scalar_int_mode imode = DImode;
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unsigned HOST_WIDE_INT ival = val64;
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unsigned int val32 = val64 & 0xffffffff;
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if (val32 == (val64 >> 32))
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{
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fmode = SFmode;
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imode = SImode;
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ival = val32;
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unsigned int val16 = val32 & 0xffff;
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if (val16 == (val32 >> 16))
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{
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fmode = HFmode;
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imode = HImode;
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ival = val16;
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unsigned int val8 = val16 & 0xff;
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if (val8 == (val16 >> 8))
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{
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imode = QImode;
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ival = val8;
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}
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}
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}
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if (which == AARCH64_CHECK_MOV
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&& imode != QImode
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&& (imode != HImode || TARGET_FP_F16INST))
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{
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long int as_long_ints[2];
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as_long_ints[0] = ival & 0xFFFFFFFF;
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as_long_ints[1] = (ival >> 32) & 0xFFFFFFFF;
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REAL_VALUE_TYPE r;
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real_from_target (&r, as_long_ints, fmode);
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if (aarch64_real_float_const_representable_p (r))
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{
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if (info)
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{
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rtx float_val = const_double_from_real_value (r, fmode);
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*info = simd_immediate_info (fmode, float_val);
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}
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return true;
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}
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}
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if (vec_flags & VEC_SVE_DATA)
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return aarch64_sve_valid_immediate (val64, info);
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return aarch64_sve_valid_immediate (ival, imode, info);
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else
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return aarch64_advsimd_valid_immediate (val64, info, which);
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return aarch64_advsimd_valid_immediate (val64, imode, info, which);
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}
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/* Check whether X is a VEC_SERIES-like constant that starts at 0 and
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@ -25205,106 +25308,29 @@ aarch64_c_mode_for_suffix (char suffix)
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return VOIDmode;
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}
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/* We can only represent floating point constants which will fit in
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"quarter-precision" values. These values are characterised by
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a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
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by:
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(-1)^s * (n/16) * 2^r
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Where:
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's' is the sign bit.
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'n' is an integer in the range 16 <= n <= 31.
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'r' is an integer in the range -3 <= r <= 4. */
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/* Return true iff X can be represented by a quarter-precision
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/* Return true iff X with mode MODE can be represented by a quarter-precision
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floating point immediate operand X. Note, we cannot represent 0.0. */
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bool
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aarch64_float_const_representable_p (rtx x)
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{
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/* This represents our current view of how many bits
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make up the mantissa. */
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int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
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int exponent;
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unsigned HOST_WIDE_INT mantissa, mask;
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REAL_VALUE_TYPE r, m;
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bool fail;
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x = unwrap_const_vec_duplicate (x);
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machine_mode mode = GET_MODE (x);
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if (!CONST_DOUBLE_P (x))
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return false;
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if (GET_MODE (x) == VOIDmode
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|| (GET_MODE (x) == HFmode && !TARGET_FP_F16INST))
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if ((mode == HFmode && !TARGET_FP_F16INST)
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|| mode == BFmode)
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return false;
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r = *CONST_DOUBLE_REAL_VALUE (x);
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REAL_VALUE_TYPE r = *CONST_DOUBLE_REAL_VALUE (x);
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/* We cannot represent infinities, NaNs or +/-zero. We won't
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know if we have +zero until we analyse the mantissa, but we
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can reject the other invalid values. */
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if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r)
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|| REAL_VALUE_MINUS_ZERO (r))
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return false;
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/* For BFmode, only handle 0.0. */
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if (GET_MODE (x) == BFmode)
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return real_iszero (&r, false);
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/* Extract exponent. */
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r = real_value_abs (&r);
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exponent = REAL_EXP (&r);
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/* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
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highest (sign) bit, with a fixed binary point at bit point_pos.
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m1 holds the low part of the mantissa, m2 the high part.
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WARNING: If we ever have a representation using more than 2 * H_W_I - 1
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bits for the mantissa, this can fail (low bits will be lost). */
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real_ldexp (&m, &r, point_pos - exponent);
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wide_int w = real_to_integer (&m, &fail, HOST_BITS_PER_WIDE_INT * 2);
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/* If the low part of the mantissa has bits set we cannot represent
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the value. */
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if (w.ulow () != 0)
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return false;
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/* We have rejected the lower HOST_WIDE_INT, so update our
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understanding of how many bits lie in the mantissa and
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look only at the high HOST_WIDE_INT. */
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mantissa = w.elt (1);
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point_pos -= HOST_BITS_PER_WIDE_INT;
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/* We can only represent values with a mantissa of the form 1.xxxx. */
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mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
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if ((mantissa & mask) != 0)
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return false;
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/* Having filtered unrepresentable values, we may now remove all
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but the highest 5 bits. */
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mantissa >>= point_pos - 5;
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/* We cannot represent the value 0.0, so reject it. This is handled
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elsewhere. */
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if (mantissa == 0)
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return false;
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/* Then, as bit 4 is always set, we can mask it off, leaving
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the mantissa in the range [0, 15]. */
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mantissa &= ~(1 << 4);
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gcc_assert (mantissa <= 15);
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/* GCC internally does not use IEEE754-like encoding (where normalized
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significands are in the range [1, 2). GCC uses [0.5, 1) (see real.cc).
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Our mantissa values are shifted 4 places to the left relative to
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normalized IEEE754 so we must modify the exponent returned by REAL_EXP
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by 5 places to correct for GCC's representation. */
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exponent = 5 - exponent;
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return (exponent >= 0 && exponent <= 7);
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return aarch64_real_float_const_representable_p (r);
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}
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/* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
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immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
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output MOVI/MVNI, ORR or BIC immediate. */
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/* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR, BIC or
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FMOV immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether
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to output MOVI/MVNI, ORR or BIC immediate. */
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char*
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aarch64_output_simd_mov_immediate (rtx const_vector, unsigned width,
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enum simd_immediate_check which)
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87
gcc/testsuite/gcc.target/aarch64/const_create_using_fmov.c
Normal file
87
gcc/testsuite/gcc.target/aarch64/const_create_using_fmov.c
Normal file
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@ -0,0 +1,87 @@
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/* { dg-do compile } */
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/* { dg-additional-options "-march=armv9-a -Ofast" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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#include <arm_neon.h>
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/*
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** g:
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** fmov v0\.4s, 1\.0e\+0
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** ret
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*/
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float32x4_t g(){
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return vdupq_n_f32(1);
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}
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/*
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** h:
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** fmov v0\.4s, 1\.0e\+0
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** ret
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*/
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uint32x4_t h() {
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return vreinterpretq_u32_f32(g());
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}
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/*
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** f1:
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** fmov v0\.4s, 1\.0e\+0
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** ret
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*/
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uint32x4_t f1() {
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return vdupq_n_u32(0x3f800000);
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}
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/*
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** f2:
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** fmov v0\.4s, 1\.5e\+0
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** ret
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*/
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uint32x4_t f2() {
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return vdupq_n_u32(0x3FC00000);
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}
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/*
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** f3:
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** fmov v0\.4s, 1\.25e\+0
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** ret
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*/
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uint32x4_t f3() {
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return vdupq_n_u32(0x3FA00000);
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}
|
||||
|
||||
/*
|
||||
** f4:
|
||||
** fmov v0\.2d, 1\.0e\+0
|
||||
** ret
|
||||
*/
|
||||
uint64x2_t f4() {
|
||||
return vdupq_n_u64(0x3FF0000000000000);
|
||||
}
|
||||
|
||||
/*
|
||||
** fn4:
|
||||
** fmov v0\.2d, -1\.0e\+0
|
||||
** ret
|
||||
*/
|
||||
uint64x2_t fn4() {
|
||||
return vdupq_n_u64(0xBFF0000000000000);
|
||||
}
|
||||
|
||||
/*
|
||||
** f5:
|
||||
** fmov v0\.8h, 1\.5e\+0
|
||||
** ret
|
||||
*/
|
||||
uint16x8_t f5() {
|
||||
return vdupq_n_u16(0x3E00);
|
||||
}
|
||||
|
||||
/*
|
||||
** f6:
|
||||
** adrp x0, \.LC0
|
||||
** ldr q0, \[x0, #:lo12:\.LC0\]
|
||||
** ret
|
||||
*/
|
||||
uint32x4_t f6() {
|
||||
return vdupq_n_u32(0x4f800000);
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue