[SPARC] Add -mfsmuld option
Add the -mfsmuld option to control the generation of the FsMULd instruction. In general, this instruction is available in architecture version V8 and V9 CPUs with FPU. Some CPUs of this category do not support this instruction properly, e.g. AT697E, AT697F and UT699. Some CPUs of this category do not implement it in hardware, e.g. LEON3/4 with GRFPU-lite. gcc/ * config/sparc/sparc.c (dump_target_flag_bits): Dump MASK_FSMULD. (sparc_option_override): Honour MASK_FSMULD. * config/sparc/sparc.h (MASK_FEATURES): Add MASK_FSMULD. * config/sparc/sparc.md (muldf3_extend): Use TARGET_FSMULD. * config/sparc/sparc.opt (mfsmuld): New option. * doc/invoke.texi (mfsmuld): Document option. From-SVN: r250570
This commit is contained in:
Sebastian Huber
Sebastian Huber
parent
404f48ac88
commit
867ba4b9ff
6 changed files with 48 additions and 13 deletions
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@ -1,3 +1,12 @@
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2017-07-26 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* config/sparc/sparc.c (dump_target_flag_bits): Dump MASK_FSMULD.
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(sparc_option_override): Honour MASK_FSMULD.
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* config/sparc/sparc.h (MASK_FEATURES): Add MASK_FSMULD.
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* config/sparc/sparc.md (muldf3_extend): Use TARGET_FSMULD.
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* config/sparc/sparc.opt (mfsmuld): New option.
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* doc/invoke.texi (mfsmuld): Document option.
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2017-07-26 Marek Polacek <polacek@redhat.com>
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PR middle-end/70992
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@ -1304,6 +1304,8 @@ dump_target_flag_bits (const int flags)
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fprintf (stderr, "FLAT ");
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if (flags & MASK_FMAF)
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fprintf (stderr, "FMAF ");
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if (flags & MASK_FSMULD)
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fprintf (stderr, "FSMULD ");
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if (flags & MASK_FPU)
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fprintf (stderr, "FPU ");
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if (flags & MASK_HARD_QUAD)
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@ -1403,24 +1405,24 @@ sparc_option_override (void)
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const int disable;
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const int enable;
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} const cpu_table[] = {
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{ "v7", MASK_ISA, 0 },
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{ "cypress", MASK_ISA, 0 },
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{ "v7", MASK_ISA|MASK_FSMULD, 0 },
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{ "cypress", MASK_ISA|MASK_FSMULD, 0 },
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{ "v8", MASK_ISA, MASK_V8 },
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/* TI TMS390Z55 supersparc */
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{ "supersparc", MASK_ISA, MASK_V8 },
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{ "hypersparc", MASK_ISA, MASK_V8 },
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{ "leon", MASK_ISA, MASK_V8|MASK_LEON },
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{ "leon", MASK_ISA|MASK_FSMULD, MASK_V8|MASK_LEON },
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{ "leon3", MASK_ISA, MASK_V8|MASK_LEON3 },
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{ "leon3v7", MASK_ISA, MASK_LEON3 },
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{ "sparclite", MASK_ISA, MASK_SPARCLITE },
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{ "leon3v7", MASK_ISA|MASK_FSMULD, MASK_LEON3 },
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{ "sparclite", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE },
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/* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
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{ "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
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/* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
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{ "f934", MASK_ISA, MASK_SPARCLITE },
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{ "f934", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE },
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{ "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
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{ "sparclet", MASK_ISA, MASK_SPARCLET },
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{ "sparclet", MASK_ISA|MASK_FSMULD, MASK_SPARCLET },
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/* TEMIC sparclet */
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{ "tsc701", MASK_ISA, MASK_SPARCLET },
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{ "tsc701", MASK_ISA|MASK_FSMULD, MASK_SPARCLET },
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{ "v9", MASK_ISA, MASK_V9 },
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/* UltraSPARC I, II, IIi */
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{ "ultrasparc", MASK_ISA,
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@ -1511,6 +1513,12 @@ sparc_option_override (void)
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target_flags |= MASK_LONG_DOUBLE_128;
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}
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/* Enable the FsMULd instruction by default if not explicitly configured by
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the user. It may be later disabled by the CPU target flags or if
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!TARGET_FPU. */
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if (!(target_flags_explicit & MASK_FSMULD))
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target_flags |= MASK_FSMULD;
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/* Code model selection. */
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sparc_cmodel = SPARC_DEFAULT_CMODEL;
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@ -1603,11 +1611,11 @@ sparc_option_override (void)
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if (TARGET_VIS4B)
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target_flags |= MASK_VIS4 | MASK_VIS3 | MASK_VIS2 | MASK_VIS;
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/* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b and -mfmaf if
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/* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if
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FPU is disabled. */
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if (! TARGET_FPU)
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target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_VIS4
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| MASK_VIS4B | MASK_FMAF);
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| MASK_VIS4B | MASK_FMAF | MASK_FSMULD);
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/* -mvis assumes UltraSPARC+, so we are sure v9 instructions
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are available; -m64 also implies v9. */
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@ -1641,6 +1649,10 @@ sparc_option_override (void)
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if (sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc)
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sparc_fix_b2bst = 1;
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/* Disable FsMULd for the UT699 since it doesn't work correctly. */
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if (sparc_fix_ut699)
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target_flags &= ~MASK_FSMULD;
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/* Supply a default value for align_functions. */
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if (align_functions == 0)
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{
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@ -438,7 +438,8 @@ extern enum cmodel sparc_cmodel;
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/* Mask of all CPU feature flags. */
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#define MASK_FEATURES \
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(MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \
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+ MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_POPC + MASK_SUBXC)
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+ MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \
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+ MASK_POPC + MASK_SUBXC)
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/* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */
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#define TARGET_HARD_MUL \
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@ -6121,7 +6121,7 @@ visl")
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[(set (match_operand:DF 0 "register_operand" "=e")
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(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
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(float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
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"(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699"
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"TARGET_FSMULD"
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"fsmuld\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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@ -93,6 +93,10 @@ mfmaf
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Target Report Mask(FMAF)
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Use UltraSPARC Fused Multiply-Add extensions.
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mfsmuld
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Target Report Mask(FSMULD)
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Use Floating-point Multiply Single to Double (FsMULd) instruction.
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mpopc
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Target Report Mask(POPC)
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Use UltraSPARC Population-Count instruction.
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@ -1124,7 +1124,7 @@ See RS/6000 and PowerPC Options.
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-mv8plus -mno-v8plus -mvis -mno-vis @gol
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-mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol
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-mvis4 -mno-vis4 -mvis4b -mno-vis4b @gol
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-mcbcond -mno-cbcond -mfmaf -mno-fmaf @gol
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-mcbcond -mno-cbcond -mfmaf -mno-fmaf -mfsmuld -mno-fsmuld @gol
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-mpopc -mno-popc -msubxc -mno-subxc @gol
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-mfix-at697f -mfix-ut699 -mfix-ut700 -mfix-gr712rc @gol
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-mlra -mno-lra}
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@ -24069,6 +24069,15 @@ Fused Multiply-Add Floating-point instructions. The default is @option{-mfmaf}
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when targeting a CPU that supports such instructions, such as Niagara-3 and
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later.
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@item -mfsmuld
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@itemx -mno-fsmuld
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@opindex mfsmuld
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@opindex mno-fsmuld
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With @option{-mfsmuld}, GCC generates code that takes advantage of the
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Floating-point Multiply Single to Double (FsMULd) instruction. The default is
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@option{-mfsmuld} when targeting a CPU supporting the architecture versions V8
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or V9 with FPU except @option{-mcpu=leon}.
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@item -mpopc
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@itemx -mno-popc
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@opindex mpopc
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