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[PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

Browse source 
gcc/ChangeLog:

	* config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension on rv32.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test.
This commit is contained in:
Jin Ma 2024-09-18 08:56:23 -06:00 • committed by Jeff Law
parent 4b7e6d5faa
commit 85fcf74034
2 changed files with 18 additions and 7 deletions
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16
gcc/config/riscv/riscv.md
View file

@ -56,6 +56,8 @@
UNSPEC_FLT_QUIET
UNSPEC_FLE_QUIET
UNSPEC_COPYSIGN
UNSPEC_FMV_X_W
UNSPEC_FMVH_X_D
UNSPEC_RINT
UNSPEC_ROUND
UNSPEC_FLOOR
@ -2626,8 +2628,9 @@
(define_insn "movsidf2_low_rv32"
[(set (match_operand:SI 0 "register_operand" "= r")
(truncate:SI
(match_operand:DF 1 "register_operand" "zmvf")))]
(unspec:SI
[(match_operand:DF 1 "register_operand" "zmvf")]
UNSPEC_FMV_X_W))]
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmv.x.w\t%0,%1"
[(set_attr "move_type" "fmove")
@ -2636,11 +2639,10 @@
(define_insn "movsidf2_high_rv32"
[(set (match_operand:SI 0 "register_operand" "= r")
(truncate:SI
(lshiftrt:DF
(match_operand:DF 1 "register_operand" "zmvf")
(const_int 32))))]
[(set (match_operand:SI 0 "register_operand" "= r")
(unspec:SI
[(match_operand:DF 1 "register_operand" "zmvf")]
UNSPEC_FMVH_X_D))]
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmvh.x.d\t%0,%1"
[(set_attr "move_type" "fmove")

9
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c Normal file
View file

@ -0,0 +1,9 @@
/* Test that we do not have ice when compile */
/* { dg-do compile } */
/* { dg-options "-march=rv32gc_zfa -mabi=ilp32d -O2 -g" } */
unsigned int
foo (double a) {
unsigned int tt = *(unsigned long long *)&a & 0xffff;
return tt;
}